Power electronic assembly having power electronic devices embedded in a flip chip

Abstract

The present disclosure relates to a power electronic assembly having a power electronic device embedded in a flip chip. A power electronic assembly includes a circuit board assembly, the circuit board assembly including a plurality of conductive logic layers, a plurality of conductive power layers, and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive logic layers. The laminate includes a power electronic device assembly, the power electronic device assembly including a substrate and a power electronic device. The substrate includes a graphite layer and a metal layer encapsulating the graphite layer. A groove is formed in an outer surface of the metal layer. The power electronic device is engaged in the groove of the outer surface of the substrate. Each conductive logic layer is disposed at a first surface of the laminate, and each conductive power layer is disposed at a second surface of the laminate opposite to the first surface of the laminate.

Description

Technical Field

[0001] The present description relates generally to power electronic assemblies and, more particularly, to apparatus and methods for power electronic assemblies having low overall thermal resistance while achieving a compact package size. Background Art

[0002] The increasing use of electronic devices in vehicles is driving the need to make electronic systems more compact. One component of these electronic systems is power electronics, which can serve as switches in inverters. Due to the heat generated, power electronics require significant cooling.

[0003] Furthermore, conventional power electronic components include multiple layers formed from different materials, resulting in different expansion rates at the interfaces of each layer. Therefore, it is possible to provide the same number of layers on each side of the power electronic device to reduce cumulative stress and mitigate bending. However, this may require unnecessary additional layers, thereby increasing the overall footprint of the power electronic component. For at least these reasons, there is a need to improve the cooling of power electronic devices while maintaining a compact package size. Summary of the Invention

[0004] In one embodiment, a power electronic assembly includes a circuit board assembly, the circuit board assembly including a plurality of conductive logic layers; a plurality of conductive power layers; and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers. The laminate includes a power electronic device assembly, the power electronic device assembly including a substrate; and a power electronic device. The substrate includes a graphite layer; and a metal layer encapsulating the graphite layer, with a groove formed in an outer surface of the metal layer. The power electronic device is bonded within the groove on the outer surface of the substrate. Each conductive logic layer is disposed on a first surface of the laminate, and each conductive power layer is disposed on a second surface of the laminate, opposite the first surface of the laminate.

[0005] In another embodiment, a power electronic assembly includes a circuit board assembly, the circuit board assembly including a plurality of conductive logic layers; a plurality of conductive power layers; a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers; and a cold plate. The circuit board assembly is mounted to a surface of the cold plate. The laminate includes a power electronic device assembly, the power electronic device assembly including a substrate; and a power electronic device. The substrate includes a graphite layer; and a metal layer encapsulating the graphite layer, with a groove formed in an outer surface of the metal layer. The power electronic device is bonded within the groove on the outer surface of the substrate. A plurality of vias thermally couple each power electronic device to the plurality of conductive logic layers and the plurality of conductive power layers. Each conductive logic layer is disposed at a first surface of the laminate, and each conductive power layer is disposed at a second surface of the laminate opposite the first surface of the laminate.

[0006] In another embodiment, a method includes: disposing a first electrically insulating layer on a first surface of a cold plate; and disposing a circuit board assembly on the first electrically insulating layer opposite the cold plate. The circuit board assembly includes: a plurality of conductive logic layers; a plurality of conductive power layers; and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers. The laminate includes: a power electronic device assembly, the power electronic device assembly including: a substrate; and a power electronic device. The substrate includes: a graphite layer; and a metal layer encapsulating the graphite layer, with a groove formed in an outer surface of the metal layer. The power electronic device is engaged within the groove of the outer surface of the substrate. Each conductive logic layer is disposed at a first surface of the laminate, and each conductive power layer is disposed at a second surface of the laminate opposite the first surface of the laminate.

[0007] These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments illustrated in the accompanying drawings are illustrative and exemplary and are not intended to limit the subject matter defined in the claims. The following detailed description of the exemplary embodiments can be understood when read in conjunction with the following drawings, in which like structures are represented by like reference numerals, wherein:

[0009] Figure 1 schematically depicts a combined perspective view of a power electronics assembly including a cold plate and circuit board assembly according to one or more embodiments described and illustrated herein;

[0010] Figure 2 Schematically depicts a schematic diagram of a system according to one or more embodiments described and illustrated herein. Figure 1 An exploded perspective view of the power electronics components;

[0011] Figure 3 Schematically depicts a schematic diagram of a system according to one or more embodiments described and illustrated herein. Figure 1 A partial perspective view of a cold plate of a power electronic assembly;

[0012] Figure 4 schematically depicts an exploded perspective view of a power electronics assembly including a substrate and power electronics according to one or more embodiments described and illustrated herein;

[0013] Figure 5 Schematically depicts a schematic diagram of a system according to one or more embodiments described and illustrated herein. Figure 4 A cross-sectional view of a power electronic device assembly;

[0014] Figure 6 Schematically depicts a system including a Figure 5A partial perspective view of a laminate of a plurality of power electronic device assemblies;

[0015] Figure 7 Schematically depicts a circuit comprising a circuit board disposed between an upper conductive layer and a lower conductive layer according to one or more embodiments described and illustrated herein. Figure 6 a cross-sectional view of a portion of a laminate forming a circuit board assembly;

[0016] Figure 8 Schematically depicts a circuit disposed between a first conductive logic layer and a first conductive power layer according to one or more embodiments described and illustrated herein. Figure 7 a cross-sectional view of a partially formed circuit board assembly;

[0017] Figure 9 Schematically depicts a circuit board having a via formed therethrough according to one or more embodiments described and illustrated herein. Figure 8 a cross-sectional view of a partially formed circuit board assembly;

[0018] Figure 10 Schematically depicts a via filled in accordance with one or more embodiments described and illustrated herein. Figure 9 a cross-sectional view of a partially formed circuit board assembly;

[0019] Figure 11 Schematically depicts the formation of a Figure 1 The circuit board assembly is disposed between the second conductive logic layer and the second conductive power layer Figure 10 a cross-sectional view of a circuit board assembly; and

[0020] Figure 12 Schematically depicts a schematic diagram of a system according to one or more embodiments described and illustrated herein. Figure 1 Cross-sectional view of a power electronics component. DETAILED DESCRIPTION

[0021] Embodiments described herein are generally directed to a power electronics assembly having a circuit board assembly coupled to a cold plate. The circuit board assembly includes a flipped-down power electronics assembly, which may be referred to herein as a flip chip, including a substrate. Power electronics may be embedded within the substrate. As discussed herein, the flipped-down orientation of the power electronics assembly positions the power electronics embedded within the substrate toward the cold plate, rather than facing away from the cold plate.

[0022] The power electronics assembly of the present disclosure includes a power electronics device secured to a substrate. As described in greater detail below, the substrate includes a graphite layer that provides enhanced heat dissipation capabilities. Furthermore, embodiments of the present disclosure include one or more electrically insulating layers that electrically isolate the power electronics device from a cold plate. For example, the electrically insulating layer of the substrate enables the removal of an electrically insulating layer between a printed circuit board and a cold plate, as the substrate itself provides electrical isolation.

[0023] As described in more detail below, the substrates of the present disclosure provide enhanced thermal performance because the graphite layer promotes heat flux to the cold plate. The substrates described herein include stacked metal, graphite, and one or more electrically insulating layers in a compact package. The bonding materials described herein for bonding substrates are particularly well-suited for improved thermal conductivity while maintaining the ability to electrically insulate the substrate relative to other bonding techniques. The devices, systems, and apparatus described herein improve heat flux from the substrate to the cold plate, thereby improving heat spreading and cooling performance of the circuit board assembly.

[0024] The cold plates, power electronics assemblies, circuit board assemblies, power electronics assemblies, etc. described herein may be used in electrified vehicles (such as, but not limited to, electric vehicles, hybrid vehicles), any electric motors, generators, industrial tools, household appliances, etc. The various assemblies described herein may be electrically coupled to an electric motor and / or a battery and may be configured as an inverter circuit operable to convert direct current (DC) power to alternating current (AC) power.

[0025] As used herein, "power electronic device" refers to any electrical component used to convert DC power to AC power and vice versa. Embodiments may also be employed in AC-AC converter and DC-DC converter applications. Non-limiting examples of power electronic devices include power metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), thyristors, and power transistors.

[0026] As used herein, "fully embedded" means that every surface of the component is surrounded by the substrate. For example, when a power electronic device component is fully embedded by a circuit board substrate, it means that the circuit board substrate material covers every surface of the component. When one or more surfaces of the component are exposed, the component is "partially embedded."

[0027] As used herein, a "substrate" is a mounting substrate operable to be fixed to a power electronic device and includes one or more of a metal layer, a graphite layer, and an electrically insulating layer.

[0028] Various embodiments of the power electronics assembly, the power electronics device assembly, and the cold plate will be described in detail below.Where possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0029] Now refer to Figure 1 and Figure 2 , generally illustrating an example power electronics assembly 100 in assembled and exploded views, respectively. Figure 1 and Figure 2 The power electronic assembly 100 shown includes a cold plate 102 and a circuit board assembly 106. The cold plate 102 may be a power electronic device 140 (see FIG. 1 ) that is capable of being coupled to a substrate material of the circuit board assembly 106. Figure 4 ) Any device that removes heat flux. Non-limiting examples of cold plate 102 include a heat sink, a single-phase liquid cooling device, a two-phase liquid cooling device, and a vapor chamber. Figure 1 and Figure 2 The cold plate 102 is shown configured as a single phase liquid cooling device. The cold plate 102 includes a fluid chamber 115 ( Figure 12 ) fluid inlet 132 and fluid outlet 134 are fluidically coupled. Figure 1 and Figure 2 The fluid inlet 132 and the fluid outlet 134 are depicted as being located on the same side of the cold plate 102, but the present disclosure is not limited to such an embodiment. That is, in other embodiments, the fluid inlet 132 and the fluid outlet 134 may be located on other surfaces.

[0030] Reference again Figure 1 and Figure 2 The circuit board assembly 106 is coupled (eg, secured) to the first surface 107 of the cold plate 102 . Figure 1 and Figure 2 The circuit board assembly 106 is shown secured to the first surface 107 of the cold plate 102 by fasteners 101 (e.g., bolts and nuts) extending through through-holes 105 of the cold plate 102 and through-holes 109 of the circuit board assembly 106. It will be appreciated that in other embodiments, the through-holes 105, 109 and fasteners 101 may be omitted, as described below.

[0031] In an embodiment, the circuit board assembly 106 may be a 3D printed layer. It will be appreciated that in such an embodiment, the 3D printed layer of the circuit board assembly 106 reduces the overall thermal resistance. In an embodiment, the circuit board assembly 106 may be laminated to the cold plate 102. However, other additive manufacturing processes for securing the circuit board assembly 106 to the cold plate 102 are also contemplated and are within the scope of the present disclosure. Additionally, as described in greater detail herein, laser drilling may be used to form holes in the power electronics 140 ( Figure 4 ) and the various components of the circuit board assembly 106. That is, vias are drilled through the circuit board assembly 106 to the top surface of the power electronic device 140 and each conductive layer. As described in more detail herein, the vias are then filled with copper by electroplating to establish electrical connections between the components. Figure 1 and Figure 2 The circuit board assembly 106 is generally depicted in FIG, but the various layers and steps of the assembly are described in detail in FIG. Figures 7 to 12 Describe in.

[0032] Now refer to Figures 3 to 12 , depicts the various steps of manufacturing the power electronic component 100. Figure 3 As shown, a first electrically insulating layer 180 is shown deposited onto the first surface 107 of the cold plate 102 to reduce the contact between the circuit board assembly 106 ( Figure 1 ) and the cold plate 102. First electrically insulating layer 180 can generally be any layer that provides electrical insulation, such as ceramic. In one embodiment, first electrically insulating layer 180 comprises an insulated metal substrate (IMS) dielectric film. The IMS dielectric film can be a solid thin film layer. In other embodiments, first electrically insulating layer 180 can be a layer of thermal paste. Note that first electrically insulating layer 180 may not have dedicated through-holes.

[0033] Now refer to Figure 4 and Figure 5 , respectively, show an exploded bottom perspective view and a combined cross-sectional view of an example substrate 121. The substrate 121 includes a plurality of stacked layers. Specifically, Figure 4 and Figure 5 The illustrated substrate 121 includes a metal layer 122 and a graphite layer 124 embedded in the metal layer 122. The metal layer 122 includes an inner surface 125 and an outer surface 128 opposite the inner surface 125. In an embodiment, the metal layer 122 includes a first metal layer and a second metal layer, and the graphite layer 124 is located between the first metal layer and the second metal layer. The metal layer 122 includes a groove 127 provided in the outer surface 128 of the metal layer 122. The groove 127 is sized to receive the power electronic device 140. As described in more detail below, the metal layer 122 provides a conductive surface to which electrodes on the bottom surface of the power electronic device 140 are connected (e.g., by direct connection and / or through electrically connected vias). It should be understood that Figure 4 and Figure 5 The various layers of substrate 121 depicted in the figures are illustrative only. That is, for example, in some embodiments, substrate 121 may include multiple graphite layers and / or other layers disposed between metal layers. It should be understood that substrate 121 is an inverted substrate 121 such that, when positioned on cold plate 102, and as described in greater detail herein, power electronics 140 face in the direction of cold plate 102 (i.e., the -z direction of the coordinate axes depicted in the figures) rather than in the opposite direction (i.e., the +z direction of the coordinate axes).

[0034] Please note that Figure 4 and Figure 5 The substrate 121 in the embodiment includes a graphite layer 124 embedded in a metal layer 122 to provide a Figure 4 and Figure 5 The substrate 121 is symmetrical about the z-axis of the coordinate axis depicted in FIG. The symmetry of the substrate 121 balances the forces on the substrate 121 during the high temperature bonding process. Since the metal layer 122 and the graphite layer 124 have different thermal expansion coefficients, it is desirable to have a symmetrical substrate stack to balance the thermally induced stresses during the bonding process.

[0035] The metal layer 122 may be made of any suitable metal or alloy. As non-limiting examples, copper and aluminum may be used as the metal layer 122. The metal layer 122 of the substrate 121 has a groove 127 formed in an outer surface 128 thereof. The groove 127 may be formed by, for example, chemical etching. The groove 127 has a size and shape to accommodate the power electronic device 140. The outer surface 128 may generally be a second major surface or surface of the metal layer 122 opposite the inner surface 125 (configured as the first major surface or surface of the metal layer 122). That is, the metal layer 122 may be a planar layer whereby the inner surface 125 faces the graphite layer 124 and the opposing outer surface 128 faces the power electronic device 140 and the circuit board assembly 106 ( Figure 1 ).

[0036] Figure 5 The graphite layer 124 depicted in the embodiment of FIG is provided to promote heat diffusion both across the base plate 121 and toward the cold plate 102 (see, e.g., FIG. Figure 12 ). The crystal structure of graphite gives it high thermal conductivity, making it useful for conducting heat flux to the cold plate 102. However, graphite does not have an isothermal profile. Instead, graphite has an anisothermal profile, which has high thermal conductivity along two axes and low thermal conductivity along a third axis. To account for the anisothermal profile of graphite, the substrate 121 is designed to be rectangular, such that its length is greater than its width. Reference Figure 5 , the graphite layer 124 along Figure 5 The x- and z-axes, depicted as coordinate axes in FIG, have high thermal conductivity. Therefore, substrate 121 is designed so that its dimension along the x-axis is greater than its dimension along the y-axis. Heat flux will travel along both the x- and z-axes. As described in more detail below, substrate 121 will move heat flux along the x-axis toward cold plate 102. Heat flux will also travel along the z-axis toward cold plate 102.

[0037] Reference again Figure 4 , depicts an exploded view of a power electronics assembly 146 , including a substrate 121 and power electronics 140 . Figure 4The power electronic device 140 and the bonding layer 143 are depicted relative to the groove 127 of the substrate 121. For example, the bonding layer 143 can be a solder layer. As another example, the bonding layer 143 can be a transient liquid phase bonding layer 143. The power electronic device 140 includes a plurality of large electrodes 141 and a plurality of small electrodes 142 on the outward surface. The large electrodes 141 can be power electrodes, and the small electrodes 142 can be signal electrodes. It is worth noting that although Figure 4 Although not visible in the figure, the power electronic device 140 further includes one or more electrodes on the opposite, inward-facing surface. By placing the power electronic device 140 into the recess 127, the one or more electrodes on the inward-facing surface of the power electronic device 140 are electrically connected to the metal layer 122. Therefore, electrical connection to the electrodes on the inward-facing surface of the power electronic device 140 can be made through the metal layer 122.

[0038] As noted above, substrate 121 is a mounting substrate to which power electronics 140 is bonded. Substrate 121 provides a conductive surface area for making connections to electrodes on the inwardly facing surface of power electronics 140. Substrate 121 further provides a heat spreading function as well as electrical isolation.

[0039] Now refer to Figure 6 , shows a bottom perspective view of a laminate 200 including one or more power electronic components 146 surrounded by a laminate material 202. The laminate 200 will be in contact with the cold plate 102 ( Figure 3 ) are disposed oppositely on the first electrically insulating layer 180. In an embodiment, the laminate material 202 comprises FR-4, however, alternative materials are within the scope of the present disclosure. As shown, a total of six power electronic device assemblies 146 are disposed in two rows of three and bonded to the cold plate 102 via the first electrically insulating layer 180 and the laminate material 202. However, it should be understood that any number of power electronic device assemblies 146 may be used depending on the application.

[0040] Now refer to Figures 7 to 11 , depicting the various steps in forming the circuit board assembly 106. Specifically, referring to Figure 7 , shows a cross-sectional view of a laminate 200 including an upper conductive layer 206 and a lower conductive layer 208 defining a core layer 204. The upper conductive layer 206 is disposed at an upper surface 200a of the laminate 200, and the lower conductive layer 208 is disposed at an opposite lower surface 200b of the laminate 200. The upper conductive layer 206 has an upper surface 206a and a lower surface 206b opposite the upper surface 206a of the upper conductive layer 206. Similarly, the lower conductive layer 208 has an upper surface 208a and a lower surface 208b opposite the upper surface 208a of the lower conductive layer 208. Figure 7As shown and discussed herein, holes are formed in the core layer 204 and the power electronics assembly 146 is inserted into the corresponding holes. Accordingly, the power electronics 140 is exposed through the lower conductive layer 208.

[0041] Now refer to Figure 8 , the second electrically insulating layer 210 is disposed on the upper surface 206a of the upper conductive layer 206, and the third electrically insulating layer 212 is disposed on the lower surface 208b of the lower conductive layer 208. The second electrically insulating layer 210 has an upper surface 210a and a lower surface 210b opposite to the upper surface 210a of the second electrically insulating layer 210. Similarly, the third electrically insulating layer 212 has an upper surface 212a and a lower surface 212b opposite to the upper surface 212a of the third electrically insulating layer 212. As shown, the laminate 200 is disposed between the second electrically insulating layer 210 and the third electrically insulating layer 212. It should be understood that the second electrically insulating layer 210 and the third electrically insulating layer 212 may include layers that are substantially the same as the first electrically insulating layer 180 ( Figure 3 )Same materials. Still refer to Figure 8 A first conductive logic layer 216 is disposed on the upper surface 210a of the second electrically insulating layer 210, and a first conductive power layer 218 is disposed on the lower surface 212b of the third electrically insulating layer 212. In one embodiment, the first conductive logic layer 216 and the first conductive power layer 218 are copper layers. The first conductive logic layer 216 has an upper surface 216a and a lower surface 216b opposite the upper surface 216a of the first conductive logic layer 216. Similarly, the first conductive power layer 218 has an upper surface 218a and a lower surface 218b opposite the upper surface 218a of the first conductive power layer 218.

[0042] refer to Figure 9 , vias 112 (both conductive and thermal vias) are formed to extend between any combination of the first conductive power layer 218, the first conductive logic layer 216, and the power electronic devices 140 of the power electronic device assembly 146. For example, the vias 112 are shown extending between the first conductive logic layer 216 and the first conductive power layer 218. Additionally, the vias 112 are shown extending between the first conductive power layer 218 and the bottom surface 140b of the power electronic device 140 to electrically couple the first conductive logic layer 216 and the first conductive power layer 218 to the bottom surface 140b of the power electronic device 140. Additionally, the vias 112 are shown extending between the first conductive power layer 218 and the bottom surface 121b of the substrate 121 to electrically couple the first conductive logic layer 216 and the first conductive power layer 218 to the top surface 140a of the power electronic device 140. The vias 112 can be formed in any suitable manner, such as, for example, laser drilling. It should be understood that the scope of the present disclosure is not limited to Figure 9While the particular configuration of vias 112 is depicted in FIG, other configurations are contemplated based on the specific requirements of the circuit board assembly 106.

[0043] The vias 112 can provide drive signals to the power electronic device 140 and provide a current path for the switching current. It is worth noting that in some embodiments, some of the vias 112 can be configured as thermal vias, which do not conduct drive signals or switching current. In addition, the substrate arrangement allows flux to move from the power electronic device 140 through the substrate 121 to the cold plate 102 ( Figure 12 In this way, the heat flux flows from the power electronics 140 through the base plate 121 to the cold plate 102 in an optimal manner.

[0044] Now refer to Figure 10 The vias 112 are filled with copper by electroplating to form electrical connections between each power electronic component 146, the first conductive logic layer 216, and the first conductive power layer 218. However, it should be understood that the vias 112 may be filled by any other suitable means other than electroplating.

[0045] Now refer to Figure 11 , the first conductive logic layer 216 and the first conductive power layer 218 are etched into a designated pattern to guide current. Once the first conductive logic layer 216 and the first conductive power layer 218 are etched, repeat the above steps. Figures 8 to 10 The described steps result in a fourth electrical insulation layer 220 being disposed on the upper surface 216 a of the first conductive logic layer 216 and a fifth electrical insulation layer 222 being disposed on the lower surface 218 b of the first conductive power supply layer 218 .

[0046] Subsequently, a second conductive logic layer 224 is disposed on the upper surface 220a of the fourth electrically insulating layer 220 opposite the first conductive logic layer 216, and a second conductive power layer 226 is disposed on the lower surface 222b of the fifth electrically insulating layer 222 opposite the first conductive power layer 218. Thus, the first conductive logic layer 216 and the second conductive logic layer 224 are disposed on the upper side of the power electronics assembly 146, while the first conductive power layer 218 and the second conductive power layer 226 are disposed on the lower side of the power electronics assembly 146, opposite the upper side. In other words, the power electronics assembly 146 separates the first conductive logic layer 216 and the second conductive logic layer 224 from the first conductive power layer 218 and the second conductive power layer 226. Therefore, it should be understood that each conductive logic layer 216, 224 is located on one side of the power electronics assembly 146, while each conductive power layer 218, 226 is located on an opposite side of the power electronics assembly 146. Furthermore, no conductive logic layer 216 , 224 is adjacent to any conductive power layer 218 , 226 , and vice versa.

[0047] Next, additional vias 112 are formed through the second conductive logic layer 224 to the first conductive logic layer 216, and additional vias 112 are formed through the second conductive power layer 226 to the first conductive power layer 218. Figure 10 As discussed above, vias 112 are filled with copper by electroplating to form electrical connections between first and second conductive logic layers 216 and 224, and first and second conductive power layers 218 and 226. However, it should be understood that vias 112 may be filled by any other suitable means other than electroplating.

[0048] Still refer to Figure 11 , second conductive logic layer 224 and second conductive power layer 226 are similarly etched into designated patterns to guide current. It should be understood that second conductive logic layer 224 can be laminated to first conductive logic layer 216, and second conductive power layer 226 can be laminated to first conductive power layer 218 in a high-temperature, high-pressure chamber. During this lamination step, material from second electrically insulating layer 210 and fourth electrically insulating layer 220 fills the gaps defined by etching first conductive logic layer 216 and second conductive logic layer 224. Similarly, material from third electrically insulating layer 212 and fifth electrically insulating layer 222 fills the gaps defined by etching first conductive power layer 218 and second conductive power layer 226.

[0049] It should be understood that the circuit board assembly 106 may include any number of electrically insulating layers and conductive layers other than those depicted herein. However, in an embodiment, the circuit board assembly 106 includes the same number of conductive logic layers as the number of conductive power layers. Furthermore, each conductive logic layer is disposed on one side of the power electronics assembly 146 and each conductive power layer is disposed on the opposite side of the power electronics assembly 146. In doing so, the description herein regarding the Figures 8 to 11 The steps described are followed by laminating each additional layer to the previous layer.

[0050] Now refer to Figure 12 , depicts a cross-sectional view of a power electronics assembly 100, including a circuit board assembly 106 shown mounted to a cold plate 102 through a first electrically insulating layer 180. It should be understood that no conductive logic layer is disposed between the laminate 200 and the cold plate 102. Instead, only the conductive power layers 218, 226 are disposed between the laminate 200 and the cold plate 102, with the conductive logic layers 216, 224 located on opposite sides of the laminate 200. Furthermore, because each conductive power layer 218, 226 is disposed between the laminate 200 and the cold plate 102, no conductive power layer 218, 226 is disposed on a side of the laminate 200 opposite the cold plate 102. Thus, each conductive logic layer 216, 224 is separated from each conductive power layer 218, 226 by the laminate 200.

[0051] A benefit of separating the conductive logic layers 216, 224 from the conductive power layers 218, 226 is that the total number of layers in the circuit board assembly 106 can be reduced without increasing the overall footprint of the circuit board assembly 106. Additionally, because the conductive power layers 218, 226 provide reduced thermal resistance compared to the conductive logic layers 216, 224, this reduces the overall thermal resistance between the power electronics 140 and the cold plate 102. This also provides improved cooling performance for the circuit board assembly 106. Furthermore, because the conductive power layers 218, 226 are disposed on the same side of the laminate 200, loop inductance is reduced, thereby reducing losses and improving the efficiency of the circuit board assembly 106.

[0052] As shown, cooling fluid from a reservoir (not shown) (as depicted by movement arrow 135) flows into the fluid chamber 115 through the fluid inlet 132 and exits the fluid chamber 115 as warmed cooling fluid through the fluid outlet 134 before returning to the reservoir, such as after passing through a heat exchanger (not shown) to remove heat from the cooling fluid 135. Although not shown, an array of fins may be provided in the fluid chamber 115 to provide additional surface area for transferring heat to the cooling fluid 135.

[0053] Still refer to Figure 12 , one or more surface mounted electronic components 214 may be mounted to the second conductive logic layer 224. As described herein, the surface mounted electronic components 214 may include, for example, transistors, resistors, capacitors, etc. Thus, it should be understood that the circuit board assembly 106 includes at least the laminate 200 (including the plurality of power electronic device assemblies 146), as well as the first conductive logic layer 216, the second conductive logic layer 224, the first conductive power layer 218, the second conductive power layer 226, and the surface mounted electronic components 214.

[0054] Based on the above, it will be understood that what is defined herein is a power electronic component and a method for manufacturing the same. Specifically, the power electronic component disclosed herein includes a circuit board assembly, which includes a plurality of conductive logic layers, a plurality of conductive power layers, and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers. The laminate includes a power electronic device assembly, which includes a substrate and a power electronic device. The substrate includes a graphite layer and a metal layer wrapping the graphite layer. A groove is formed in the outer surface of the metal layer. The power electronic device is engaged in the groove of the outer surface of the substrate. Each conductive logic layer is disposed at a first surface of the laminate, and each conductive power layer is disposed at a second surface of the laminate opposite to the first surface of the laminate.

[0055] It is noted that the terms "substantially" and "approximately" may be used herein to represent the inherent degree of uncertainty that can be attributed to any quantitative comparison, value, measurement, or other representation. These terms are also used herein to represent the degree by which a quantitative representation may vary from a reference without resulting in a change in the basic function of the subject matter at issue.

[0056] While specific embodiments have been illustrated and described herein, it will be appreciated that various other changes and modifications may be made without departing from the scope of the claimed subject matter. Furthermore, while various aspects of the claimed subject matter have been described herein, these aspects need not necessarily be used in combination. Accordingly, the appended claims encompass all such changes and modifications within the scope of the claimed subject matter.

[0057] It will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments described herein without departing from the scope of the claimed subject matter. Therefore, this specification is intended to cover modifications and variations of the various embodiments described herein as long as such modifications and variations are within the scope of the claims and their equivalents.

Claims

1. A power electronic component comprising: Circuit board assembly, including: multiple conductive logic layers; a plurality of conductive power planes; and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers, the laminate comprising: Power electronic components, including: Substrate, including: a graphite layer; and a metal layer wrapping the graphite layer, forming grooves in an outer surface of the metal layer; and a power electronic device engaged within the recess of the outer surface of the substrate, Each conductive logic layer is disposed at a first surface of the laminate board, and each conductive power layer is disposed at a second surface of the laminate board opposite to the first surface of the laminate board.

2. The power electronic assembly of claim 1 , wherein the laminate comprises: laminated materials; as well as A plurality of power electronic device components are embedded within the laminate material. The power electronic assembly of claim 2 , wherein the laminate material comprises FR-4.

4. The power electronic component according to claim 1, wherein: The circuit board assembly further includes a plurality of vias extending through the plurality of conductive logic layers and the plurality of conductive power layers for thermally coupling the power electronic device to the plurality of conductive logic layers and the plurality of conductive power layers. The power electronic component according to claim 1 , wherein the length of the substrate is greater than the width of the substrate. 6 . The power electronic assembly of claim 1 , further comprising a cold plate, wherein the circuit board assembly is bonded to a surface of the cold plate via a first electrically insulating layer. 7 . The power electronics assembly according to claim 6 , wherein the power electronics of the power electronics assembly face in the direction of the cold plate.

8. The power electronics assembly of claim 6, wherein each of the plurality of electrically conductive power layers is disposed between the laminate and the cold plate.

9. The power electronics assembly of claim 6, wherein no conductive logic layer is disposed between the power electronics assembly and the cold plate.

10. The power electronics assembly of claim 6, wherein no conductive power plane is provided on a side of the power electronics assembly opposite the cold plate.

11. A power electronic component comprising: Circuit board assembly, including: multiple conductive logic layers; a plurality of conductive power planes; and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers, the laminate comprising: Power electronic components, including: Substrate, including: a graphite layer; and a metal layer wrapping the graphite layer, forming grooves in an outer surface of the metal layer; and power electronic devices engaged within the recesses of the outer surface of the substrate, a plurality of vias thermally coupling each power electronic device to the plurality of conductive logic layers and the plurality of conductive power layers; and a cold plate, the circuit board assembly being mounted to a surface of the cold plate, Each conductive logic layer is disposed at a first surface of the laminate board, and each conductive power layer is disposed at a second surface of the laminate board opposite to the first surface of the laminate board.

12. The power electronics assembly according to claim 11, wherein: The laminate comprises a laminate material; and The plurality of power electronic components are embedded within the laminate material. 13 . The power electronics assembly according to claim 11 , wherein the power electronics of the power electronics assembly face in the direction of the cold plate.

14. The power electronics assembly of claim 11, wherein each of the plurality of electrically conductive power layers is disposed between the laminate and the cold plate.

15. The power electronics assembly of claim 11, wherein no conductive logic layer is disposed between the power electronics assembly and the cold plate. 16 . The power electronics assembly of claim 11 , wherein no conductive power plane is provided on a side of the power electronics assembly opposite the cold plate.

17. A method comprising: providing a first electrically insulating layer on the first surface of the cold plate; A circuit board assembly is disposed on the first electrically insulating layer opposite the cold plate, the circuit board assembly comprising: multiple conductive logic layers; a plurality of conductive power planes; and a laminate disposed between the plurality of conductive logic layers and the plurality of conductive power layers, the laminate comprising: Power electronic components, including: Substrate, including: a graphite layer; and a metal layer wrapping the graphite layer, forming grooves in an outer surface of the metal layer; and a power electronic device engaged within the recess of the outer surface of the substrate, Each conductive logic layer is disposed at a first surface of the laminate board, and each conductive power layer is disposed at a second surface of the laminate board opposite to the first surface of the laminate board.

18. The method of claim 17, wherein the power electronics of the power electronics assembly face in the direction of the cold plate.

19. The method of claim 17, wherein no conductive logic layer is disposed between the power electronics assembly and the cold plate.

20. The method of claim 17, wherein no conductive power plane is provided on a side of the power electronics assembly opposite the cold plate.

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