A neural network dedicated in-memory computing readout device and control method thereof

Abstract

The present invention discloses a neural network dedicated in-memory calculation readout device and a control method thereof, which relates to the technical field of integrated circuit design. A current sensing circuit sequentially performs conductivity conversion, current reduction and current subtraction to obtain a processed current. An integral trigger circuit integrates an integral capacitor based on the processed current to obtain a total voltage, which is the sum of the integral voltage generated by the processed current of the current quantization cycle and the residual voltage of the previous quantization cycle. A positive counting pulse or a negative counting pulse is generated at the same time. When a bidirectional counter circuit receives a positive counting pulse or a negative counting pulse, the count value of the previous quantization cycle is increased by 1 or decreased by 1 to obtain the count value of the current quantization cycle. When the current quantization cycle is the last quantization cycle, the activation value of the current quantization cycle is determined according to the count value of the current quantization cycle. The present invention significantly reduces the quantization error by introducing a residual accumulation function.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low quantization error neural network dedicated in-memory calculation readout device and a control method thereof. Background Art

[0002] With the advent of the big data era, the amount of data generated globally is growing rapidly, of which more than 80% is unstructured data (images, voice, text, etc.). How to efficiently extract valuable information from massive amounts of unstructured data has become a challenge. Neural network accelerators based on in-memory computing use the array structure and physical properties of the memory array to implement in-situ computing within the storage unit. Due to its high parallelism and avoidance of data movement, it can achieve high-speed and energy-efficient vector matrix multiplication operations, and can efficiently extract valuable information from massive amounts of unstructured data. However, in order to achieve data flow between different layers, it is usually necessary to use analog-to-digital converters and post-processing circuits to quantize the results of the multiplication and accumulation (Vector matrix multiplication, VMM) operations of the memory array, which brings the following challenges: Figure 1 As shown, Figure 1 In the example, X is the input vector, W is the weight vector, X and W have the same dimensions, and a parameter x in X is i Corresponding to a weight value w in W i , because the input vector X dimension of the multiplication and accumulation operation in the neural network is usually large (the maximum dimension exceeds 4608), and the size of the memory array is limited (usually less than 256×256), the input vector of the neural network needs to be split into N parameter groups, each parameter group includes M parameters, and each parameter group in different arrays is weighted and summed with the weight value corresponding to each parameter in the parameter group to obtain a partial sum, and then the partial sum is summed and activated. At the same time, since each parameter includes multiple bits, and only 1 bit can be input each time, the process of weighted summing of each parameter group in different arrays with the weight value corresponding to each parameter in the parameter group also needs to be performed multiple times to obtain the partial sum of each bit, and then summed and activated, which will cause the quantization error generated in the process of multiple quantization and digital domain partial sum summing to accumulate errors, and as the number of splits increases, the quantization error also increases accordingly, such as Figure 2 As shown, as the number of bits increases, the quantization error also increases.

[0003] Based on this, there is an urgent need for a neural network-specific in-memory calculation readout device and a control method thereof that can reduce quantization errors. Summary of the invention

[0004] The object of the present invention is to provide a neural network dedicated in-memory calculation readout device and a control method thereof, which significantly reduces the quantization error by introducing a residual accumulation function.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A neural network dedicated in-memory calculation readout device, comprising: a current sensing circuit, an integral trigger circuit and a bidirectional counter circuit;

[0007] The input end of the current sensing circuit is connected to the bit line of the memory array; the current sensing circuit is used to convert the conductance of the positive weight and the conductance of the negative weight of the memory array in the current quantization cycle into the current of the positive weight and the current of the negative weight respectively, and reduce and subtract the current of the positive weight and the current of the negative weight to obtain the processed current of the current quantization cycle; the memory array is used to complete the neural network in-memory calculation; the conductance of the positive weight is the multiplication and accumulation result of the input value of the current quantization cycle and the positive weight, and the conductance of the negative weight is the multiplication and accumulation result of the input value of the current quantization cycle and the negative weight; the input value of the current quantization cycle is the nth bit of each parameter in a parameter group obtained by splitting the input vector, n=1, 2, ..., N, N is the total number of bits; the positive weight and the negative weight correspond to the parameters one by one, and the difference between the positive weight and the negative weight is equal to the weight value corresponding to the corresponding parameter; the number of quantization cycles is equal to the product of the total number of parameter groups obtained by splitting the input vector and the total number of bits included in the parameter;

[0008] The input end of the integration trigger circuit is connected to the output end of the current sensing circuit; the integration trigger circuit is used to integrate the integration capacitor based on the processed current of the current quantization cycle to obtain a total voltage, and when the total voltage reaches the positive threshold, generate a positive counting pulse, and discharge the integration capacitor at the same time, so that the total voltage decreases by a first preset value to obtain the residual voltage of the current quantization cycle; when the total voltage reaches the negative threshold, generate a negative counting pulse, and charge the integration capacitor at the same time, so that the total voltage increases by a second preset value to obtain the residual voltage of the current quantization cycle; when the total voltage does not reach the positive threshold and does not reach the negative threshold, the total voltage is used as the residual voltage of the current quantization cycle; the total voltage is the sum of the integrated voltage generated by the processed current of the current quantization cycle and the residual voltage of the previous quantization cycle; the first preset value is the difference between the positive threshold and the basic voltage of the integration capacitor; the second preset value is the difference between the basic voltage of the integration capacitor and the negative threshold; the basic voltage of the integration capacitor is greater than the negative threshold, and the basic voltage of the integration capacitor is less than the positive threshold;

[0009] The input end of the bidirectional counter circuit is connected to the output end of the integral trigger circuit; the bidirectional counter circuit is used to increase the count value of the previous quantization cycle by 1 when receiving the positive counting pulse, and decrease the count value of the previous quantization cycle by 1 when receiving the negative counting pulse, so as to obtain the count value of the current quantization cycle, and when the current quantization cycle is the last quantization cycle, determine the activation value of the current quantization cycle according to the count value of the current quantization cycle.

[0010] A control method for a neural network dedicated in-memory computing readout device, used to control the above-mentioned neural network dedicated in-memory computing readout device to work, comprising:

[0011] inputting the input value of the current quantization cycle into the memory array;

[0012] The current sensing circuit converts the positive-weighted conductance and the negative-weighted conductance of the memory array in the current quantization cycle into the positive-weighted current and the negative-weighted current, respectively, and reduces and subtracts the positive-weighted current and the negative-weighted current to obtain the processed current of the current quantization cycle;

[0013] The integral trigger circuit integrates the integral capacitor based on the processed current of the current quantization cycle to obtain a total voltage, and when the total voltage reaches a positive threshold, generates a positive counting pulse, and discharges the integral capacitor at the same time, so that the total voltage decreases by a first preset value, and obtains a residual voltage of the current quantization cycle; when the total voltage reaches a negative threshold, generates a negative counting pulse, and charges the integral capacitor at the same time, so that the total voltage increases by a second preset value, and obtains a residual voltage of the current quantization cycle; when the total voltage does not reach the positive threshold and does not reach the negative threshold, the total voltage is taken as the residual voltage of the current quantization cycle;

[0014] The bidirectional counter circuit increases the count value of the previous quantization cycle by 1 when receiving the positive counting pulse, and decreases the count value of the previous quantization cycle by 1 when receiving the negative counting pulse, so as to obtain the count value of the current quantization cycle;

[0015] Determine whether the current quantization cycle is the last quantization cycle; if so, the bidirectional counter circuit determines the activation value of the current quantization cycle according to the count value of the current quantization cycle; if not, return to the step of "inputting the input value of the current quantization cycle into the memory array".

[0016] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0017] The present invention provides a neural network dedicated in-memory calculation readout device and a control method thereof. A current sensing circuit converts the positive weighted conductance and the negative weighted conductance of the current quantization cycle into positive weighted current and negative weighted current respectively, and reduces and subtracts the positive weighted current and the negative weighted current to obtain the processed current of the current quantization cycle. An integral trigger circuit integrates an integral capacitor based on the processed current of the current quantization cycle to obtain a total voltage, which is the sum of the integral voltage generated by the processed current of the current quantization cycle and the residual voltage of the previous quantization cycle. When the total voltage reaches a positive threshold, a positive counting pulse is generated and the integral capacitor is discharged at the same time. When the total voltage reaches a negative threshold, a negative counting pulse is generated and the integral capacitor is charged at the same time. When a positive counting pulse is received, a bidirectional counter circuit increases the count value of the previous quantization cycle by 1, and when a negative counting pulse is received, the count value of the previous quantization cycle is reduced by 1 to obtain the count value of the current quantization cycle. When the current quantization cycle is the last quantization cycle, an activation value of the current quantization cycle is determined according to the count value of the current quantization cycle. The present invention can avoid quantization error caused by setting the residual voltage to zero for each quantization by retaining the residual voltage of the previous quantization cycle and summing it with the integrated voltage of the current quantization cycle, that is, significantly reducing the quantization error by introducing a residual accumulation function. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the implementation of the neural network VMM operation based on the memory array provided by the present invention.

[0020] Figure 2 A schematic diagram of the cumulative effect of quantization error caused by quantization and summation after splitting the VMM operation provided by the present invention, and a schematic diagram of the relationship curve between the quantization error and the number of splits; wherein, Figure 2 (a) is a schematic diagram of the cumulative effect of quantization error caused by the VMM operation being split and quantized and then summed; Figure 2 (b) is a schematic diagram of the relationship curve between quantization error and number of splits.

[0021] Figure 3 The basic principle and specific circuit design diagram of the readout device provided in Example 1 of the present invention; wherein, Figure 3 (a) is a schematic diagram of the basic principle; Figure 3(b) is a schematic diagram of the specific circuit design.

[0022] Figure 4 A circuit diagram of a current sensing circuit provided in Embodiment 1 of the present invention and a curve diagram of a relationship between an output current of a first current mirror and a conductance value of a memory array; wherein: Figure 4 (a) is a circuit diagram; Figure 4 (b) is a schematic diagram of the relationship curve between output current and conductance value.

[0023] Figure 5 A circuit diagram of a second current mirror for subtracting positive and negative weighted currents based on a common-source and common-gate current mirror design provided in Embodiment 1 of the present invention.

[0024] Figure 6 A schematic diagram of system overhead analysis provided in Example 1 of the present invention.

[0025] Figure 7 A schematic diagram comparing power consumption without sampling and holding and with sampling and holding provided in Embodiment 1 of the present invention.

[0026] Figure 8 A circuit diagram of an integral trigger circuit provided in Example 1 of the present invention.

[0027] Fig. 9 A comparison diagram of the conventional voltage-type reset and the charge-type reset provided in Embodiment 1 of the present invention; wherein: Fig. 9 (a) is a circuit diagram of a conventional voltage-type reset method and the corresponding expression of the relationship between the output frequency and the input current; Fig. 9 (b) is a circuit diagram of the charge-type reset method and the corresponding expression of the relationship between the output frequency and the input current.

[0028] Fig.10 This is a schematic diagram of the residual charge accumulation function provided in Example 1 of the present invention.

[0029] Fig.11 This is a schematic diagram of the relationship between the quantization accuracy of the readout device provided in Example 1 of the present invention and the energy consumption of a single quantization and the quantization time.

[0030] Fig.12 This is a circuit diagram of a bidirectional counter circuit provided in Example 1 of the present invention.

[0031] Fig.13 This is a schematic diagram of the functional simulation results of the bidirectional counter circuit provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] The object of the present invention is to provide a neural network dedicated in-memory calculation readout device and a control method thereof, which significantly reduces the quantization error by introducing a residual accumulation function.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Example 1

[0036] like Figure 3 As shown, a neural network-specific in-memory calculation and readout device in this embodiment includes: a current sensing circuit, an integration trigger circuit and a bidirectional counter circuit.

[0037] The input end of the current sensing circuit is connected to the bit line of the memory array. The current sensing circuit is used to convert the conductance of the positive weight and the conductance of the negative weight of the memory array in the current quantization cycle into the current of the positive weight and the current of the negative weight respectively, and reduce and subtract the current of the positive weight and the current of the negative weight to obtain the processed current of the current quantization cycle. Among them, the memory array is used to complete the neural network in-memory calculation. The conductance of the positive weight is the multiplication and accumulation result of the input value of the current quantization cycle and the positive weight, and the conductance of the negative weight is the multiplication and accumulation result of the input value of the current quantization cycle and the negative weight. The input value of the current quantization cycle is the nth bit of each parameter in a parameter group obtained by splitting the input vector, n=1, 2,..., N, N is the total number of bits. The positive weight and the negative weight correspond to the parameters one by one, and the difference between the positive weight and the negative weight is equal to the weight value corresponding to the corresponding parameter. The number of quantization cycles is equal to the product of the total number of parameter groups obtained by splitting the input vector and the total number of bits included in the parameter.

[0038] The input end of the integration trigger circuit is connected to the output end of the current sensing circuit. The integration trigger circuit is used to integrate the integration capacitor based on the processed current of the current quantization cycle to obtain the total voltage, and when the total voltage reaches the positive threshold, a positive counting pulse is generated, and the integration capacitor is discharged at the same time, so that the total voltage drops by a first preset value to obtain the residual voltage of the current quantization cycle; when the total voltage reaches the negative threshold, a negative counting pulse is generated, and the integration capacitor is charged at the same time, so that the total voltage rises by a second preset value to obtain the residual voltage of the current quantization cycle; when the total voltage does not reach the positive threshold and does not reach the negative threshold, the total voltage is the residual voltage of the current quantization cycle. The total voltage is the sum of the integrated voltage generated by the processed current of the current quantization cycle and the residual voltage of the previous quantization cycle. The first preset value is the difference between the positive threshold and the basic voltage of the integration capacitor. The second preset value is the difference between the basic voltage of the integration capacitor and the negative threshold. The basic voltage of the integration capacitor is greater than the negative threshold, and the basic voltage of the integration capacitor is less than the positive threshold.

[0039] The input end of the bidirectional counter circuit is connected to the output end of the integral trigger circuit. The bidirectional counter circuit is used to increase the count value (i.e., the quantization value) of the previous quantization cycle by 1 when receiving a positive counting pulse, and to decrease the count value of the previous quantization cycle by 1 when receiving a negative counting pulse, so as to obtain the count value of the current quantization cycle, and to determine the activation value of the current quantization cycle according to the count value of the current quantization cycle when the current quantization cycle is the last quantization cycle.

[0040] In this embodiment, the memory array is used to complete the in-memory calculation of the neural network, which can be called a resistive array or a memristor. The memory array includes multiple word lines, multiple bit lines, and multiple source lines. Considering that the memory array cannot store negative values, this embodiment defines positive weights and negative weights, both of which are non-negative numbers. The positive weight minus the negative weight equals the weight value. The positive weight is deployed on one bit line and the negative weight is deployed on another bit line to complete the deployment process of the weight value.

[0041] Considering that the dimension of the input vector is much larger than the dimension of the memory array, and each parameter of the input vector includes multiple bits, the present embodiment first splits the input vector into multiple parameter groups, each parameter group includes several parameters, and then splits each parameter to obtain multiple bits, one bit of each parameter of a parameter group constitutes an input value, that is, the input value is the nth bit of each parameter in a parameter group obtained by splitting the input vector, n=1, 2, ..., N, N is the total number of bits. Therefore, the total number of input values ​​is equal to the product of the total number of parameter groups obtained by splitting the input vector and the total number of bits included in the parameter. Based on the above splitting process, the present embodiment defines multiple quantization cycles, and one input value is input in each quantization cycle, so the number of quantization cycles is also equal to the product of the total number of parameter groups obtained by splitting the input vector and the total number of bits included in the parameter.

[0042] In each quantization cycle, the weight value deployment process of the bit lines with positive weights and the bit lines with negative weights is first performed, and then the input value is input to the word line of the memory array, so that the memory array completes the weighted summation process of each value in the input value and the positive weight corresponding to the value, and obtains the conductance of the positive weight. At the same time, the memory array completes the weighted summation process of each value in the input value and the negative weight corresponding to the value, and obtains the conductance of the negative weight. It should be noted that a value represents the nth bit of a parameter, and the positive weight and negative weight corresponding to a value are the positive weight and negative weight corresponding to the parameter.

[0043] The input end of the current sensing circuit is connected to the bit line of the memory array, specifically connected to the bit line with positive weight and the bit line with negative weight in the memory array. The current sensing circuit is used to measure the conductivity R of the positive weight in the memory array. POS and the negatively weighted conductance R NEG Read out and convert into positive weighted current I P and negative weight current I N , and then the positive weighted current and the negative weighted current are proportionally reduced and subtracted to obtain the processed current, and the processed current is passed to the integral trigger circuit.

[0044] like Figure 4 As shown in (a), since the devices in the memory array store conductance values, and the conventional ADC processes the quantization of voltage values ​​or current values, in order to facilitate the subsequent processing of the quantization circuit, the conductance value needs to be converted into a current value first. In this embodiment, an operational amplifier is used to maintain the voltage at one end of the bit line of the memory array at a stable voltage (such as 0.2V), and the other end of the bit line of the memory array is connected to 0V, so that the positive weighted conductance and negative weighted conductance stored on the memory array will be respectively converted into a current value with a positive weight. P and negative weight current IN Specifically, a preset voltage V is applied to the non-inverting input terminal of the operational amplifier. READ (usually set to 0.2V), according to the virtual short characteristic of the operational amplifier, the voltage at its inverting input will also be maintained at V READ Since one end of the memory array is grounded and the other end is connected to the inverting input of the operational amplifier, a voltage difference V will be generated across the two ends of the memory array. READ , thus generating a current V READ / R, where R is the resistance of the memory array. When calculating the current of the positive weight, R is the reciprocal of the conductance of the positive weight. When calculating the current of the negative weight, R is the reciprocal of the conductance of the negative weight. Since the memory array stores both positive and negative weights, two array currents are generated (i.e., the current of the positive weight I P and negative weight current I N ), the direction of the array current is from VDD to the memory array through the first current mirror input terminal.

[0045] Since the current output by the memory array is in the order of hundreds of microamperes during the neural network operation, the current is too large for the subsequent integral trigger circuit to process directly. Therefore, the first current mirror is used to reduce the array current output by the memory array by A times and then transmit it to the integral trigger circuit for processing. This embodiment can also adjust the bias voltage V of the first current mirror in the current sensing circuit. BIAS To control the output current of the first current mirror (i.e. the positive weighted reduced current I P and the negative weighted reduced current I N ), the relationship curve between the output current of the first current mirror and the conductance value of the memory array is as follows: Figure 4 (b) as shown.

[0046] like Figure 5 As shown in the figure, it is a schematic diagram of the circuit for realizing the positive and negative current subtraction function by using a current mirror in the current sensing circuit. The current I is sampled by the first current mirror and reduced by A times. P and I N The positive and negative currents are subtracted by a current subtractor based on a common-source and common-gate current mirror to obtain a processed current. This processed current becomes the output current of the current sensing circuit and is input into the integration trigger circuit.

[0047] In this embodiment, the current sensing circuit includes: an operational amplifier, a first current mirror and a second current mirror.

[0048] The non-inverting input terminal of the operational amplifier is connected to a preset voltage, the inverting input terminal of the operational amplifier is connected to one end of the bit line of the memory array, the other end of the bit line of the memory array is grounded, the output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier, and the inverting input terminal of the operational amplifier is the input terminal of the current sensing circuit. The operational amplifier is used to convert the positive weighted conductance and the negative weighted conductance of the memory array in the current quantization cycle into positive weighted current and negative weighted current respectively.

[0049] The input end of the first current mirror is connected to the output end of the operational amplifier. The first current mirror is used to reduce the positive weighted current and the negative weighted current respectively to obtain the reduced positive weighted current and the reduced negative weighted current. It should be noted that the ratio of the positive weighted current to be reduced is the same as the ratio of the negative weighted current to be reduced, that is, the positive weighted current and the negative weighted current are reduced in equal proportion.

[0050] The input end of the second current mirror is connected to the output end of the first current mirror, and the output end of the second current mirror is the output end of the current sensing circuit. The second current mirror is used to subtract the positive weighted reduced current from the negative weighted reduced current to obtain the processed current of the current quantization cycle.

[0051] In this embodiment, both the first current mirror and the second current mirror may be cascode current mirrors.

[0052] like Figure 6 As shown, the huge power consumption and area overhead caused by the analog-to-digital converter and the post-processing circuit undermine the system efficiency. In order to solve this problem, the present embodiment is designed with a sample-and-hold function. Specifically, since applying a voltage to the memory array will generate a large DC power consumption, in order to solve this problem, the present embodiment realizes the sample-and-hold function by controlling the opening and closing of the transmission gate in the current sensing circuit. Sampling refers to the process of applying a voltage to the memory array to generate a positive-weighted current and a negative-weighted current, and inputting the current sensing circuit. It usually takes about 10ns for the read current of the input current sensing circuit (that is, the positive-weighted current and the negative-weighted current) to stabilize; holding means that after the read current is stable, the current sensing circuit stores the size of the read current and no longer applies voltage to the memory array, thereby reducing DC power consumption. The implementation principle of the above-mentioned sample-and-hold function is as follows: Figure 4As shown in (a), during sampling, the SAMPLE signal is high, the transfer gate (TG) is opened, and the current at the input end on the left side of the first current mirror can be copied to the output end on the right side of the first current mirror; when the read current at the output end of the first current mirror reaches stability about 10ns after sampling, the SAMPLE signal switches to a low level, and the transfer gate is turned off. At this time, the current change at the input end on the left side of the first current mirror no longer affects the current at the output end on the right side of the first current mirror, and the current at the output end on the right side of the first current mirror will remain in a stable state. At this time, the voltage V is no longer applied to the memory array. READ The sampling and holding function can effectively reduce the read power consumption of the memory array. Figure 7 shown.

[0053] More specifically, the implementation process of the sample and hold function is as follows: the SAMPLE signal is set to a high level, and the transmission gate in the current sensing circuit is turned on, thereby transmitting the gate voltage at the input end of the first current mirror to the gate voltage at the output end of the first current mirror. In this way, since the input and output ends of the first current mirror have the same voltage and are both in the saturation working area, the current at the output end of the first current mirror will follow the current change at the input end of the first current mirror. When the SAMPLE signal is pulled high for about 10ns, the current at the output end of the first current mirror can be stable. At this time, the SAMPLE signal can be pulled low and the transmission gate can be closed. Due to the sample and hold function, the current at the output end of the first current mirror will remain unchanged, and thus will not affect the accuracy of subsequent calculations. At the same time, the voltage V READ Set to 0V to stop generating array current, thereby reducing array power consumption.

[0054] In this embodiment, the current sensing circuit further includes: a transmission gate. One end of the transmission gate is connected to the input end of the first current mirror, and the other end of the transmission gate is connected to the output end of the first current mirror. The transmission gate is used to close when the duration of the first current mirror receiving the current of the positive weight and the current of the negative weight reaches a first preset duration, and the first preset duration may be 10ns.

[0055] The input end of the integration trigger circuit is connected to the output end of the current sensing circuit. The integration trigger circuit is used to integrate the processed current of the current quantization cycle on the integration capacitor to obtain a total voltage, which is the integrated voltage generated by the processed current of the current quantization cycle and the residual voltage Q of the previous quantization cycle. RESIDUAL When the voltage on the integrating capacitor (i.e., the total voltage) reaches the positive threshold or the negative threshold, a positive counting pulse or a negative counting pulse is generated according to the direction of the trigger threshold. The positive counting pulse and the negative counting pulse are captured by the subsequent bidirectional counter circuit for counting, and a negative or positive reset charge Q is generated on the other hand.RESET , to reset the voltage on the integrating capacitor, that is, when the total voltage reaches the positive threshold, a positive counting pulse is generated, and a negative reset charge is generated at the same time to discharge the integrating capacitor, so that the total voltage drops by a first preset value, and the residual voltage of the current quantization cycle is obtained, and the first preset value is the difference between the positive threshold and the basic voltage of the integrating capacitor; when the total voltage reaches the negative threshold, a negative counting pulse is generated, and a positive reset charge is generated at the same time to charge the integrating capacitor, so that the total voltage rises by a second preset value, and the residual voltage of the current quantization cycle is obtained, and the second preset value is the difference between the basic voltage of the integrating capacitor and the negative threshold; when the total voltage does not reach the positive threshold and does not reach the negative threshold, the residual voltage of the current quantization cycle is obtained.

[0056] like Figure 8 As shown, the input of the integral trigger circuit is the processed current output by the current sensing circuit. According to the current direction of the processed current of the current sensing circuit, the processed current output by the current sensing circuit will charge or discharge the integral capacitor. Taking charging as an example, when the upper plate voltage of the integral capacitor exceeds the positive threshold V TH+ When the output of the first voltage comparator is reversed, the first monostable circuit is triggered to generate a pulse signal T with a fixed width. RESET (i.e., a positive counting pulse), this pulse signal turns on the NMOS below (i.e., the first switch tube), thereby causing the upper plate of the integrating capacitor to generate a discharge current I through the first current source. RESET Since the first current source is turned on for a period of time determined by T RESET Controlled and I RESET is constant, so the discharge amount of the upper plate of the integrating capacitor is T RESET *I RESET , the voltage of the integrating capacitor will be discharged to V TH+ Below, under the action of the charging current, the voltage on the upper plate of the integrating capacitor will exceed V TH+ , and the next discharge is performed, and the above process is repeated continuously. The discharge situation is similar to the above charging situation, and will not be repeated here. For example, the capacitance of the integral capacitor is set to 100fF, and the positive threshold voltage V TH+ Set to 1.1V, the negative threshold voltage V TH- The reset current I generated by the first current source and the second current source is set to 0.7V, the pulse width of the first monostable circuit and the second monostable circuit is about 0.4ns, and the reset current I generated by the first current source and the second current source is about 0.4ns. RESET It is 50uA.

[0057] In this embodiment, the integration trigger circuit includes: an integration capacitor, a first voltage comparator, a first monostable circuit, a first switch tube, a first current source, a second voltage comparator, a second monostable circuit, a second switch tube and a second current source.

[0058] One end of the integrating capacitor is grounded, and the other end of the integrating capacitor is respectively connected to the inverting input end of the first voltage comparator, the output end of the first current source, the inverting input end of the second voltage comparator, and the output end of the second current source, and the other end of the integrating capacitor is the input end of the integrating trigger circuit. The integrating capacitor is used to integrate the processed current based on the current quantization cycle to obtain the total voltage.

[0059] The non-inverting input terminal of the first voltage comparator is connected to the positive threshold value. The first voltage comparator is used to generate a falling edge when the total voltage reaches the positive threshold value, that is, when the total voltage is greater than the positive threshold value.

[0060] The input end of the first monostable circuit is connected to the output end of the first voltage comparator. The first monostable circuit is used to generate a positive counting pulse when receiving a falling edge.

[0061] The first switch tube is connected to the output end of the first monostable circuit and is used to be turned on when a positive counting pulse is received.

[0062] The input end of the first current source is connected to the first switch tube. The first current source is used to discharge the integral capacitor when the first switch tube is turned on, so that the total voltage drops by a first preset value to obtain the residual voltage of the current quantization cycle, and the residual voltage of the current quantization cycle refers to the voltage remaining after the total voltage on the integral capacitor drops by the first preset value.

[0063] The positive phase input terminal of the second voltage comparator is connected to the negative threshold value. The second voltage comparator is used to generate a rising edge when the total voltage reaches the negative threshold value, that is, when the total voltage is less than the negative threshold value.

[0064] The input end of the second monostable circuit is connected to the output end of the second voltage comparator. The second monostable circuit is used to generate a negative counting pulse when receiving a rising edge.

[0065] The second switch tube is connected to the output end of the second monostable circuit and is used to be turned on when a negative counting pulse is received.

[0066] The input end of the second current source is connected to the second switch tube. The second current source is used to charge the integration capacitor when the second switch tube is turned on, so that the total voltage rises by a second preset value to obtain the residual voltage of the current quantization cycle, and the residual voltage of the current quantization cycle refers to the voltage remaining after the total voltage on the integration capacitor rises by the second preset value.

[0067] The output end of the first monostable circuit and the output end of the second monostable circuit constitute the output end of the integration trigger circuit.

[0068] The function of the integral trigger circuit is to convert the processed current output by the current sensing circuit into a positive counting pulse or a negative counting pulse, and the frequency of the generated positive counting pulse or negative counting pulse is proportional to the magnitude of the processed current input. The integral trigger circuit proposed in this embodiment has two characteristics, charge type reset and residual amount retention.

[0069] The integral trigger circuit of this embodiment has a charge-type reset function. The traditional integral trigger circuit uses a voltage-type reset, which leads to serious nonlinearity, while the charge-type reset proposed in this embodiment has better linearity. The comparison between the two is as follows: Fig. 9 As shown, Fig. 9 In, f OUT is the output frequency of the generated pulse signal (positive counting pulse or negative counting pulse), I IN is the input current (i.e. the processed current), C is the capacitance, V th is the preset threshold of the voltage comparator, T DELAY is the delay time of the voltage comparator. Fig. 9 The simulation shows the relationship between the output frequency and input current of the integral trigger circuit using charge-type reset and voltage-type reset under the same voltage comparator power consumption. It can be seen that the linearity of the relationship between the output frequency and input current of the integral trigger circuit using charge-type reset is better, and as the input current increases, the increase in the output frequency of the charge-type reset method relative to the voltage-type reset method gradually increases, and the increase in the output frequency reaches 110% when the input current is the largest.

[0070] The integral trigger circuit in this embodiment also has a residual quantity holding function. Fig.10The residual charge accumulation function is demonstrated. In the traditional integral trigger circuit, the charge on the integral capacitor is cleared through a zeroing operation between multiple quantization cycles, so that different quantization cycles are independent of each other and have the same initial conditions. This is common and necessary for ADCs for traditional purposes, because multiple quantization processes should be guaranteed not to interfere with each other. However, in neural network applications, the quantization results of multiple quantization cycles may be the partial sum of the overall VMM operation results, and the final operation result is obtained by adding these partial sums. The charges cleared in each quantization cycle are also part of the operation result, but they are not quantized because the minimum accuracy of the integral trigger circuit is not reached. This is the source of the quantization error caused by the ADC accuracy limitation. If these residual charges are discarded in each quantization cycle, the final operation result will be the result of the quantization and addition of the partial sum results of each calculation, which will lead to the accumulation of quantization errors of each partial sum quantization result. The residual charge accumulation function designed in this embodiment can keep the charge that does not reach the trigger threshold in the previous quantization cycle when facing multiple quantization operations that need to be summed in the end, and add it to the result of the next quantization cycle, so that the residual charge that does not reach the threshold can participate in the accumulation of the next quantization cycle. By introducing the residual charge accumulation function, the circuit can realize the function of summing all the partial sum results in the charge domain and then quantizing them when processing the quantization of multiple partial sums, so that the final operation result only introduces one quantization error. That is, in order to solve the error accumulation problem caused by adding in the digital domain after multiple quantizations, this embodiment designs a residual charge accumulation function, that is, when the quantization results of two quantization cycles of the readout device need to be added, the residual charge (i.e., residual voltage) that does not reach the trigger threshold (positive threshold or negative threshold) on the integral capacitor at the end of the previous quantization cycle can be kept, and then can be accumulated in the next quantization cycle, avoiding the quantization error caused by the abandonment of this part of the charge, and achieving the effect of reducing the cumulative error introduced by adding after multiple quantizations.

[0071] In different layers of a neural network, the quantization accuracy requirements for the operation results are not consistent. Usually, the first few layers of a neural network require higher quantization accuracy, while the subsequent layers require relatively lower quantization accuracy. However, the design of traditional ADCs usually cannot flexibly adjust the quantization accuracy. To solve this problem, this embodiment adjusts the working time T of the integral trigger circuit. ADC_EN , it is possible to conveniently control the number of pulses that the circuit can generate, and then adjust the quantization accuracy of the integral trigger circuit, so as to adjust the quantization accuracy according to different neural network requirements, and realize adjustable quantization accuracy, that is, it is possible to control the accuracy of the quantization of the current value, and realize flexible control of the quantization accuracy of the readout device.

[0072] Fig.11The accuracy of the readout device and the energy consumption of a single quantization corresponding to different quantization times are demonstrated. As the quantization time increases, the accuracy of the readout device can be improved, but the corresponding energy consumption for a single quantization also increases. This feature proves that the readout device has configurable quantization accuracy. Therefore, in an actual neural network system based on a memory array, for neural networks that require higher quantization accuracy or certain network layers in the neural network, a longer quantization time of the readout device can be used to exchange higher power consumption for higher quantization accuracy; and for neural networks with lower quantization accuracy requirements or certain network layers in the neural network, the quantization accuracy of the readout device can be flexibly reduced to save time and energy consumption in the quantization process, and to achieve more efficient neural network operations without reducing the network recognition accuracy.

[0073] In this embodiment, the integration trigger circuit further includes: a third switch tube, which is located between the other end of the integration capacitor and the inverting input end of the first voltage comparator, the output end of the first current source, the inverting input end of the second voltage comparator, and the output end of the second current source. The third switch tube is used to disconnect when the working time of the integration capacitor reaches a second preset time. The second preset time is determined according to the user's required quantization accuracy and the number of bits n of the input value of the current quantization cycle. The higher the user's required quantization accuracy, the higher the reference time. The second preset time is the product of the reference time and 2 to the power of n-1, thereby achieving adjustable quantization accuracy and completing the shift-add function that the post-processing circuit can complete.

[0074] In this embodiment, the integration trigger circuit further includes: a fourth switch tube, which is connected in parallel with the integration capacitor and is used to clear the charge of the integration capacitor.

[0075] After receiving the pulse signal (i.e., positive counting pulse or negative counting pulse), the bidirectional counter circuit will add or subtract one to the count value originally stored in the bidirectional counter circuit according to the pulse signal. After completing all quantization and obtaining the final operation result, the bidirectional counter circuit processes the stored data (i.e., count value) and finally outputs the result of nonlinear activation after being processed by the ReLU function. Therefore, the integral trigger circuit and the bidirectional counter circuit jointly complete the function of ADC that converts the input current into a digital quantity.

[0076] The function of the bidirectional counter circuit is to count the positive and negative pulse signals generated by the integral trigger circuit within a certain period of time, and the final counting result of the bidirectional counter circuit is the quantization result of the readout device. In order to count the pulse signal generated by the integral trigger circuit, a bidirectional counter circuit is required. Traditional pulse counting circuits usually use traveling wave counters to realize the function of pulse counting, but the traveling wave counter can only realize unidirectional counting of pulses, that is, after each pulse is received, the value stored in the traveling wave counter is increased by one. Therefore, in order to process the positive and negative counting pulses generated by the integral trigger circuit, two sets of traveling wave counters are required, and a subtractor is required to process the output results of the two sets of traveling wave counters to realize the output of the final calculation result. Based on this, the present embodiment designs a bidirectional counter circuit that can count the positive and negative counting pulses in both directions, that is, when the bidirectional counter circuit receives a positive counting pulse, it adds one to the originally stored value, and when it receives a negative counting pulse, it subtracts one from the originally stored value, and negative numbers are represented in the form of complement code. The bidirectional counter circuit of this embodiment is as follows Fig.12 The circuit function simulation results are shown in Fig.13 shown.

[0077] The function of the bidirectional counter circuit is to record the number of positive counting pulses or negative counting pulses generated by the integral trigger circuit and output it in the form of binary complement. For each positive counting pulse input, the count of the bidirectional counter circuit will increase by 1, and for each negative counting pulse input, the count of the bidirectional counter circuit will decrease by 1. During the quantization process of the readout device, the integral trigger circuit will continue to generate positive counting pulses or negative counting pulses, so the output of the bidirectional counter circuit will continue to increase or decrease. After the quantization is completed, the integral trigger circuit will no longer generate pulses, so the output of the bidirectional counter circuit will no longer change. At this time, the output of the bidirectional counter circuit is the final quantization result.

[0078] Since the positive and negative currents are subtracted in the previous integration trigger circuit, the integration trigger circuit will only generate one pulse at the same time, that is, the positive counting pulse and the negative counting pulse will not be generated at the same time. Therefore, an RS trigger can be used to connect the positive counting pulse and the negative counting pulse to the set end and reset end of the RS trigger respectively, and the counting direction of the currently received pulse is determined by the state of the RS trigger output value, and then the operation of adding or subtracting one is performed according to the counting direction. First, an RS trigger is used to determine whether the currently received positive counting pulse or negative counting pulse is used, and the positive counting pulse and the negative counting pulse are ORed and passed to the subsequent counter (i.e., D trigger). If the current count pulse is positive, the RS trigger output is 0. At this time, except for the flip of the 0th D trigger, the subsequent D trigger will only flip when the previous D trigger output is 1 and receives a pulse, and the pulse will continue to be passed to the next D trigger. When the output of the previous D trigger is 0, the state will not flip, and the pulse will not be passed to the next D trigger; when the RS trigger output is 1, the situation is the opposite. The D trigger will flip when the previous D trigger output is 0 and receives a pulse, and the pulse will continue to be passed to the next D trigger. When the output of the previous D trigger is 1, it remains unchanged and does not pass the pulse to the next D trigger. Finally, when the final quantization result is output, the positive or negative of the stored count value is judged according to the information stored in the highest D trigger. If the value of the highest D trigger is 1, it means that the count value stored in the counter is negative, and the output of the counter is 0; if the value of the highest D trigger is 0, it means that the count value stored in the counter is positive, and the output of the counter is the current stored value. In this way, the nonlinear activation function of the ReLu function is realized and the activation value is obtained. A neural network usually needs to perform activation processing on the output of each layer, and ReLU is a common activation function. This embodiment uses a bidirectional counter circuit to complete the ReLU function that can be completed by the post-processing circuit.

[0079] Although the 8-bit ADC quantization accuracy is sufficient for VMM operations in common neural networks, the bidirectional counter circuit is designed to be 13 bits, that is, it includes 13 D flip-flops. This is because the readout device designed in this embodiment is optimized for the partial sum summing process. Due to the residual charge accumulation function in the integral trigger circuit, the readout device may need to continuously process the quantization results of multiple quantization cycles, and the partial sum results obtained by the same readout device in multiple quantization cycles need to be added. In the commonly used network structure, the maximum number of partial sum additions required is 18, so in the counter, an extra 5 bits are reserved to avoid the final summation result exceeding the storage range of the counter, resulting in incorrect final output results.

[0080] It should be noted that the initial state of the D terminal of each D flip-flop is 0.

[0081] In this embodiment, the bidirectional counter circuit includes: an RS flip-flop and a plurality of D flip-flops.

[0082] The CLK terminal of the 0th D flip-flop is connected to the output terminal of the OR gate, the first input terminal of the OR gate is connected to the output terminal of the first monostable circuit, and the second input terminal of the OR gate is connected to the output terminal of the second monostable circuit. The CLK terminal of the i-th D flip-flop is connected to the output terminal of the i-th first AND gate, the first input terminal of the i-th first AND gate is connected to the CLK terminal of the i-1-th D flip-flop, the second input terminal of the i-th first AND gate is connected to the output terminal of the i-th XOR gate, the first input terminal of the i-1-th D flip-flop is connected to the Q terminal, the second input terminal of the i-th XOR gate is connected to the output terminal of the RS flip-flop, the R terminal of the RS flip-flop is connected to the output terminal of the first monostable circuit, and the S terminal of the RS flip-flop is connected to the output terminal of the second monostable circuit. i=1, 2, ..., I-1, I is the total number of D flip-flops.

[0083] The D terminal of the 0th D flip-flop is connected to the The D end of the i-th D flip-flop is connected to the end.

[0084] The Q end of the jth D flip-flop is connected to the first input end of the jth second AND gate, and the second input end of the jth second AND gate is connected to the Q end of the I-1th D flip-flop. The output terminals of all the second AND gates constitute the output terminal of the integration trigger circuit. j = 0, 1, ... I-2.

[0085] This embodiment proposes an in-memory computing readout device dedicated to a neural network with low quantization error. It mainly proposes a low quantization error readout device for in-memory computing neural networks, which uses full charge domain calculations for quantization and post-processing. Specifically, a novel residual charge accumulation function is introduced to reduce the calculation error caused by calculation partitioning. The resolution of the ADC can be adjusted by changing the quantization time of the ADC to achieve adjustable accuracy. In order to further improve the power consumption and area efficiency of the readout device, several designs are carried out, including sampling and holding, charge reset, ReLU function and bidirectional counter, so as to propose an in-memory computing readout device with residual accumulation function. In addition, through multiple designs, the area, energy consumption and delay performance of the readout device are optimized.

[0086] Example 2

[0087] A control method for a neural network dedicated in-memory computing readout device, used to control the neural network dedicated in-memory computing readout device described in Example 1 to work, comprising:

[0088] inputting the input value of the current quantization cycle into the memory array;

[0089] The current sensing circuit converts the positive-weighted conductance and the negative-weighted conductance of the memory array in the current quantization cycle into the positive-weighted current and the negative-weighted current, respectively, and reduces and subtracts the positive-weighted current and the negative-weighted current to obtain the processed current of the current quantization cycle;

[0090] The integral trigger circuit integrates the integral capacitor based on the processed current of the current quantization cycle to obtain a total voltage, and when the total voltage reaches a positive threshold, generates a positive counting pulse, and discharges the integral capacitor at the same time, so that the total voltage decreases by a first preset value, and obtains a residual voltage of the current quantization cycle; when the total voltage reaches a negative threshold, generates a negative counting pulse, and charges the integral capacitor at the same time, so that the total voltage increases by a second preset value, and obtains a residual voltage of the current quantization cycle; when the total voltage does not reach the positive threshold and does not reach the negative threshold, the total voltage is taken as the residual voltage of the current quantization cycle;

[0091] The bidirectional counter circuit increases the count value of the previous quantization cycle by 1 when receiving the positive counting pulse, and decreases the count value of the previous quantization cycle by 1 when receiving the negative counting pulse, so as to obtain the count value of the current quantization cycle;

[0092] Determine whether the current quantization cycle is the last quantization cycle; if so, the bidirectional counter circuit determines the activation value of the current quantization cycle according to the count value of the current quantization cycle; if not, return to the step of "inputting the input value of the current quantization cycle into the memory array".

[0093] The control method of this embodiment also includes: determining whether the duration for which the first current mirror receives the positive-weighted current and the negative-weighted current reaches a first preset duration; if so, controlling the transmission gate to close and controlling the preset voltage to 0.

[0094] The control method of this embodiment also includes: judging whether the working time of the integral capacitor reaches a second preset time length; if so, disconnecting the third switch tube; wherein, the method for determining the second preset time length includes: determining a reference time length according to the quantization accuracy required by the user; calculating the product of the reference time length and 2 to the power of n-1 to obtain the second preset time length, where n is the number of bits of the input value of the current quantization cycle.

[0095] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A neural network dedicated in-memory computing readout device, characterized in that: include: Current sensing circuit, integral trigger circuit and bidirectional counter circuit; The input terminal of the current sensing circuit is connected to a bit line of the memory array; The current sensing circuit is used to convert the positive weighted conductance and the negative weighted conductance of the memory array in the current quantization cycle into the positive weighted current and the negative weighted current respectively, and reduce and subtract the positive weighted current and the negative weighted current to obtain the processed current of the current quantization cycle; The memory array is used to complete the neural network in-memory calculation; The conductance of the positive weight is the result of the multiplication and addition of the input value of the current quantization cycle and the positive weight, and the conductance of the negative weight is the result of the multiplication and addition of the input value of the current quantization cycle and the negative weight; the input value of the current quantization cycle is the nth bit of each parameter in a parameter group obtained by splitting the input vector, n=1, 2, ..., N, N is the total number of bits; the positive weight and the negative weight correspond to the parameters one by one, and the difference between the positive weight and the negative weight is equal to the weight value corresponding to the corresponding parameter; the number of quantization cycles is equal to the product of the total number of parameter groups obtained by splitting the input vector and the total number of bits included in the parameter; The input end of the integration trigger circuit is connected to the output end of the current sensing circuit; the integration trigger circuit is used to integrate the integration capacitor based on the processed current of the current quantization cycle to obtain a total voltage, and when the total voltage reaches a positive threshold, generate a positive counting pulse, and discharge the integration capacitor at the same time, so that the total voltage drops by a first preset value, and obtain a residual voltage of the current quantization cycle; When the total voltage reaches a negative threshold, a negative counting pulse is generated, and the integration capacitor is charged at the same time, so that the total voltage rises by a second preset value to obtain a residual voltage of the current quantization cycle; When the total voltage does not reach the positive threshold and does not reach the negative threshold, the total voltage is taken as the residual voltage of the current quantization cycle; the total voltage is the sum of the integrated voltage generated by the processed current of the current quantization cycle and the residual voltage of the previous quantization cycle; The first preset value is the difference between the positive threshold and the basic voltage of the integration capacitor; The second preset value is the difference between the basic voltage of the integrating capacitor and the negative threshold; The basic voltage of the integrating capacitor is greater than the negative threshold, and the basic voltage of the integrating capacitor is less than the positive threshold; The input end of the bidirectional counter circuit is connected to the output end of the integral trigger circuit; the bidirectional counter circuit is used to increase the count value of the previous quantization cycle by 1 when receiving the positive counting pulse, and decrease the count value of the previous quantization cycle by 1 when receiving the negative counting pulse, so as to obtain the count value of the current quantization cycle, and when the current quantization cycle is the last quantization cycle, determine the activation value of the current quantization cycle according to the count value of the current quantization cycle.

2. A neural network dedicated in-memory computing and reading device according to claim 1, characterized in that: The current sensing circuit comprises: an operational amplifier, a first current mirror and a second current mirror; The non-inverting input terminal of the operational amplifier is connected to a preset voltage, the inverting input terminal of the operational amplifier is connected to one end of the bit line of the memory array, the other end of the bit line of the memory array is grounded, the output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier, and the inverting input terminal of the operational amplifier is the input terminal of the current sensing circuit; the operational amplifier is used to convert the positive-weighted conductance and the negative-weighted conductance of the memory array in the current quantization cycle into positive-weighted current and negative-weighted current respectively; The input end of the first current mirror is connected to the output end of the operational amplifier; the first current mirror is used to reduce the positive weight current and the negative weight current respectively to obtain the positive weight reduced current and the negative weight reduced current; The input end of the second current mirror is connected to the output end of the first current mirror, and the output end of the second current mirror is the output end of the current sensing circuit; the second current mirror is used to subtract the scaled current of the positive weight from the scaled current of the negative weight to obtain the processed current of the current quantization cycle.

3. A neural network dedicated in-memory computing and reading device according to claim 2, characterized in that: The current sensing circuit further includes: a transmission gate; One end of the transmission gate is connected to the input end of the first current mirror, and the other end of the transmission gate is connected to the output end of the first current mirror; the transmission gate is used to close when the duration for which the first current mirror receives the positive-weighted current and the negative-weighted current reaches a first preset duration.

4. The neural network dedicated in-memory computing and reading device according to claim 1, characterized in that: The integration trigger circuit includes: an integration capacitor, a first voltage comparator, a first monostable circuit, a first switch tube, a first current source, a second voltage comparator, a second monostable circuit, a second switch tube and a second current source; One end of the integration capacitor is grounded, and the other end of the integration capacitor is respectively connected to the inverting input end of the first voltage comparator, the output end of the first current source, the inverting input end of the second voltage comparator and the output end of the second current source, and the other end of the integration capacitor is the input end of the integration trigger circuit; the integration capacitor is used to integrate the processed current based on the current quantization cycle to obtain a total voltage; The non-inverting input terminal of the first voltage comparator is connected to the positive threshold; the first voltage comparator is used to generate a falling edge when the total voltage reaches the positive threshold; The input end of the first monostable circuit is connected to the output end of the first voltage comparator; the first monostable circuit is used to generate a positive counting pulse when receiving the falling edge; The first switch tube is connected to the output end of the first monostable circuit; the first switch tube is used to open when receiving the positive counting pulse; The input end of the first current source is connected to the first switch tube; the first current source is used to discharge the integration capacitor when the first switch tube is turned on, so that the total voltage drops by a first preset value to obtain the residual voltage of the current quantization cycle; The non-inverting input terminal of the second voltage comparator is connected to the negative threshold; the second voltage comparator is used to generate a rising edge when the total voltage reaches the negative threshold; The input end of the second monostable circuit is connected to the output end of the second voltage comparator; the second monostable circuit is used to generate a negative counting pulse when receiving the rising edge; The second switch tube is connected to the output end of the second monostable circuit; the second switch tube is used to open when receiving the negative counting pulse; The input end of the second current source is connected to the second switch tube; the second current source is used to charge the integration capacitor when the second switch tube is turned on, so that the total voltage rises by a second preset value to obtain the residual voltage of the current quantization cycle; The output end of the first monostable circuit and the output end of the second monostable circuit constitute the output end of the integration trigger circuit.

5. The neural network dedicated in-memory computing and reading device according to claim 4, characterized in that: The integration trigger circuit also includes: a third switch tube; the third switch tube is located between the other end of the integration capacitor and the inverting input end of the first voltage comparator, the output end of the first current source, the inverting input end of the second voltage comparator and the output end of the second current source; the third switch tube is used to disconnect when the working time of the integration capacitor reaches a second preset time; the second preset time is determined according to the quantization accuracy required by the user and the number of bits n of the input value of the current quantization cycle.

6. A neural network dedicated in-memory computing and reading device according to claim 4, characterized in that: The integration trigger circuit also includes: a fourth switch tube; the fourth switch tube is connected in parallel with the integration capacitor; the fourth switch tube is used to clear the charge of the integration capacitor.

7. The neural network dedicated in-memory computing and reading device according to claim 4, characterized in that: The bidirectional counter circuit comprises: an RS trigger and a plurality of D triggers; The CLK terminal of the 0th D flip-flop is connected to the output terminal of the OR gate, the first input terminal of the OR gate is connected to the output terminal of the first monostable circuit, and the second input terminal of the OR gate is connected to the output terminal of the second monostable circuit; the CLK terminal of the ith D flip-flop is connected to the output terminal of the ith first AND gate, the first input terminal of the ith first AND gate is connected to the CLK terminal of the i-1th D flip-flop, the second input terminal of the ith first AND gate is connected to the output terminal of the ith XOR gate, the first input terminal of the ith XOR gate is connected to the Q terminal of the i-1th D flip-flop, the second input terminal of the ith XOR gate is connected to the output terminal of the RS flip-flop, the R terminal of the RS flip-flop is connected to the output terminal of the first monostable circuit, and the S terminal of the RS flip-flop is connected to the output terminal of the second monostable circuit; i=1, 2, ..., I-1, I is the total number of D flip-flops; The D terminal of the 0th D flip-flop is connected to the The D terminal of the i-th D flip-flop is connected to the end; The Q end of the jth D flip-flop is connected to the first input end of the jth second AND gate; the second input end of the jth second AND gate is connected to the Q end of the I-1th D flip-flop. The output terminals of all second AND gates constitute the output terminal of the integral trigger circuit; j = 0, 1, ..., I-2.

8. A control method for a neural network dedicated in-memory computing readout device, used to control the operation of a neural network dedicated in-memory computing readout device as claimed in any one of claims 1 to 7, characterized in that: include: inputting the input value of the current quantization cycle into the memory array; The current sensing circuit converts the positive-weighted conductance and the negative-weighted conductance of the memory array in the current quantization cycle into the positive-weighted current and the negative-weighted current, respectively, and reduces and subtracts the positive-weighted current and the negative-weighted current to obtain the processed current of the current quantization cycle; The integration trigger circuit integrates the integration capacitor based on the processed current of the current quantization cycle to obtain a total voltage, and generates a positive counting pulse when the total voltage reaches a positive threshold, and discharges the integration capacitor at the same time, so that the total voltage drops by a first preset value to obtain a residual voltage of the current quantization cycle; When the total voltage reaches a negative threshold, a negative counting pulse is generated, and the integration capacitor is charged at the same time, so that the total voltage rises by a second preset value to obtain a residual voltage of the current quantization cycle; When the total voltage does not reach the positive threshold and does not reach the negative threshold, taking the total voltage as the residual voltage of the current quantization cycle; The bidirectional counter circuit increases the count value of the previous quantization cycle by 1 when receiving the positive counting pulse, and decreases the count value of the previous quantization cycle by 1 when receiving the negative counting pulse, so as to obtain the count value of the current quantization cycle; Determine whether the current quantization cycle is the last quantization cycle; If yes, the bidirectional counter circuit determines the activation value of the current quantization cycle according to the count value of the current quantization cycle; if no, the process returns to the step of "inputting the input value of the current quantization cycle into the memory array".

9. The control method of the neural network dedicated in-memory computing readout device according to claim 8, characterized in that: Also includes: Determine whether the duration for which the first current mirror receives the current with positive weight and the current with negative weight reaches a first preset duration; If so, the transmission gate is controlled to be closed, and the preset voltage is controlled to be zero.

10. The control method of a neural network dedicated in-memory computing readout device according to claim 8, characterized in that: Also includes: Determining whether the working time of the integral capacitor reaches a second preset time length; If yes, disconnect the third switch tube; Among them, the method for determining the second preset time length includes: determining the reference time length according to the quantization accuracy required by the user; calculating the product of the reference time length and 2 to the power of n-1 to obtain the second preset time length; n is the number of bits of the input value of the current quantization cycle.

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