A memory test and repair system and method, and integrated circuit

Abstract

The present application relates to the technical field of integrated circuits, and further to a memory test and repair system and method, and an integrated circuit. The system comprises: a memory array with redundant columns; a first controller comprises: a first control unit receives a first test signal in a first test mode and outputs a first test control signal; a second control unit receives a second test signal in a second test mode and outputs a second test control signal; a second controller receives the first / second test control signal and generates a third test control signal; traverses the test memory array under the third test control signal, and feeds back the first test result to the first controller; compares and analyzes and outputs the second test result; the third controller analyzes the second test result and obtains fault information; the fourth controller analyzes the fault information and outputs a repair control signal to the memory array, and the memory array is repaired in an address reconstruction manner. The system saves hardware resources and test time.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and further to a memory test and repair system and method, and an integrated circuit. Background Art

[0002] The memory array in an integrated circuit is the core component of data storage, and its reliability directly affects the performance of the entire system. To ensure the reliability of the memory array, the industry generally adopts two main repair strategies: hard repair and soft repair.

[0003] Hard repair technology: Hard repair usually involves testing the memory array using external automatic test equipment to identify the faulty cells and implement permanent repairs through physical means. However, it has several disadvantages, including the need for a large amount of hardware resources and long testing time.

[0004] Soft repair technology: The existing soft repair technology does not use the APB system bus as a test method or channel. The system cannot obtain and use test results and fault information, making the test method relatively rigid and inflexible. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a memory test and repair system and method, and an integrated circuit, which saves hardware resources and test time.

[0006] In a first aspect, the present application provides a memory test and repair system, comprising: a memory array with redundant columns; a first controller, comprising a first control unit and a second control unit, wherein the first control unit outputs a first test control signal after receiving a first test signal in a first test mode; the second control unit outputs a second test control signal after receiving a second test signal in a second test mode; a second controller, receiving the first / second test control signals, generating a third test control signal, wherein the third test control signal comprises a test vector sequence and an address read and write control signal; after traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result to the first controller; and comparing and analyzing and outputting a second test result, wherein the second test result comprises a current test address and a failure bitmap; a third controller, receiving and analyzing the second test result, obtaining fault information, wherein the fault information comprises a faulty bad pixel type, a number of failed bits, and a bad pixel address; a fourth controller, receiving and analyzing the fault information, and when the faulty bad pixel type is a repairable type, outputting a repair control signal to the memory array, wherein the memory array is repaired in an address reconstruction manner; the repair control signal comprises a repair enable signal and a bad pixel address sequence.

[0007] The above memory test and repair system can control the corresponding controller through the automatic test machine control unit to complete the test of the memory array with redundant columns, and can also control the corresponding controller through the APB bus control unit to complete the test of the memory array with redundant columns. The test means are more diversified and the operation is more flexible. At the same time, in the process of repairing the memory array with redundant columns, there is no need to perform hard repair by laser or blowing electronic fuses, which saves hardware resources and test time.

[0008] In one implementation, it also includes: a central processing unit connected to the first controller, sending the first test signal to the first controller; the central processing unit receives the fault information output by the first controller.

[0009] In the test and repair system of the above memory, the central processing unit reads the fault information from the first control unit, and when the fault type is a repairable type, writes the generated repair information into the register unit, and controls the latch control unit to output a repair control signal to the memory array with redundant columns for repair, further improving the flexibility of the system and user experience.

[0010] In one implementation, the fourth controller includes: a latch control unit, which analyzes the fault information and outputs the repair control signal to the memory array when the fault information is of a repairable type; and a register unit, which latches the fault information when the fault information is of a repairable type.

[0011] In the test and repair system of the above memory, after the fourth controller receives the fault information sent by the third controller, the latch control unit determines whether the fault type in the fault information is a repairable type. If the fault type is a repairable type, the latch control unit outputs a repair control signal to the memory array with redundant columns for repair, and the register unit latches the fault information; if the fault type is an unrepairable type, the latch control unit does not output a repair control signal, and the register unit does not latch the fault information. In this way, the area overhead of the test and repair system of the memory can be reduced, and the purpose of balancing the repair efficiency is also achieved.

[0012] In one implementation, the fourth controller further includes: a test control unit, which detects a repair result after the memory array is repaired.

[0013] The above memory test and repair system confirms whether the memory array with redundant columns is successfully repaired by comparing the previous test result with the secondary test result, thereby improving the repair accuracy and reducing the repair error.

[0014] In one implementation, the register unit receives the repair information written by the central processor through the first control unit, and the latch control unit receives the repair information and generates the repair control signal; the central processor also reads the second test result from the register unit through the first control unit.

[0015] In one implementation: the central processor is further used to receive the first test result obtained by the test machine from the second control unit, and generate the repair information; the second test control signal is sent by the test machine.

[0016] In the above memory test and repair system, the central processing unit can be linked with the automatic test machine to obtain the first test result obtained by the automatic test machine in the first test mode or the second test mode, and generate corresponding repair information according to the first test result. Then the repair information is written into the register unit, and the latch control unit is controlled to output a repair control signal to repair the memory array with redundant columns, further improving the compatibility of the system.

[0017] In one implementation, the first controller further includes: a data synchronization unit, which performs synchronization processing on the data when the first controller interacts with the central processing unit via a bus.

[0018] In one implementation, the second controller includes a test vector generator and a comparator, the test vector generator generates the third test control signal according to the algorithm model, and the comparator compares, analyzes and outputs the second test result; the third controller has the algorithm model built in to analyze whether there are faulty bad points and the number of bad points in the tested memory array; when there is a single bad point or multiple bad points in a single column, the type of the faulty bad point is a repairable type.

[0019] In a second aspect, the present application further provides an integrated circuit, comprising a memory test and repair system as described in any one of the above implementations.

[0020] In a third aspect, the present application also provides a memory test and repair method, which is applied in a memory test and repair system described in any of the above implementations, and includes the following steps: when analysis shows that the memory is in a first test mode, generating a first test control signal; when analysis shows that the memory is in a second test mode, generating a second test control signal; based on the first / second test control signal, generating a third test control signal, the third test control signal including a test vector sequence and an address read and write control signal; after traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result; and comparing and analyzing and outputting a second test result, the second test result including a current test address and a failure bitmap; analyzing the second test result to obtain fault information, the fault information including a faulty bad pixel type, a number of failure bits, and a bad pixel address; when the faulty bad pixel type is a repairable type, outputting a repair control signal to the memory array, and the memory array is repaired by address reconstruction; the repair control signal includes a repair enable signal and a bad pixel address sequence.

[0021] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0022] 1. The test of the memory array with redundant columns can be completed by controlling the corresponding controller through the automatic test machine control unit, or by controlling the corresponding controller through the APB bus control unit. The test means are more diversified and the operation is more flexible. At the same time, in the repair process of the memory array with redundant columns, there is no need to perform hard repair by laser or blowing electronic fuses, which saves hardware resources and test time.

[0023] 2. The central processing unit reads the fault information from the first control unit. When the fault type is a repairable type, the generated repair information is written into the register unit, and the latch control unit is controlled to output a repair control signal to the memory array with redundant columns for repair, further improving the flexibility of the system and user experience.

[0024] 3. After receiving the fault information sent by the third controller, the fourth controller determines whether the fault type in the fault information is a repairable type by the latch control unit. If the fault type is a repairable type, the latch control unit outputs a repair control signal to the memory array with redundant columns for repair, and the register unit latches the fault information; if the fault type is an unrepairable type, the latch control unit does not output a repair control signal, and the register unit does not latch the fault information. In this way, the area overhead of the memory test and repair system can be reduced, and the purpose of balancing the repair efficiency can also be achieved.

[0025] 4. By comparing the previous test results with the secondary test results, it is confirmed whether the memory array with redundant columns is successfully repaired, thereby improving the accuracy of the repair and reducing the repair error.

[0026] 5. The central processing unit can be linked with the automatic test machine to obtain the first test result obtained by the automatic test machine in the first test mode or the second test mode, and generate corresponding repair information according to the first test result. Then the repair information is written into the register unit, and the latch control unit is controlled to output a repair control signal to repair the memory array with redundant columns, further improving the compatibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0028] Figure 1 A schematic diagram of the structure of a memory hard repair provided by an embodiment of the present application is shown;

[0029] Figure 2 A schematic diagram of the structure of a memory soft repair provided by an embodiment of the present application is shown;

[0030] Figure 3 A schematic diagram of the structure of a memory test and repair system provided in an embodiment of the present application is shown;

[0031] Figure 4 A flowchart of testing and repairing a memory provided by an embodiment of the present application is shown;

[0032] Figure 5 A flow chart of a memory test and repair method provided in an embodiment of the present application is shown.

[0033] Reference numerals:

[0034] A first controller 100; a second controller 200; a third controller 300; a fourth controller 400; a storage array with redundant columns 500; an automatic test machine 600; a central processing unit 700; a memory management unit 800; a first control unit 110; a second control unit 120; a data synchronization unit 130; a test vector generator 210; a state machine 220; a comparator 230; a register unit 410; a latch control unit 420; and a test control unit 430. DETAILED DESCRIPTION

[0035] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0036] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0037] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0038] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0039] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0040] In a specific implementation, the terminal device described in the embodiments of the present application includes, but is not limited to, other portable devices such as mobile phones, laptop computers, tutoring machines, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that in some embodiments, the terminal device is not a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., touch screen displays and / or touch pads).

[0041] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0043] Static Random-Access Memory (SRAM) is a storage technology widely used in integrated circuits. It is mainly used in situations where frequent and fast read and write operations are required. Therefore, the initial form of SRAM is a simple storage matrix composed of basic storage units, each of which is responsible for storing one bit of data. The SRAM design at this stage focuses on speed and efficiency, but has a low tolerance for failures. In particular, once a storage unit fails, it may cause the entire chip to fail. In order to improve the reliability of SRAM, designers began to introduce the concept of redundancy. This is like adding a "substitute player" to the memory. When a storage unit fails, the redundant unit can immediately take over its work, also known as redundant allocation. To this end, based on SRAM, designers designed an SRAM storage array with redundant columns.

[0044] The SRAM storage array with redundant columns is composed of multiple small-capacity single-port SRAM memories or dual-port SRAM memories to form multiple large-capacity storage array groups. The number of array groups can be dynamically configured according to the chip system requirements. Redundant columns are additional storage cells in the array. They do not participate in data storage under normal circumstances, but are on standby to replace those failed cells at any time. These redundant columns are physically adjacent to normal storage cells, but are logically independent.

[0045] When a cell or column in a memory array fails, the system can identify the location of the failure through built-in fault detection and repair logic, and use a redundant column to replace the failed cell. This process is called "fault repair". After replacing the failed cell with a redundant column, the system needs to adjust the address mapping of the memory to ensure that the mapping of logical addresses to physical addresses is still correct. This usually involves address reconstruction logic, which can automatically redirect access to the failed cell to the redundant column.

[0046] There are many ways to repair the failure of the memory array, which are described below with reference to the accompanying drawings:

[0047] Reference Figure 1 , which shows a schematic diagram of the structure of a memory hard repair provided by an embodiment of the present application. Figure 1As shown, it includes: a storage array 500 with redundant columns, an automatic test machine 600, and an electronic fuse 900. The automatic test machine 600 is used to test whether the storage array 500 with redundant array has a fault. For example, the automatic test machine sends a test vector sequence with a diagnostic function to the storage array 500 with redundant array for testing. The storage array 500 with redundant columns is used to feed back a corresponding test response to the automatic test machine 600. The electronic fuse 900 is used to repair the fault that occurs in the storage array 500 with redundant columns. The automatic test machine 600 communicates with the storage array 500 with redundant columns. The communication mode includes, for example, but is not limited to: I / O interface, JTAG interface, boundary scan, serial communication, parallel communication, dedicated test interface, control signal, data synchronization, status and command register, network communication, test access port, etc.

[0048] Taking the I / O interface as an example, the automatic test machine 600 sends a test vector sequence with a diagnostic function to the storage array 500 with redundant columns through the I / O interface, which is used to traverse the entire storage array. Test whether each storage array can work normally. After the test is completed, the storage array 500 with redundant columns feeds back the corresponding test response to the automatic test machine 600. The automatic test machine generates a bitmap based on the test response. Among them, the bitmap will show which storage arrays are working normally and which storage arrays are faulty. The failure bitmap is a type of bitmap, which only marks which storage arrays are faulty. The automatic test machine 600 performs redundancy allocation according to the failure bitmap and obtains corresponding reconfiguration repair information. Then the reconfiguration repair information is downloaded to the electronic fuse 900. The address mapping between the fault column and the redundant column is realized by laser or by blowing the electronic fuse 900, so that the redundant column replaces the fault column, and the address reconstruction can be completed. That is, when the system attempts to access a fault column, the control logic will automatically redirect the access to the corresponding redundant column. In this way, the fault repair of the storage array 500 with redundant columns is completed.

[0049] In addition to hard repair, soft repair can also be used to repair the faulty memory array. Figure 2 , which shows a schematic diagram of the structure of a memory soft repair provided by an embodiment of the present application. Figure 2As shown, it includes: a second controller 200, a third controller 300, a fourth controller 400, and a storage array 500 with redundant columns. The second controller 200 is used to generate a test control signal to perform fault detection on the storage array 500 with redundant columns, for example, the test control signal includes a test vector sequence and an address read and write signal. The third controller 300 is used to analyze the test result obtained by the second controller 200, for example, the test result includes the current test address and the failure bitmap. The fourth controller 400 is used to allocate redundant columns and reconstruct addresses according to the fault information analyzed by the third controller 300, for example, the fault information includes the type of faulty bad pixel, the number of failed bits, and the bad pixel address. The controller or algorithm that implements the function of the second controller 200, for example, includes but is not limited to a built-in self-test (Built-In Self-Test, BIST) controller, a marching test algorithm, a scan path, etc. The controller or algorithm that implements the function of the third controller 300, for example, includes but is not limited to a built-in self-diagnosis (Built-In Self-Diagnosis, BISD) controller, a fault isolation logic, a diagnostic engine, etc. The controller or algorithm implementing the function of the fourth controller 400 includes, for example, but is not limited to, a built-in self-repair (BISR) controller, redundant logic, repair fuses, and the like.

[0050] Taking the second controller 200 as a BIST controller, the third controller 300 as a BISD controller, and the fourth controller 400 as a BISR controller as an example, after the system is powered on, the second controller 200 starts automatically and sends a test control signal to the storage array 500 with a redundant array to detect whether the storage array 500 with a redundant array fails. The current test address and the failure bitmap in the test result are sent to the third controller 300 for analysis to obtain the type of the faulty bad point, the number of failure bits, and the bad point address. The third controller 300 sends the type of the faulty bad point, the number of failure bits, and the bad point address to the fourth controller 400, and the fourth controller 400 performs redundant column allocation according to the received fault information to replace the detected faulty storage array, and performs corresponding address reconstruction. This solution realizes the built-in self-repair of the memory, shields the failed memory, and improves the yield and reliability of the memory.

[0051] The embodiment of the present application also proposes a fault repair method for a memory array, by interacting an APB (Advanced Peripheral Bus) bus system, an automatic test machine, and the second controller 200, the third controller 300, and the fourth controller 400, so that the APB bus system can directly obtain test results and fault information, and control the fourth controller 400 to repair the memory array 500 with redundant columns according to the test results and fault information. The APB bus system can also obtain test results from the automatic test machine, so that the test results of the automatic test machine can be used to write the fourth controller 400 and repair the memory array 500 with redundant columns.

[0052] The following is a detailed description with reference to the accompanying drawings. Figure 3 , which shows a schematic diagram of the structure of a memory test and repair system provided by an embodiment of the present application. Figure 3 As shown, the system includes: a first controller 100, a second controller 200, a third controller 300, a fourth controller 400, a storage array with redundant columns 500, an automatic test machine 600, a central processing unit 700, and a memory management unit 800. The first controller 100 includes a first control unit 110 and a second control unit 120. After receiving the first test signal in the first test mode, the first control unit 110 outputs the first test control signal; after receiving the second test signal in the second test mode, the second control unit 120 outputs the second test control signal; the second controller 200 receives the first / second test control signal and generates a third test control signal, the third test control signal includes a test vector sequence and an address read / write control signal; after traversing the memory array 500 with redundant columns under the third test control signal, the first test result is fed back to the first controller 100; and the second test result is compared and analyzed and output, the second test result includes the current test address and the failure bitmap; the third controller 300 receives and analyzes the second test result to obtain fault information, the fault information includes the type of faulty bad pixel, the number of failed bits, and the bad pixel address; the fourth controller 400 receives and analyzes the fault information, and when the type of the faulty bad pixel is a repairable type, a repair control signal is output to the memory array 500 with redundant columns, and the memory array 500 with redundant columns is repaired in an address reconstruction manner; the repair control signal includes a repair enable signal and a bad pixel address sequence.

[0053] In the embodiment of the present application, the first test mode is a self-test and self-repair process, and the second test mode is an automatic test machine test process. Users can select the corresponding test mode for testing according to their own needs.

[0054] Taking the first test mode as an example, after the test and repair system of the memory is reset and initialized, the self-test and self-repair process is completed during the startup process (wherein, the entry process of the self-test is that the user uses the software program to send a self-test startup instruction through the SWD port on the central processor 700, and the first control unit 110 starts the self-test process according to the self-test startup instruction), and then enters the normal working mode 1. Wherein the normal working mode 1 is that the memory array 500 with redundant columns has no fault or the fault has been repaired. In the first test mode, the first control unit 110 receives the first test signal and generates a corresponding first test control signal (bist_clk, rst_l, test_h). The second controller 200 generates a third test control signal according to the first test control signal. The memory array 500 with redundant columns is traversed and tested through the third test control signal. After the test is completed, the second controller 200 feeds back the first test result to the first controller 100. At the same time, the second controller 200 will also perform an XOR comparison analysis on the content to be tested in the memory array 500 with redundant columns and the expected value, and output the corresponding second test result to the third controller 300. The third controller 300 analyzes the second test result to obtain fault information, and sends the fault information to the first controller 100 and the fourth controller 400 respectively. The fourth controller 400 receives and analyzes the fault information, and when it is determined that the faulty bad pixel type in the fault information is a repairable type, it outputs a repair enable signal (repair_enable) and a bad pixel address sequence (repair_data_auto) to the memory array with redundant columns 500, so that the redundant columns in the memory array with redundant columns 500 replace the detected faulty memory array, and perform corresponding address reconstruction. Thus, the first test mode is completed.

[0055] Taking the second test mode as an example, the automatic test machine 600 sends a second test signal to the second control unit 120 in the first controller 100, and the second test signal includes an input clock (ate_clk), a reset (reset), an enable bit (test_debug_l), and an array selection (test_mb_sel), etc. Among them, the enable bit is used to control the first controller 100 to enter the automatic test machine test process. In this process, the second control unit 120 generates a corresponding second test control signal according to the second test signal. The second controller 200 generates a third test control signal according to the second test control signal. The memory array 500 with redundant columns is traversed through the third test control signal. After the test is completed, the second controller 200 feeds back the first test result (fail_h / test_done, where fail_h indicates that a fault is found during the test process; test_done indicates that the test process has ended) to the first controller 100. The second control unit 120 in the first controller 100 sends the first test result and repair_info (repair information) to the automatic test machine 600, thereby completing the second test mode. It can be imagined that during the second test mode, since the memory array 500 with redundant columns is tested in parallel, the automatic test machine 600 obtains the test results of all memory arrays. To determine which column of memory sends a fault, the automatic test machine 600 can modify the value of the array selection (for example, modify it to test_mb_sel[2:0]), select the specified memory array for testing, or perform serial scan tests on each memory one by one. At this time, the automatic test machine 600 obtains the test results of the memory to be tested.

[0056] In the embodiment of the present application, the first controller 100 is a system controller, the first control unit 110 is an APB bus control unit, and the second control unit 120 is an automatic test machine control unit.

[0057] The APB bus control unit is used to control the first test mode, which includes a series of register groups mounted on the APB bus. For example, it includes but is not limited to multiple command register groups, multiple status register groups, etc. Among them, the command register group (BIST_CSR) is used to control the start or pause of the built-in self-test / built-in self-repair process, and reflect whether the built-in self-test / built-in self-repair is completed. The status register group (BIST_STATUS_XXX) records the first test results and fault information of each memory. The first test result of each memory will be recorded in an independent status bit.

[0058] The automatic test machine control unit is used to control the second test mode, communicate with the automatic test machine 600 through the external I / O interface, receive the second test signal sent by the automatic test machine 600, and feed back the first test result and repair information to the automatic test machine 600.

[0059] The embodiment of the present application can not only control the corresponding controller through the automatic test machine control unit to complete the test of the memory array with redundant columns, but also control the corresponding controller through the APB bus control unit to complete the test of the memory array with redundant columns, and the test means are more diversified and the operation is more flexible. At the same time, in the process of repairing the memory array with redundant columns, the embodiment of the present application does not need to perform hard repair by laser or blowing electronic fuses, which saves hardware resources and test time.

[0060] In one case, the memory array 500 with redundant columns is configured by the Memory Compiler to support the repair of redundant columns. In order to balance the repair efficiency and area overhead, the embodiment of the present application can support the repair of faulty bad points of a single column of memory. When one or more bits of a column of memory fail, the column can be repaired; but when two or more columns of memory fail, the array memory cannot be repaired. Therefore, the fault type in the fault information can be divided into a repairable type and an unrepairable type, and the type information of the fault is characterized by two combined signals (repairable_h, repair_data_force).

[0061] In the first test mode, when the fourth controller 400 receives fault information, it needs to perform different operations according to the fault type. Figure 3 The embodiment of the present application provides a memory test and repair system, wherein the fourth controller 400 includes: a latch control unit 410, which analyzes fault information and outputs a repair control signal to the memory array when the fault information is of a repairable type; and a register unit 420, which latches the fault information when the fault information is of a repairable type. The latch control unit 410 may be a repairable fault latch unit; and the register unit 420 may be a repair information register unit.

[0062] After receiving the fault information sent by the third controller 300, the fourth controller 400 determines whether the fault type in the fault information is a repairable type by the latch control unit 410. If the fault type is a repairable type, the latch control unit 410 outputs a repair control signal to the memory array 500 with redundant columns for repair, and the register unit 420 latches the fault information; if the fault type is an unrepairable type, the latch control unit 410 does not output a repair control signal, and the register unit 420 does not latch the fault information. In this way, the area overhead of the test and repair system of the memory of the embodiment of the present application can be reduced, and the purpose of balancing the repair efficiency is also achieved.

[0063] In one embodiment of the present application, the repairable type of fault information can be configured by software and written into the register unit 420 by the central processor 700, so that the user can call and implement the repair of the memory array 500 with redundant columns. Figure 3 An embodiment of the present application provides a test and repair system for a memory, wherein a central processing unit 700 is connected to a first controller 100 and sends a first test signal to the first controller 100; the central processing unit 700 receives fault information output by the first controller 100; a register unit 420 receives repair information written by the central processing unit 700 through a first control unit 110, and a latch control unit 410 receives the repair information and generates a repair control signal.

[0064] The central processing unit 700 accesses each status register group in the first control unit 110 through the APB bus and reads the fault information therefrom. The central processing unit 700 determines whether the fault type in the fault information is a repairable type. If it is determined to be a repairable type, it is further determined whether the memory array 500 with redundant columns has been repaired. If it is determined that the repair is completed, the central processing unit 700 controls the memory test repair system to enter normal working mode 1; if it is determined that the repair is not completed, the central processing unit 700 generates corresponding repair information according to the fault information, and writes the repair information to the register unit 420 through the first control unit 110, and controls the latch control unit 410 to output a repair control signal to the memory array 500 with redundant columns for repair.

[0065] Furthermore, if the CPU 700 determines that the fault type in the fault information is an unrepairable type, the test and repair system of the control memory enters normal working mode 2. In normal working mode 2, the CPU 700 sends the unrepairable type fault information to the memory management unit 800. The memory management unit 800 replaces the unrepairable fault memory column with the reserved redundant column through software and hardware, writes the data originally written to the fault memory column to the replaced redundant column, or avoids using those faulty memory columns.

[0066] In an embodiment of the present application, the central processing unit reads fault information from the first control unit, and when the fault type is a repairable type, writes the generated repair information into the register unit, and controls the latch control unit to output a repair control signal to the memory array with redundant columns for repair, further improving the flexibility of the test process of the present application and the user experience.

[0067] In one embodiment of the present application, the CPU 700 may also receive the first test result sent by the automatic test machine 600, and generate corresponding repair information according to the first test result to repair the memory array 500 with redundant columns. Figure 3 The embodiment of the present application provides a memory test and repair system, wherein the central processor 700 is further used to receive a first test result obtained by the test machine from the second control unit 120 and generate repair information; the second test control signal is sent by the test machine.

[0068] In the embodiment of the present application, the central processor 700 receives the first test result obtained by the automatic test machine (the test machine is an automatic test machine) 600 from the second control unit 120, and generates repair information. At the same time, the central processor 700 writes the generated repair information into the register unit 420 in the fourth controller 400 through the first control unit 110, and the register unit 420 also sends the repair information to the latch control unit 410. The latch control unit 410 generates a repair control signal according to the repair information, and sends the repair control signal to the memory array 500 with redundant columns for repair.

[0069] In the embodiment of the present application, the central processing unit can be linked with the automatic test machine to obtain the first test result obtained by the automatic test machine in the first test mode or the second test mode, and generate corresponding repair information according to the first test result. Then the repair information is written into the register unit, and the latch control unit is controlled to output a repair control signal to repair the memory array with redundant columns, further improving the compatibility of the test process of the present application.

[0070] In one embodiment of the present application, refer to the attached Figure 3 , the register unit 420 can also store the second test result, the central processor 700 reads the second test result from the register unit 420 through the first control unit 110, and generates repair information according to the read second test result. At the same time, the central processor 700 writes the generated repair information into the register unit 420 in the fourth controller 400, and the register unit 420 also sends the repair information to the latch control unit 410. The latch control unit 410 generates a repair control signal according to the repair information, and sends the repair control signal to the memory array 500 with redundant columns for repair.

[0071] In one embodiment of the present application, after completing the entire process of the first test mode, or after the central processor receives the repair information sent by the automatic test machine and repairs the memory array with redundant columns according to the repair information, or after the central processor reads the fault information through the status register group in the first control unit and repairs the memory array with redundant columns according to the fault information, the repaired result can be tested again. For example, referring to the attached Figure 3 The embodiment of the present application provides a memory test and repair system, and the fourth controller 400 further includes: a test control unit 430, which detects the repair result after the memory array is repaired.

[0072] During the start-up of the secondary detection process, the test control unit 430 locks the fault information of the previous repair or the information written from the central processor 700 through the control signal (se_enable), so that the tested memory is in a repaired state. After the secondary test is completed, the results of the previous test and the secondary test are compared to confirm whether the repair is successful. If the repair is confirmed to be successful, the test and repair system of the memory is controlled to enter normal working mode 1. The test and repair system of the memory of the present application confirms whether the memory array with redundant columns is successfully repaired by comparing the previous test results with the secondary test results, thereby improving the accuracy of the repair and reducing the repair error.

[0073] In one embodiment of the present application, refer to the attached Figure 3 The first controller 100 further includes: a data synchronization unit 130. When the first controller 100 interacts with the central processing unit 700 via the bus, the data synchronization unit 130 performs synchronization processing on the data.

[0074] In the embodiment of the present application, the data synchronization unit 130 is a data synchronization processing unit, wherein in the first test mode, the test clock of the second controller 200 is derived from an external passive crystal oscillator clock (24MHz), and the first control unit 110 uses a high-speed PLL clock (192MHz). When the second controller 200 interacts with the first control unit 110, it is necessary to synchronize the data across the clock domain and add a delay unit. In the second test mode, the APB bus does not act, and the test clock of the second controller 200 uniformly uses a specific frequency clock (10MHz) output by the automatic test machine 600, and the data does not need to be synchronized at this time.

[0075] In one embodiment of the present application, refer to the attached Figure 3The second controller 200 includes a test vector generator 210, a state machine 220 and a comparator 230. The test vector generator 210 generates a third test control signal according to the algorithm model, and the comparator 230 compares and analyzes and outputs a second test result; the state machine 220 is used to control the test vector generator 210 to generate a third control signal, and to perform a parallel traversal of the memory array 500 with redundant columns through the third control signal; the third controller 300 has a built-in algorithm model to analyze whether there are bad points and the number of bad points in the tested memory array; when there is a single bad point or multiple bad points in a single column, the bad point type is a repairable type.

[0076] In the embodiment of the present application, the state machine 220 is a self-test finite state machine, and the comparator 230 is a fault address comparator. Among them, the state machine 220 is used to control the test vector generator 210 to generate a third test control signal according to the algorithm model SMARCHCHKBvcd according to the first / second test control signal, and send the third test control signal to the memory array 500 with redundant columns for parallel traversal. At the same time, the comparator 230 will perform an XOR comparison analysis on the content to be tested in the memory array 500 with redundant columns, generate a corresponding second test result, and send the second test result to the third controller 300. The third controller 300 has a built-in algorithm model for analyzing and diagnosing whether there are faulty bad points and the number of bad points in the currently tested memory array, and outputs the type information of the fault to the first controller 100 through two combined signals (repairable_h, repair_data_force). If it is a single bad point or multiple bad points in a single column, a repairable flag is output, otherwise an unrepairable flag information is output.

[0077] The above two test modes are complementary: the second test mode process is performed by the automatic test machine 600 to obtain the corresponding first test result. When used later, the central processing unit 700 receives the first test result sent by the automatic test machine 600 and generates repair information. This information is configured to the fourth controller 400 through the first control unit 110. For the selection of repair information, the test and repair system of the memory automatically monitors which test mode process is currently in, and selects the repair information to be output to the memory array 500 with redundant columns. In the following two cases, when the central processing unit 700 writes the repair information into the fourth controller 400, the repair information written by the central processing unit 700 is selected to be output to the memory array 500 with redundant columns; when the first test mode process is started, the repair information generated after the first test mode ends is output to the memory array 500 with redundant columns.

[0078] Reference Figure 4 , which shows a flow chart of a memory test and repair provided by an embodiment of the present application, such as Figure 4As shown, it includes: after the system is powered on and reset and initialized, it is determined whether to enter the second test mode. If the second test mode is entered, the second controller 200 traverses the memory array 500 with redundant columns through the third test control signal, and after the test is completed, the second controller 200 feeds back the first test result to the automatic test machine 600 through the first controller 100.

[0079] If the second test mode is not entered, continue to determine whether to enter the first test mode. If the first test mode is not entered, directly enter the normal working mode one. If the first test mode is entered, the fault information obtained from the test is sent to the register unit 420 for latching and the status register group in the first control unit 110. After the first test mode ends, the central processing unit 700 accesses each status register group in the first control unit 110 through the APB bus and reads the fault information therefrom. Determine whether the memory array 500 with redundant columns is fault-free or fault-free after repair. If it is determined that there is still a fault, enter the normal working mode two. If it is determined that there is no fault or no fault after repair, determine whether to perform a secondary test on the repair result. If no secondary test is performed, directly enter the normal working mode one. If a secondary test is performed, determine whether to use the test result of the second test mode. If the test result of the second test mode is used, the central processing unit 700 writes the first test result into the fourth controller 400, and at the same time, the test control unit 430 controls the latch control unit 410 to perform a second test, and compares the result of the second test with the result of the second test mode to confirm whether the repair is successful. If the repair is successful, the normal working mode 1 is entered; if the test result of the second test mode is not used, the test control unit 430 controls the latch control unit 410 to perform a second test, and compares the result of the second test with the result of the first test mode to confirm whether the repair is successful. If the repair is successful, the normal working mode 1 is entered.

[0080] Reference Figure 5 , which shows a flow chart of a memory test and repair method provided in an embodiment of the present application, which is applied to the memory test and repair system described in the aforementioned embodiment, such as Figure 5 As shown, including:

[0081] S500, when it is analyzed that the memory is in the first test mode, a first test control signal is generated; when it is analyzed that the memory is in the second test mode, a second test control signal is generated.

[0082] S510, generating a third test control signal according to the first / second test control signal, wherein the third test control signal includes a test vector sequence and an address read / write control signal.

[0083] S520, after traversing the test memory array under the third test control signal, feeding back and outputting the first test result, and comparing and analyzing and outputting the second test result, the second test result includes the current test address and the failure bitmap.

[0084] S530, analyzing the second test result to obtain fault information, where the fault information includes the type of bad pixel, the number of failed bits, and the bad pixel address.

[0085] S540, when the faulty bad pixel type is a repairable type, a repair control signal is output to the memory array, and the memory array is repaired in an address reconstruction manner; the repair control signal includes a repair enable signal and a bad pixel address sequence.

[0086] The details of the embodiments of the present application have been described in the memory test and repair system in the aforementioned embodiments, and will not be repeated here.

[0087] An embodiment of the present application also provides an integrated circuit, including a test and repair system for the memory as described in any of the aforementioned embodiments.

[0088] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0089] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0090] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. Exemplarily, the device embodiments described above are merely schematic. Exemplarily, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation. Exemplarily, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0091] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0093] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0094] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A memory test and repair system, characterized in that: include: A memory array with redundant columns; The first controller comprises a first control unit and a second control unit, wherein the first control unit outputs a first test control signal after receiving a first test signal in a first test mode; After receiving the second test signal in the second test mode, the second control unit outputs a second test control signal; A second controller receives the first / second test control signal and generates a third test control signal, wherein the third test control signal includes a test vector sequence and an address read / write control signal; After traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result to the first controller through the second controller; and performing an XOR comparison analysis on the content to be tested in the memory array with redundant columns and the expected value through the second controller to output a second test result, wherein the second test result includes a current test address and a failure bitmap; A third controller receives and analyzes the second test result to obtain fault information, and the third controller sends the fault information to the first controller and the fourth controller respectively, wherein the fault information includes a faulty bad pixel type, a number of failed bits, and a bad pixel address; The fourth controller receives and analyzes the fault information, and when the fault bad point type is a repairable type, outputs a repair control signal to the memory array, and the memory array is repaired in an address reconstruction manner; the repair control signal includes a repair enable signal and a bad point address sequence.

2. A memory test and repair system as claimed in claim 1, characterized in that: Also includes: A central processing unit, connected to the first controller, and sending the first test signal to the first controller; The central processing unit receives the fault information output by the first controller.

3. A memory test and repair system as claimed in claim 2, characterized in that: The fourth controller comprises: A latch control unit, which analyzes the fault information and outputs the repair control signal to the memory array when the fault information is of a repairable type; The storage unit latches the fault information when the fault information is of a repairable type.

4. A memory test and repair system as claimed in claim 3, characterized in that: The fourth controller further includes: The test control unit detects the repair result after the memory array is repaired.

5. A memory test and repair system as claimed in claim 3, characterized in that: The register unit receives the repair information written by the central processor through the first control unit, and the latch control unit receives the repair information and generates the repair control signal; The central processing unit also reads the second test result from the storage unit through the first control unit.

6. A memory test and repair system as claimed in any one of claims 1 to 5, characterized in that: The central processing unit is also used to receive the first test result obtained by the test machine from the second control unit, and generate the repair information; the second test control signal is sent by the test machine.

7. A memory test and repair system as claimed in claim 2, characterized in that: The first controller also includes: A data synchronization unit is used to synchronize data when the first controller and the central processing unit interact with each other via a bus.

8. A memory test and repair system as claimed in any one of claims 1 to 5, characterized in that: The second controller comprises a test vector generator and a comparator, wherein the test vector generator generates the third test control signal according to the algorithm model, and the comparator compares and analyzes and outputs the second test result; The third controller has the algorithm model built in, and analyzes whether there are bad spots and the number of bad spots in the tested memory array; when there is a single bad spot or multiple bad spots in a single column, the bad spot type is a repairable type.

9. An integrated circuit, characterized in that: A memory test and repair system comprising the memory test and repair system as described in claims 1 to 8.

10. A memory test and repair method, characterized in that: The method is applied in a memory test and repair system as claimed in claims 1 to 8, comprising the steps of: When the analysis shows that the memory is in the first test mode, generating a first test control signal; When the analysis shows that the memory is in the second test mode, generating a second test control signal; Generate a third test control signal according to the first / second test control signal, wherein the third test control signal includes a test vector sequence and an address read / write control signal; After traversing and testing the memory array under the third test control signal, feeding back and outputting a first test result to the first controller through the second controller; and performing an XOR comparison analysis on the content to be tested in the memory array with redundant columns and the expected value through the second controller to output a second test result, wherein the second test result includes a current test address and a failure bitmap; Analyze the second test result to obtain fault information, and send the fault information to the first controller and the fourth controller respectively through the third controller, wherein the fault information includes the type of the faulty pixel, the number of failed bits, and the address of the bad pixel; When the faulty bad pixel type is a repairable type, a repair control signal is output to the memory array, and the memory array is repaired in an address reconstruction manner; the repair control signal includes a repair enable signal and a bad pixel address sequence.

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