Display panel and manufacturing method of array substrate

Abstract

The application discloses a display panel and a preparation method of an array substrate. In the array substrate, a first electrode, a channel portion and a second electrode are stacked to form a vertical thin film transistor together with a gate electrode. The array substrate and the preparation method of the application have a simplified structure and are formed by a process with fewer mask plates.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a preparation method of an array substrate. BACKGROUND

[0002] For panel factories, the reduction of the number of mask plates used is one of the paths to reduce costs. Currently, four mask plate technology is generally used for array substrates of liquid crystal display panels. However, the structure of the array substrate prepared by using four mask plates is relatively complex, and the cost is relatively high. SUMMARY

[0003] Embodiments of the present application provide a display panel and a preparation method of an array substrate, which can simplify the structure of the array substrate.

[0004] Embodiments of the present application provide a display panel, which comprises an array substrate, and the array substrate comprises:

[0005] a substrate;

[0006] a first metal layer disposed on the substrate, the first metal layer comprising a first electrode, the first electrode being one of a source electrode and a drain electrode;

[0007] a first insulating layer disposed on the substrate, the first insulating layer being provided with an opening, the opening exposing the first electrode, the first insulating layer comprising a first portion and a second portion connected to each other, the thickness of the first portion being greater than the thickness of the second portion, and the first portion being located on a side of the second portion close to the first electrode;

[0008] an active layer disposed on the substrate, the active layer comprising a channel portion and a non-channel portion, the channel portion being connected to be disposed on a side of the first electrode away from the substrate, and the non-channel portion being connected to be disposed on a side of the second portion away from the substrate;

[0009] a second metal layer disposed on the substrate, the second metal layer comprising a second electrode and a gate electrode, the second electrode being the other of the source electrode and the drain electrode, the second electrode being connected to be disposed on a side of the channel portion away from the substrate, and the gate electrode being disposed on a side of the non-channel portion away from the substrate;

[0010] a second insulating layer covering the first insulating layer and the second metal layer, the second insulating layer being provided with a contact hole, the contact hole exposing the second electrode; and

[0011] a pixel electrode disposed on a side of the second insulating layer away from the substrate and connected to the second electrode through the contact hole.

[0012] Optionally, in some embodiments of the present application, the thickness of the second portion is less than the thickness of the first electrode.

[0013] Optionally, in some embodiments of the present application, the second portion, the non-channel portion and the gate are sequentially stacked to form a first stacked structure, the first electrode and the channel portion are sequentially stacked to form a second stacked structure, the thickness of the first stacked structure is less than the thickness of the first portion, and the thickness of the second stacked structure is less than the thickness of the first portion.

[0014] Optionally, in some embodiments of the present application, the first metal layer further comprises a data line connected to the first electrode, and the first insulating layer comprises a third portion covering a side of the data line away from the substrate, the thickness of the third portion being less than the thickness of the second portion.

[0015] Optionally, in some embodiments of the present application, the second metal layer further comprises a scan line connected to the gate.

[0016] Optionally, in some embodiments of the present application, the first insulating layer is a photoresist material.

[0017] Optionally, in some embodiments of the present application, the width of the first portion is between 7000 angstroms and 8000 angstroms.

[0018] Correspondingly, the present application further provides a preparation method of an array substrate, comprising the following steps:

[0019] providing a substrate and a first mask plate, the first mask plate comprising an opaque region, a first light-transmissive region and a full light-transmissive region, the light transmittance of the opaque region being 0, the light transmittance of the full light-transmissive region being 100%, and the light transmittance of the first light-transmissive region being greater than the light transmittance of the opaque region and less than the light transmittance of the full light-transmissive region;

[0020] forming a patterned first metal layer on the substrate by using the first mask plate, the first metal layer comprising a first electrode, the first electrode being one of a source electrode and a drain electrode, the first electrode corresponding to the opaque region, and the regions corresponding to the first light-transmissive region and the full light-transmissive region not being provided with the first metal layer;

[0021] forming a patterned first insulating layer on the substrate by using the first mask plate, the first insulating layer being provided with an opening exposing the first electrode, the first insulating layer comprising a first portion and a second portion connected to each other, the thickness of the first portion being greater than the thickness of the second portion, and the first portion being located at a side of the second portion close to the first electrode; the opening corresponding to the opaque region, the first portion corresponding to the full light-transmissive region, and the second portion corresponding to the first light-transmissive region.

[0022] forming a semiconductor layer, a second metal layer and a planar sacrificial layer on the substrate in sequence, the height of the second metal layer corresponding to the light-shielding region is less than the height of the second metal layer corresponding to the full light-transmitting region, and the height of the second metal layer corresponding to the light-shielding region is greater than the height of the second metal layer corresponding to the full light-transmitting region, based on the planar surface of the substrate close to the first metal layer;

[0023] planarly etching the planar sacrificial layer so as to expose the portion of the second metal layer corresponding to the full light-transmitting region, and the remaining planar sacrificial layer shields the portion of the second metal layer corresponding to the light-shielding region and the first light-transmitting region;

[0024] etching the second metal layer and the semiconductor layer to form a patterned second metal layer and an active layer with the remaining planar sacrificial layer as a shield, and then removing the remaining planar sacrificial layer; the active layer includes a channel portion and a non-channel portion, the channel portion is connected to be arranged on the side of the first electrode away from the substrate, the non-channel portion is connected to be arranged on the side of the second portion away from the substrate, the second metal layer includes a second electrode and a gate, the second electrode is the other of the source and the drain, the second electrode is connected to be arranged on the side of the channel portion away from the substrate, and the gate is arranged on the side of the non-channel portion away from the substrate;

[0025] forming a second insulating layer and a pixel electrode on the substrate in sequence, and the pixel electrode is connected to the second electrode.

[0026] Optionally, in some embodiments of the present application, the first mask plate further includes a second light-transmitting region, the light transmittance of the second light-transmitting region is less than the light transmittance of the first light-transmitting region and greater than the light transmittance of the light-shielding region; and the patterned first metal layer further includes a data line, the data line corresponds to the second light-transmitting region.

[0027] In the step of forming a patterned first insulating layer on the substrate by using the first mask plate, the first insulating layer further includes a third portion, the third portion covers the side of the data line away from the substrate, and the thickness of the third portion is less than the thickness of the second portion.

[0028] In the step of planarly etching the planar sacrificial layer, the portion of the second metal layer corresponding to the second light-transmitting region is also exposed.

[0029] Optionally, in some embodiments of the present application, the step of forming a second insulating layer and a pixel electrode on the substrate in sequence includes:

[0030] forming a second insulating layer on the substrate, the second insulating layer covering the second metal layer and the first insulating layer;

[0031] forming a patterned photoresist layer on the second insulating layer by using a second mask plate, the photoresist layer including a hollow part, a first shielding part and a second shielding part, the hollow part corresponding to the second electrode and exposing the second insulating layer, the first shielding part corresponding to a region of the pixel electrode, the second shielding part corresponding to a region of the non-pixel electrode, the second shielding part having a thickness greater than that of the first shielding part;

[0032] etching the second insulating layer to form a contact hole by shielding with the patterned photoresist layer;

[0033] ashing the photoresist layer to remove the first shielding part and thin the second shielding part;

[0034] performing flocking on the remaining photoresist layer;

[0035] forming a transparent conductive layer on the remaining photoresist layer;

[0036] removing the photoresist layer to form a pixel electrode connected to the second electrode through the contact hole.

[0037] The array substrate of the display panel and the preparation method thereof according to the embodiments of the present application form an array substrate with a simplified structure by using a process with fewer mask plates. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a structural schematic diagram of an array substrate in a display panel provided by the embodiments of the present application;

[0039] Figure 2 is a plan view of an array substrate in a display panel provided by the embodiments of the present application;

[0040] Figure 3 is a schematic diagram of step B1 of the preparation method of the array substrate provided by the embodiments of the present application;

[0041] Figure 4 is a schematic diagram of step B2 of the preparation method of the array substrate provided by the embodiments of the present application;

[0042] Figure 5 is a schematic diagram of step B3 of the preparation method of the array substrate provided by the embodiments of the present application;

[0043] Figure 6 is a schematic diagram of step B4 of the preparation method of the array substrate provided by the embodiments of the present application;

[0044] Figure 7is a schematic diagram of step B5 of the preparation method of the array substrate provided in the embodiments of the present application;

[0045] Figure 8 is a schematic diagram of step B6 of the preparation method of the array substrate provided in the embodiments of the present application;

[0046] Figure 9 is a schematic diagram of step B7 of the preparation method of the array substrate provided in the embodiments of the present application;

[0047] Figure 9-1 is a schematic diagram of step B71 of the preparation method of the array substrate provided in the embodiments of the present application;

[0048] Figure 9-2 is a schematic diagram of step B72 of the preparation method of the array substrate provided in the embodiments of the present application

[0049] Figure 9-3 is a schematic diagram of step B73 of the preparation method of the array substrate provided in the embodiments of the present application;

[0050] Figure 9-4 is a schematic diagram of step B74 of the preparation method of the array substrate provided in the embodiments of the present application;

[0051] Figure 9-5 is a schematic diagram of step B75 of the preparation method of the array substrate provided in the embodiments of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as “up” and “down” generally refer to the up and down in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and “inner” and “outer” refer to the outline of the device; the words “first”, “second”, “third” and the like are only used as labels, and do not impose numerical requirements or establish sequences.

[0053] The embodiments of the present application provide a display panel and a preparation method of an array substrate, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0054] The display panel provided by the embodiment of the present application comprises an array substrate. Optionally, the display panel can be a liquid crystal panel, an electrophoretic panel or an electroluminescent panel. The electroluminescent panel can be an organic light-emitting diode panel, an inorganic light-emitting diode panel or a quantum dot light-emitting diode panel, etc.

[0055] It should be noted that the embodiment of the present application is described by taking a liquid crystal panel with an array substrate as an example, but is not limited to this.

[0056] The preparation method of the array substrate and the display panel are described below with reference to the accompanying drawings of the specification.

[0057] Please refer to Figure 1 and Figure 2 The embodiment of the present application provides a display panel comprising an array substrate 100, which comprises a substrate 11, a first metal layer 12, a first insulating layer 13, an active layer 14, a second metal layer 15, a second insulating layer 16 and a pixel electrode 17.

[0058] The first metal layer 12 is arranged on the substrate 11. The first metal layer 12 comprises a first electrode 121, which is one of a source electrode and a drain electrode.

[0059] The first insulating layer 13 is arranged on the substrate 11. The first insulating layer 13 is provided with an opening 13a, which exposes the first electrode 121. The first insulating layer 13 comprises a first part 131 and a second part 132 connected to each other, the thickness of the first part 131 is greater than the thickness of the second part 132, and the first part 131 is located on the side of the second part 132 close to the first electrode 121.

[0060] The active layer 14 is arranged on the substrate 11. The active layer 14 comprises a channel part 141 and a non-channel part 142. The channel part 141 is connected to be arranged on the side of the first electrode 121 away from the substrate 11, and the non-channel part 142 is connected to be arranged on the side of the second part 132 away from the substrate 11.

[0061] The second metal layer 15 is arranged on the substrate 11. The second metal layer 15 comprises a second electrode 151 and a gate electrode 152. The second electrode 151 is the other of the source electrode and the drain electrode. The second electrode 151 is connected to be arranged on the side of the channel part 141 away from the substrate 11. The gate electrode 152 is arranged on the side of the non-channel part 142 away from the substrate 11.

[0062] The second insulating layer 16 covers the first insulating layer 13 and the second metal layer 15. The second insulating layer 16 is provided with a contact hole 16a, which exposes the second electrode 151. The pixel electrode 17 is arranged on the side of the second insulating layer 16 away from the substrate 11, and is connected to the second electrode 151 through the contact hole 16a.

[0063] The array substrate 100 of the embodiment of the present application adopts the structure that the second electrode 151 and the gate electrode 152 are arranged in the same layer, and the first electrode 121, the channel portion 141 and the second electrode 151 are directly stacked to form a vertical thin film transistor, so as to simplify the structure of the array substrate 100.

[0064] In an embodiment, the array substrate 100 of the present application is prepared by adopting a two-step mask plate process with multiple light transmittances, so as to not only simplify the structure, but also save the number of mask plate processes and save the cost.

[0065] Optionally, the mask plate can be a half-tone mask plate or a gray-tone mask plate, etc.

[0066] In an embodiment, the first electrode 121 is taken as the source electrode, and the second electrode 151 is taken as the drain electrode, but the present application is not limited thereto, for example, the first electrode 121 can also be taken as the drain electrode, and the second electrode 151 can also be taken as the source electrode.

[0067] In an embodiment of the present application, the thickness d2 of the second portion 132 is less than the thickness s1 of the first electrode 121.

[0068] It can be understood that, please refer to Figure 1 The thickness d2 of the second portion 132 is small, so that at least part of the gate electrode 152 is arranged in a forward direction with respect to the channel portion 141, so as to facilitate the accurate control of the on and off of the channel of the thin film transistor.

[0069] It should be noted that the side of the channel portion 141 forming the on channel is the front side of the channel portion 141, and the forward direction relative arrangement means that the gate electrode 152 is arranged in the forward direction with respect to the front side of the channel portion 141 and overlaps the front side of the channel portion 141. In addition, since the gate electrode 152 is connected to the non-channel portion 142, the non-channel portion 141 is regarded as a compensation gate electrode, which is connected to the same control signal as the gate electrode 152, and controls the on and off of the channel portion 141 together.

[0070] Optionally, in some embodiments, the thickness d2 of the second portion 132 plus the thickness of the non-channel portion 142 is equal to or less than the thickness s1 of the first electrode 121, and the thickness of the gate electrode 152 is greater than the thickness of the channel portion 141, so that the surface of the non-channel portion 141 away from the substrate 11 is flush with the surface of the first electrode 121 away from the substrate 11, and the side of the channel portion 141 close to the gate electrode 152 is arranged in the forward direction with respect to the side of the gate electrode 152 close to the channel portion 141. That is, compared with the partial non-channel portion 142 and the partial gate electrode 152 jointly facing the channel portion 142, since the conductivity of the gate electrode 152 is stronger than the conductivity of the non-channel portion 142, the gate electrode 152 can control the arrangement of the channel portion 141 entirely, so as to improve the stability, accuracy and response time of the control.

[0071] In an embodiment of the present application, the second portion 132, the non-channel portion 142 and the gate 152 are sequentially stacked to form a first stacked structure z1. The first electrode 121 and the channel portion 141 are sequentially stacked to form a second stacked structure z2. The thickness of the first stacked structure z1 is less than the thickness d1 of the first portion 131, and the thickness of the second stacked structure z2 is less than the thickness d1 of the first portion 131.

[0072] It should be noted that the thickness of the first stacked structure z1 and the second stacked structure z2 is less than the thickness d1 of the first portion 131 so that the second electrode 151 and the gate 152 are formed in the same step in subsequent processes.

[0073] In an embodiment of the present application, the first metal layer 12 further includes a data line 122 connected to the first electrode 121. The first insulating layer 13 includes a third portion 133. The third portion 133 covers a side of the data line 122 away from the substrate 11. The thickness d3 of the third portion 133 is less than the thickness d2 of the second portion 132.

[0074] It should be understood that the thickness d3 of the third portion 133 is less than the thickness d2 of the second portion 132 so that the first metal layer 12, the first insulating layer 13, the active layer 14 and the second metal layer 15 can be formed by using the same mask plate, and the non-channel portion 142 and the second metal layer 15 are not connected on the data line 122, which reduces the height of the data line 122 and further reduces the influence of the data line 122 on the pixel electrode 17 and the scan line 153.

[0075] In some embodiments, the third portion 133 can be omitted, and the side of the data line 122 away from the substrate 11 is sequentially stacked with another non-channel portion 142 and a partial second metal layer 15. That is, the corresponding process is that the data line 122 corresponds to the light shielding area of the first mask plate as described below.

[0076] In an embodiment of the present application, the second metal layer 15 further includes a scan line 153 connected to the gate 152.

[0077] Please refer to Figure 2 The scan line 153 and the data line 122 are in different layers and cross each other. The first electrode 121, the channel portion 141 and the second electrode 151 are stacked to form a stacked member. In the plan view of the array substrate, the stacked member has a ring shape with a gap 15b. That is, the planar pattern of the first electrode 121, the channel portion 141 and the second electrode 151 all have a ring shape with a gap.

[0078] The scan line 153 passes through the gap 15b and is connected to the gate 152.

[0079] The channel portion 141 has a ring structure with a notch, which can increase the width of the channel, improve the response speed of the thin film transistor, and reduce the response time.

[0080] Optionally, in some embodiments, the planar pattern of the channel portion 141 can also be other shapes, such as I-shaped or U-shaped, and the like, which will not be described here.

[0081] Optionally, the width h of the first portion 131 is between 7000 angstroms and 8000 angstroms. It should be understood that the width h of the first portion 131 is related to the threshold voltage of the thin film transistor, and by adjusting the width h of the first portion 131, the stability and response speed of the thin film transistor can be adjusted.

[0082] Optionally, the width h of the first portion 131 is between 7000 angstroms and 8000 angstroms, so as to meet the requirements of the threshold voltage, response time and stability of the thin film transistor. In another embodiment, the width h of the first portion 131 can also be other thicknesses, which can be adjusted according to actual needs, which will not be described here.

[0083] Optionally, the width h of the first portion 131 can be 7000 angstroms, 7100 angstroms, 7200 angstroms, 7300 angstroms, 7400 angstroms, 7500 angstroms, 7600 angstroms, 7700 angstroms, 7800 angstroms, 7900 angstroms or 8000 angstroms, etc.

[0084] Optionally, the material of the first insulating layer 13 can be inorganic material or organic material.

[0085] In an embodiment of the present application, the material of the first insulating layer 13 can be organic photoresist, so that the first insulating layer 13 can be directly subjected to a photoetching process without the need to additionally provide a photoresist layer to pattern the first insulating layer 13.

[0086] Based on the above description of the array substrate 100, the present embodiment also provides a preparation method of the array substrate 100 described in the above embodiments, which comprises the following steps:

[0087] Step B1, providing a substrate 11 and a first mask plate. The first mask plate comprises a light shielding area, a first light transmission area and a full light transmission area, the light transmission rate of the light shielding area is 0%, the light transmission rate of the full light transmission area is 100%, and the light transmission rate of the first light transmission area is greater than that of the light shielding area and less than that of the full light transmission area.

[0088] Step B2, using the first mask plate to form a patterned first metal layer 12 on the substrate 11. The first metal layer 12 comprises a first electrode 121, the first electrode 121 being one of a source electrode and a drain electrode, the first electrode 121 corresponding to the light shielding area, and the areas corresponding to the first light transmission area and the full light transmission area not being provided with the first metal layer 12.

[0089] In step B3, the first mask plate is used to form a patterned first insulating layer 13 on the substrate 11. The first insulating layer 13 is provided with an opening 13a exposing the first electrode 121. The first insulating layer 13 comprises a first portion 131 and a second portion 132 connected to each other, the thickness d1 of the first portion 131 is greater than the thickness d2 of the second portion 132, and the first portion 131 is located on the side of the second portion 132 close to the first electrode 121; the opening 13a corresponds to the light-shielding region, the first portion 131 corresponds to the full-transmissive region, and the second portion 132 corresponds to the first-transmissive region.

[0090] In step B4, a semiconductor layer ad, a second metal layer 15 and a planar sacrificial layer xs are sequentially formed on the substrate 11. Based on the plane of the substrate 11 close to the first metal layer 12, the height of the second metal layer 15 corresponding to the light-shielding region is less than the height of the second metal layer 15 corresponding to the full-transmissive region, and the height of the second metal layer 15 corresponding to the light-shielding region is greater than the height of the second metal layer 15 corresponding to the full-transmissive region.

[0091] In step B5, the planar sacrificial layer xs is etched in the whole area so as to expose the part of the second metal layer 15 corresponding to the full-transmissive region, and the remaining planar sacrificial layer xs blocks the part of the second metal layer 15 corresponding to the light-shielding region and the first-transmissive region.

[0092] In step B6, the second metal layer 15 and the semiconductor layer ad are etched to form a patterned second metal layer 15 and an active layer 14 with the remaining planar sacrificial layer xs as a block, and then the remaining planar sacrificial layer xs is removed. The active layer 14 comprises a channel portion 141 and a non-channel portion 142, the channel portion 141 is connected to be arranged on the side of the first electrode 121 away from the substrate 11, and the non-channel portion 142 is connected to be arranged on the side of the second portion 132 away from the substrate 11; the second metal layer 15 comprises a second electrode 151 and a gate 152, the second electrode 151 is the other of the source and the drain. The second electrode 151 is connected to be arranged on the side of the channel portion 141 away from the substrate 11, and the gate 152 is arranged on the side of the non-channel portion 142 away from the substrate 11.

[0093] In step B7, a second insulating layer 16 and a pixel electrode 17 are sequentially formed on the substrate 11. The pixel electrode 17 is connected to the second electrode 151.

[0094] It should be noted that in the preparation method of the array substrate 100, the first metal layer 12, the first insulating layer 13, the active layer 14 and the second metal layer 15 are formed by using the same mask plate process, which reduces the process of the mask plate and simplifies the structure of the array substrate 100.

[0095] Hereinafter, the application will be described in detail with reference to the accompanying drawings. Figures 3-9The manufacturing method of the array substrate 100 in the embodiment of the present application is described.

[0096] Referring to Figure 3 , step B1, a substrate 11 and a first mask plate Ma are provided. The first mask plate Ma includes an opaque region m1, a first light-transmitting region m2 and a full light-transmitting region m4. The light-transmitting rate of the opaque region m1 is 0, the light-transmitting rate of the full light-transmitting region m4 is 100%, and the light-transmitting rate of the first light-transmitting region m2 is greater than the light-transmitting rate of the opaque region m1 and less than the light-transmitting rate of the full light-transmitting region m4.

[0097] It should be noted that the opaque region m1, the first light-transmitting region m2, the second light-transmitting region m3 and the full light-transmitting region m4 of the first mask plate are all provided with corresponding setting regions on the substrate 11. For example, in the direction of the orthographic projection of the substrate 11, the opaque region m1 corresponds to cover a first setting region sz1 of the substrate 11, the first light-transmitting region m2 corresponds to cover a second setting region sz2 of the substrate 11, the second light-transmitting region m3 corresponds to cover a third setting region sz3 of the substrate 11, and the full light-transmitting region m4 corresponds to cover a fourth setting region sz4 of the substrate 11.

[0098] The light-transmitting rates of the opaque region m1, the second light-transmitting region m3, the first light-transmitting region m2 and the full light-transmitting region m4 increase in turn. That is, the light-transmitting rate of the opaque region m1 is 0, the light-transmitting rate of the full light-transmitting region m4 is 100%, and the light-transmitting rate of the second light-transmitting region m3 is less than the light-transmitting rate of the first light-transmitting region m2 and greater than the light-transmitting rate of the opaque region m1.

[0099] Optionally, the light-transmitting rate of the first light-transmitting region m2 is between 40% and 80%, for example, it can be 40%, 50%, 60%, 70% or 80%, etc. The light-transmitting rate of the second light-transmitting region m3 is between 20% and 60%, for example, it can be 20%, 30%, 40%, 50% or 60%, etc. In an embodiment, the light-transmitting rate of the first light-transmitting region m2 can be 60%, and the light-transmitting rate of the second light-transmitting region m3 can be 40%; but it is not limited thereto, for example, the light-transmitting rate of the first light-transmitting region m2 can be 70%, and the light-transmitting rate of the second light-transmitting region m3 can be 30%, etc.

[0100] Optionally, the substrate 11 can be a rigid substrate or a flexible substrate. The material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, aromatic fluorine-containing toluene containing polyarylate, polycyclic olefin, polyimide or polyurethane.

[0101] Then, step B2 is entered.

[0102] Referring to Figure 4In step B2, the first mask plate is used to form a patterned first metal layer 12 on the substrate 11. The first metal layer 12 includes a first electrode 121, which is one of the source and the drain, and the first electrode 121 corresponds to the light-shielding area ml. The first transparent area m2 and the full transparent area m4 correspond to areas where the first metal layer 12 is not provided.

[0103] In an embodiment, step B2 can include sequentially forming a first metal material layer and a photoresist material layer on the substrate 11; then exposing the photoresist material layer using the first mask plate, so that the photoresist material layer corresponding to the full transparent area m4 and the first transparent area m2 is fully exposed, for example, by increasing the exposure time; then developing the photoresist material layer to expose the first metal material layer in the full transparent area m4 and the first transparent area m2, and to leave the photoresist material layer in the light-shielding area ml and the second transparent area m3; then etching the first metal material layer in the full transparent area m4 and the first transparent area m2; and finally stripping the remaining photoresist material layer to form the patterned first metal layer 12.

[0104] Optionally, the photoresist material layer can be a positive photoresist.

[0105] In an embodiment, the patterned first metal layer 12 further includes a data line 122, and the data line 122 corresponds to the second transparent area m3.

[0106] That is, the first electrode 121 is provided in the first setting area szl of the substrate 11, and the data line 122 is provided in the third setting area sz3 of the substrate 11.

[0107] Optionally, the first metal layer 12 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy containing any of the above metal elements, or an alloy containing a combination of any of the above metal elements, etc. In addition, the first metal layer 12 can have a single-layer structure or a laminated structure of two or more layers.

[0108] Optionally, the thickness of the first metal layer 12 is between 2000 angstroms and 4000 angstroms, for example, 2000 angstroms, 3000 angstroms, or 4000 angstroms.

[0109] Then, step B3 is performed.

[0110] Please refer to Figure 5, step B3, a first mask plate Ma is used to form a patterned first insulating layer 13 on the substrate 11. The first insulating layer 13 is provided with an opening 13a exposing the first electrode 121. The first insulating layer 13 comprises a first portion 131 and a second portion 132 connected to each other, the thickness d1 of the first portion 131 is greater than the thickness d2 of the second portion 132, and the first portion 131 is located on the side of the second portion 132 close to the first electrode 121; the opening 13a corresponds to the light-shielding area m1, the first portion 131 corresponds to the full light-transmitting area m4, and the second portion 132 corresponds to the first light-transmitting area m2.

[0111] Optionally, the first insulating layer 13 further comprises a third portion 133 covering the side of the data line 122 away from the substrate 11, and the thickness of the third portion 133 is less than the thickness of the second portion 132.

[0112] Optionally, step B3 comprises: first forming a first insulating layer on the substrate 11, the first insulating layer can be an organic photoresist, such as a negative photoresist; then, using the first mask plate Ma to expose and develop the first insulating layer, wherein the light-shielding area m1 corresponds to the first electrode 121, the second light-transmitting area m3 corresponds to the data line 122, and the first light-transmitting area m2 corresponds to the gate region, so that the first insulating layer of the light-shielding area m1 is completely etched to form the opening 13a, the first insulating layer of the first light-transmitting area m2 and the second light-transmitting area m3 is partially etched to form the second portion 132 and the third portion 133, and the first insulating layer of the full light-transmitting area m4 is not etched to form the first portion 131.

[0113] Optionally, the thickness of the first portion 131 is between 5000 angstroms and 7000 angstroms, such as 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms or 7000 angstroms. The thickness of the second portion 132 is between 2000 angstroms and 4000 angstroms, such as 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms or 4000 angstroms. The thickness of the third portion 133 is between 1000 angstroms and 3000 angstroms, such as 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms or 3000 angstroms.

[0114] The arrangement of the first portion 131, the second portion 132 and the third portion 133 provides a basis for subsequent formation of flat sacrificial layers xs of different thicknesses and completion of gate alignment and active layer sandwich alignment of source and drain electrodes.

[0115] Subsequently, step B4 is entered.

[0116] Please refer to Figure 6, step B4, a semiconductor layer ad, a second metal layer 15 and a planar sacrificial layer xs are formed on the substrate 11 in sequence. Based on the planar surface of the substrate 11 close to the first metal layer 12, the height of the second metal layer 15 corresponding to the light-shielding area ml is less than the height of the second metal layer 15 corresponding to the full light-transmitting area m4, and the height of the second metal layer 15 corresponding to the light-shielding area ml is greater than the height of the second metal layer 15 corresponding to the full light-transmitting area m4.

[0117] It should be noted that, on the basis of the formation of the patterned first insulating layer 13, the semiconductor layer ad and the second metal layer 15 are formed in sequence, and the film thickness of each film layer is uniform, thereby forming a structure with high and low terrains. The planar sacrificial layer xs with flowability covers the above terrains to form different thicknesses.

[0118] For example, the planar sacrificial layer xs is thinnest corresponding to the first portion 131, thickest corresponding to the second portion 132, second thinnest corresponding to the third portion 133, and second thickest corresponding to the light-shielding area ml.

[0119] Optionally, the semiconductor layer ad can include one of polysilicon, monocrystalline silicon, amorphous silicon or oxide semiconductor. The thickness of the semiconductor layer ad is between 500 angstroms and 1500 angstroms, for example, it can be 500 angstroms, 1000 angstroms or 1500 angstroms.

[0120] The material of the second metal layer 15 can be formed by using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. In addition, the second metal layer 15 can have a single-layer structure or a laminated structure of two or more layers. The thickness of the second metal layer 15 is between 2000 angstroms and 4000 angstroms, for example, it can be 2000 angstroms, 3000 angstroms or 4000 angstroms.

[0121] The material of the planar sacrificial layer xs can be an organic material with flowability, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc. The maximum thickness of the planar sacrificial layer xs is between 19000 angstroms and 21000 angstroms, for example, it can be 19000 angstroms, 20000 angstroms or 21000 angstroms.

[0122] Then turn to step B5.

[0123] Please refer to Figure 7 , step B5, the planar sacrificial layer xs is etched to expose the portion of the second metal layer 15 corresponding to the full light-transmitting area m4, and the remaining planar sacrificial layer xs blocks the portion of the second metal layer 15 corresponding to the light-shielding area ml and the first light-transmitting area m2; the portion of the second metal layer 15 corresponding to the second light-transmitting area m3 is also exposed.

[0124] Optionally, dry etching can be used to etch the whole surface of the planarized sacrificial layer xs.

[0125] Then go to step B6.

[0126] Please refer to Figure 8 , step B6, etching the second metal layer 15 and the semiconductor layer ad to form the patterned second metal layer 15 and the active layer 14, with the remaining planarized sacrificial layer xs as a shield, and then removing the remaining planarized sacrificial layer xs.

[0127] The active layer 14 includes a channel portion 141 and a non-channel portion 142, the channel portion 141 is connected to be disposed on the side of the first electrode 121 away from the substrate 11, and the non-channel portion 142 is connected to be disposed on the side of the second portion 132 away from the substrate 11. The second metal layer 15 includes a second electrode 151 and a gate 152, the second electrode 151 is the other of the source and the drain. The second electrode 151 is connected to be disposed on the side of the channel portion 141 away from the substrate 11, and the gate 152 is disposed on the side of the non-channel portion 142 away from the substrate 11.

[0128] Optionally, dry etching or wet etching can be used to remove the second metal layer 15 and the semiconductor layer ad corresponding to the second light-transmitting region m3 and the full light-transmitting region m4.

[0129] Then go to step B7.

[0130] Please refer to Figure 9 , step B7, sequentially forming a second insulating layer 16 and a pixel electrode 17 on the substrate 11. The pixel electrode 17 is connected to the second electrode 151.

[0131] In an embodiment of the present application, step B7 includes steps B71 to B76. The steps B71 to B76 are described below.

[0132] Step B71, please refer to Figure 9-1 , forming a second insulating layer 16 on the substrate 11, the second insulating layer 16 covers the second metal layer 15 and the first insulating layer 13.

[0133] Optionally, the material of the second insulating layer 16 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide and titanium oxide, and can also be an organic insulating material such as polyimide (PI). The thickness of the second insulating layer 16 is between 1000 angstroms and 3000 angstroms, for example, it can be 1000 angstroms, 2000 angstroms or 3000 angstroms.

[0134] Then go to step B72.

[0135] Step B72, please refer to Figure 9-2A second mask is used to form a patterned photoresist layer pr on the second insulating layer 16. The photoresist layer pr includes a hollow portion r0, a first shielding portion r1 and a second shielding portion r2. The hollow portion r0 corresponds to the second electrode 151 and exposes the second insulating layer 16. The first shielding portion r1 corresponds to the area of the pixel electrode 17. The second shielding portion r2 corresponds to the area of the non-pixel electrode. The thickness of the second shielding portion r2 is greater than the thickness of the first shielding portion r1.

[0136] It is noted that in step B72, the area of the pixel electrode 17 refers to the area of the pixel electrode 17 in the subsequent process step (step B75).

[0137] The second mask also includes a light-shielding area, a secondary light-transmitting area and a full light-transmitting area. The light-transmitting rate of the secondary light-transmitting area is between that of the light-shielding area and the full light-transmitting area. In an embodiment, the photoresist layer pr is a positive photoresist. The hollow portion r0 corresponds to the light-shielding area. The first shielding portion r1 corresponds to the secondary light-transmitting area. The second shielding portion r2 corresponds to the full light-transmitting area. In some embodiments, the photoresist layer pr can also be a negative photoresist. The hollow portion r0 corresponds to the light-shielding area. The first shielding portion r1 corresponds to the secondary light-transmitting area. The second shielding portion r2 corresponds to the full light-transmitting area.

[0138] The process then proceeds to step B73.

[0139] In step B73, referring to Figure 9-3 A contact hole 16a is formed in the second insulating layer 16 by etching, with the patterned photoresist layer pr as a shielding. The process then proceeds to step B74.

[0140] In step B74, referring to Figure 9-4 The photoresist layer pr is ashed to remove the first shielding portion r1 and to thin the second shielding portion r2 to expose the area for forming the subsequent pixel electrode 17. The process then proceeds to step B75.

[0141] In step B75, referring to Figure 9-5 The remaining photoresist layer pr is subjected to a flocking treatment, and a transparent conductive layer tm is formed on the remaining photoresist layer pr.

[0142] It is noted that the flocking treatment is a surface treatment of the photoresist layer pr to form a rough surface. The transparent conductive layer tm covering the photoresist layer pr subjected to the flocking treatment will cause the transparent conductive layer tm to be broken.

[0143] Optionally, the material of the transparent conductive layer tm can be indium tin oxide, indium zinc oxide or other oxides.

[0144] In step B76, referring to Figure 9The photoresist layer pr is removed to form the pixel electrode 17, which is connected to the second electrode 151 through the contact hole 16a.

[0145] Thus, the preparation process of the array substrate 100 is completed.

[0146] The preparation method of the array substrate 100 of the embodiment of the present application adopts a two-mask process to form an array substrate with a simpler structure, thereby reducing the mask process.

[0147] The array substrate of the display panel and the preparation method thereof of the embodiment of the present application adopt a two-mask process to form an array substrate with a simpler structure.

[0148] The array substrate and the preparation method thereof and the display panel provided by the embodiment of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples; the above embodiment is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising an array substrate, characterized in that, The array substrate comprises: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a first electrode, the first electrode being one of a source electrode and a drain electrode; a first insulating layer disposed on the substrate, the first insulating layer being provided with an opening, the opening exposing the first electrode, the first insulating layer comprising a first portion and a second portion connected to each other, the first portion having a thickness greater than that of the second portion, the first portion being located on a side of the second portion close to the first electrode; an active layer disposed on the substrate, the active layer comprising a channel portion and a non-channel portion, the channel portion being connected to be disposed on a side of the first electrode away from the substrate, the non-channel portion being connected to be disposed on a side of the second portion away from the substrate; a second metal layer disposed on the substrate, the second metal layer comprising a second electrode and a gate electrode, the second electrode being the other of the source electrode and the drain electrode, the second electrode being connected to be disposed on a side of the channel portion away from the substrate, the gate electrode being disposed on a side of the non-channel portion away from the substrate; a second insulating layer covering the first insulating layer and the second metal layer, the second insulating layer being provided with a contact hole, the contact hole exposing the second electrode; and a pixel electrode disposed on a side of the second insulating layer away from the substrate and connected to the second electrode through the contact hole; the second portion, the non-channel portion and the gate electrode are sequentially stacked to form a first stacked structure, the first electrode and the channel portion are sequentially stacked to form a second stacked structure, the thickness of the first stacked structure being less than the thickness of the first portion, the thickness of the second stacked structure being less than the thickness of the first portion; the thickness of the second portion is less than the thickness of the first electrode.

2. The display panel of claim 1, wherein, The first metal layer further comprises a data line connected to the first electrode, the first insulating layer comprises a third portion, the third portion covering a side of the data line away from the substrate, the thickness of the third portion being less than the thickness of the second portion.

3. The display panel of claim 2, wherein, The second metal layer further comprises a scan line connected to the gate electrode.

4. The display panel of claim 1, wherein, The first insulating layer is a photoresist material.

5. The display panel of claim 1, wherein, The width of the first portion is between 7000 angstroms and 8000 angstroms.

6. A method for fabricating an array substrate, characterized in that, The method comprises the following steps: providing a substrate and a first mask plate, the first mask plate comprising an opaque region, a first light-transmissive region and a full light-transmissive region, the light transmittance of the opaque region being 0, the light transmittance of the full light-transmissive region being 100%, the light transmittance of the first light-transmissive region being greater than that of the opaque region and less than that of the full light-transmissive region; forming a patterned first metal layer on the substrate using the first mask plate, the first metal layer comprising a first electrode, the first electrode being one of a source electrode and a drain electrode, the first electrode corresponding to the opaque region; The first mask plate is used to form a patterned first insulating layer on the substrate, the first insulating layer is provided with an opening, the opening exposes the first electrode, the first insulating layer comprises a first part and a second part connected to each other, the thickness of the first part is greater than the thickness of the second part, and the first part is located on the side of the second part close to the first electrode; the opening corresponds to the light-shielding area, the first part corresponds to the full light-transmitting area, and the second part corresponds to the first light-transmitting area; A semiconductor layer, a second metal layer and a planar sacrificial layer are sequentially formed on the substrate, based on the plane of the substrate close to the first metal layer, the height of the second metal layer corresponding to the light-shielding area is less than the height of the second metal layer corresponding to the full light-transmitting area, and the height of the second metal layer corresponding to the light-shielding area is greater than the height of the second metal layer corresponding to the full light-transmitting area; The planar sacrificial layer is etched in the whole area, so that the part of the second metal layer corresponding to the full light-transmitting area is exposed, and the remaining planar sacrificial layer shields the part of the second metal layer corresponding to the light-shielding area and the first light-transmitting area; The second metal layer and the semiconductor layer are etched to form a patterned second metal layer and an active layer with the remaining planar sacrificial layer as a shield, and then the remaining planar sacrificial layer is removed; the active layer comprises a channel part and a non-channel part, the channel part is connected and arranged on the side of the first electrode away from the substrate, the non-channel part is connected and arranged on the side of the second part away from the substrate, the second metal layer comprises a second electrode and a gate, the second electrode is the other of the source electrode and the drain electrode, the second electrode is connected and arranged on the side of the channel part away from the substrate, and the gate is arranged on the side of the non-channel part away from the substrate; A second insulating layer and a pixel electrode are sequentially formed on the substrate, and the pixel electrode is connected to the second electrode.

7. The method of manufacturing an array substrate according to claim 6, wherein The first mask plate further comprises a second light-transmitting area, the light transmittance of the second light-transmitting area is less than the light transmittance of the first light-transmitting area and greater than the light transmittance of the light-shielding area; and the patterned first metal layer further comprises a data line, the data line corresponds to the second light-transmitting area; In the step of forming the patterned first insulating layer on the substrate by using the first mask plate, the first insulating layer further comprises a third part, the third part covers the side of the data line away from the substrate, and the thickness of the third part is less than the thickness of the second part; In the step of etching the planar sacrificial layer in the whole area, the part of the second metal layer corresponding to the second light-transmitting area is also exposed.

8. The method for fabricating the array substrate according to claim 7, characterized in that, The step of sequentially forming a second insulating layer and a pixel electrode on the substrate comprises: A second insulating layer is formed on the substrate, and the second insulating layer covers the second metal layer and the first insulating layer; forming a patterned photoresist layer on the second insulating layer using a second mask, the photoresist layer including a hollow portion, a first shielding portion and a second shielding portion, the hollow portion corresponding to the second electrode and exposing the second insulating layer, the first shielding portion corresponding to the area of the pixel electrode, the second shielding portion corresponding to the area of the non-pixel electrode, the second shielding portion having a thickness greater than that of the first shielding portion; etching the second insulating layer to form a contact hole using the patterned photoresist layer as a shield; ashing the photoresist layer to remove the first shielding portion and thin the second shielding portion; performing a flocking process on the remaining photoresist layer; forming a transparent conductive layer on the remaining photoresist layer; removing the photoresist layer to form a pixel electrode connected to the second electrode through the contact hole.

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