Back-to-back three-dimensional stacked fan-out packaging structure and preparation method thereof, back-to-back three-dimensional stacked fan-out packaging module and preparation method thereof

Abstract

The present invention discloses a back-to-back three-dimensional stacked fan-out packaging structure and a preparation method thereof, and discloses a packaging module using the packaging structure and a preparation method thereof, wherein the packaging structure comprises at least one group of stacked chips, each group of stacked chips comprises at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction; an encapsulation material layer, which encapsulates the stacked chips; a first rewiring layer located on one side of the encapsulation material layer and electrically connected to the chip with a functional surface facing the first direction; a second rewiring layer located on the other side of the encapsulation material layer and electrically connected to the chip with a functional surface facing the second direction; and a vertical interconnection conductive structure for electrically connecting the first rewiring layer and the second rewiring layer. The solution of the present invention does not require chip TSV stacking, and the stacked chips can be electrically connected in the shortest vertical interconnection manner, while ensuring a high interconnection density and transmission performance, reducing packaging costs and improving packaging yields.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a back-to-back three-dimensional stacked fan-out packaging structure and a preparation method thereof, and a back-to-back three-dimensional stacked fan-out packaging module and a preparation method thereof. Background Art

[0002] With the development of science and technology, the amount of data transmission is becoming increasingly huge, which leads to an increasing demand for the capacity of electronic device memory. In order to meet the needs of high data transmission capacity and large storage capacity, the memory also needs to have a higher bandwidth and lower power consumption. In order to increase the bandwidth of the memory, the industry currently usually uses 3D stacking bonding packaging technology to prepare the packaging structure of the memory chip.

[0003] Among them, in the 3D stacking bonding packaging process, chip stacking is a more common packaging form, which stacks multiple chips by stacking bonding to form a chip packaging structure with higher interconnection density and performance. In the chip stacking packaging process, interconnecting the stacked chips by TSV (through silicon via) technology is currently a more common way to achieve interconnection between stacked chips. However, this method usually requires the preparation of through silicon vias (TSV, through silicon via) and micro copper pillars on the chip, the process is complex, the packaging yield is low, and the packaging process based on TSV technology also requires expensive materials such as NCF (non-conductive film) or NCP (non-conductive glue) and TCB bonder (thermal compression debonding equipment), the process cost is very high, and the chip stacking bonding speed is extremely slow, and the overall packaging efficiency is also low. For example, TSMC's typical CoWoS packaging technology can interconnect CPU or GPU with HBM (High Bandwidth Memory) with high bandwidth, but its packaging process is to first stack HBM using TSV technology, then flip the HBM TSV stack and CPU / GPU on the adapter using TCB technology, and then flip the whole on the carrier using TCB technology. It can be seen that this packaging method requires repeated use of TCB technology (Thermo-compression Bonding, thermal compression bonding technology), so the overall process of this packaging method is complex and costly. In addition, since CoWoS packaging flips TSV stack and CPU / GPU on the adapter using TCB technology, and the HBM memory and CPU of CoWoS are on the same side, the memory can only be placed around the CPU, so its space utilization is very poor, resulting in a very large package size and low integration, which is difficult to meet the growing demand for high storage capacity. In addition, the CoWoS package also requires the adapter board encapsulated with the HBM stack and CPU / GPU to be flipped on the carrier board as a whole, which also limits the line width and line spacing of the interconnection lines, while increasing the length of the interconnection lines, which will also affect the interconnection density and transmission performance of the device.

[0004] In addition, for stacked packaged devices, the stacking of multiple layers of chips will cause heat dissipation difficulties, which will also affect the transmission efficiency between chips. Summary of the invention

[0005] The embodiment of the present invention provides a new back-to-back three-dimensional stacked fan-out packaging structure, which does not require chip TSV stacking, and the stacked chips can achieve electrical connectivity in the shortest vertical interconnection manner, thereby further reducing packaging costs and improving packaging yield while ensuring high interconnection density and transmission performance.

[0006] In a first aspect, an embodiment of the present invention provides a back-to-back three-dimensional stacked fan-out packaging structure, comprising:

[0007] At least one group of stacked chips, each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, wherein the first direction and the second direction are opposite directions;

[0008] An encapsulation material layer encapsulating the laminated chip;

[0009] A first redistribution layer located on one side of the encapsulation material layer and electrically connected to the chip with the functional surface facing the first direction;

[0010] A second redistribution layer located on the other side of the encapsulation material layer and electrically connected to the chip with the functional surface facing the second direction;

[0011] A vertical interconnect conductive structure for electrically connecting the first redistribution layer and the second redistribution layer, at least a portion of the vertical interconnect conductive structure is disposed in the encapsulation material layer.

[0012] In a second aspect, an embodiment of the present invention provides a back-to-back three-dimensional stacked fan-out packaging module, comprising:

[0013] A packaging carrier, wherein the packaging carrier is the back-to-back three-dimensional stacked fan-out packaging structure described in the first aspect of the embodiment of the present invention, and the packaging structure includes at least two groups of stacked chips;

[0014] A flip chip, wherein the flip chip is disposed on at least a portion of the rewiring conductive structure of the first rewiring layer or the second rewiring layer of the package carrier and is electrically connected to the corresponding rewiring conductive structure; and

[0015] A solder ball or an external pin is disposed on the first rewiring layer or the second rewiring layer and is electrically interconnected with at least a portion of the rewiring conductive structure.

[0016] In a third aspect, an embodiment of the present invention provides another back-to-back three-dimensional stacked fan-out packaging module, comprising:

[0017] A packaging carrier, wherein the packaging carrier is the back-to-back three-dimensional stacked fan-out packaging structure described in the first aspect of the embodiment of the present invention, and the packaging structure includes at least two groups of stacked chips;

[0018] A fine circuit adapter board disposed on the first rewiring layer or the second rewiring layer of the package carrier, the fine circuit adapter board being electrically connected to the corresponding rewiring layer;

[0019] A flip chip, the flip chip is disposed on the fine circuit adapter and is electrically connected to the fine circuit adapter; and

[0020] Solder balls or external pins are arranged on the redistribution layer of the fine circuit adapter plate and are electrically interconnected with at least part of the redistribution conductive structure.

[0021] In a fourth aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which includes:

[0022] Perform chip stacking and pasting on one of the surfaces of the temporary carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and pasted together by pasting materials;

[0023] Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0024] Preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with a functional surface facing a first direction and a vertical interconnect conductive structure penetrating the encapsulation material layer;

[0025] Removing the temporary carrier, wherein after the temporary carrier is removed, the surface of the chip covered by the temporary carrier is exposed on the surface of the encapsulation material layer;

[0026] A first rewiring layer electrically connected to the chip facing in a first direction and a second rewiring layer electrically connected to the chip facing in a second direction are respectively prepared on two surfaces of the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing in the first direction through the first conductive structure, the second rewiring layer is directly electrically interconnected with the chip facing in the second direction, and the first rewiring layer and the second rewiring layer are electrically connected through the vertical interconnect conductive structure.

[0027] In a fifth aspect, an embodiment of the present invention provides another method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which includes:

[0028] Preparing a supporting insulating material on one surface of the temporary carrier in advance, so as to define a concave chip attaching area by the supporting insulating material;

[0029] Preparing a first vertical conductive structure penetrating the supporting insulating material on the supporting insulating material;

[0030] Perform chip stacking and pasting in the chip pasting area of ​​the temporary carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and pasted together by pasting materials;

[0031] Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0032] Preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with a functional surface facing a first direction and a second vertical conductive structure vertically interconnected with the first vertical conductive structure, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure;

[0033] Removing the temporary carrier, wherein after the temporary carrier is removed, the surface of the chip covered by the temporary carrier is exposed on the surface of the encapsulation material layer;

[0034] A first rewiring layer electrically connected to the chip facing in a first direction and a second rewiring layer electrically connected to the chip facing in a second direction are respectively prepared on two surfaces of the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing in the first direction through the first conductive structure, the second rewiring layer is directly electrically interconnected with the chip facing in the second direction, and the first rewiring layer and the second rewiring layer are electrically connected through the vertical interconnect conductive structure.

[0035] In a sixth aspect, an embodiment of the present invention provides another method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0036] Perform chip stacking and pasting on one of the surfaces of the permanent carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and pasted together by pasting materials;

[0037] Using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0038] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0039] Prepare a vertical interconnection conductive structure penetrating the encapsulation material layer and the permanent carrier on the encapsulation material layer and the permanent carrier;

[0040] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0041] Prepare a second conductive structure on the permanent carrier that is electrically connected to the chip with the functional surface facing the second direction;

[0042] A second redistribution layer is prepared on the permanent carrier, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the chip with the functional surface facing the second direction through the second conductive structure.

[0043] In a seventh aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0044] Preparing a supporting insulating material on one surface of the permanent carrier in advance, so as to define a concave chip attaching area by the supporting insulating material;

[0045] Preparing a first vertical conductive structure on the supporting insulating material, penetrating the supporting insulating material and the permanent carrier;

[0046] Perform chip stacking and pasting in the chip pasting area of ​​the permanent carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and pasted together by pasting materials;

[0047] Using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0048] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0049] Preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure;

[0050] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0051] Prepare a second conductive structure on the permanent carrier that is electrically connected to the chip with the functional surface facing the second direction;

[0052] A second redistribution layer is prepared on the permanent carrier, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the chip with the functional surface facing the second direction through the second conductive structure.

[0053] In an eighth aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0054] preparing a fine interconnection line layer on one surface of the temporary carrier;

[0055] Perform chip stacking and pasting on the fine interconnection line layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection line layer is pasted on the fine interconnection line layer by adhesive materials;

[0056] Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0057] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0058] Preparing a vertical interconnect conductive structure penetrating the encapsulation material layer and the fine interconnect line layer on the encapsulation material layer and the fine interconnect line layer;

[0059] Removing the temporary carrier, wherein after the temporary carrier is removed, the fine interconnection line layer covered by the temporary carrier is exposed on the surface of the encapsulation material layer;

[0060] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0061] Preparing a second conductive structure on the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction;

[0062] A second redistribution layer is prepared on the fine interconnection layer, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection layer and the chip with the functional surface facing the second direction through the second conductive structure.

[0063] In a ninth aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0064] preparing a fine interconnection line layer on one surface of the temporary carrier;

[0065] Preparing a supporting insulating material on the fine interconnection line layer to define a concave chip attaching area through the supporting insulating material;

[0066] Preparing a first vertical conductive structure on the supporting insulating material, penetrating the supporting insulating material and the fine interconnection line layer;

[0067] Perform chip stacking and pasting in the chip pasting area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection layer is pasted on the fine interconnection layer by adhesive materials;

[0068] Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0069] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0070] Preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure;

[0071] Removing the temporary carrier, wherein after the temporary carrier is removed, the fine interconnection line layer covered by the temporary carrier is exposed on the surface of the encapsulation material layer;

[0072] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0073] Preparing a second conductive structure on the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction;

[0074] A second redistribution layer is prepared on the fine interconnection layer, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection layer and the chip with the functional surface facing the second direction through the second conductive structure.

[0075] In a tenth aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0076] Preparing a fine interconnection line layer on one surface of a permanent substrate;

[0077] Perform chip stacking and pasting on the fine interconnection line layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection line layer is pasted on the fine interconnection line layer by adhesive materials;

[0078] Using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0079] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0080] Prepare a vertical interconnection conductive structure on the encapsulation material layer and the permanent carrier, which penetrates the encapsulation material layer, the adhesive material, the fine interconnection line layer and the permanent carrier;

[0081] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0082] Preparing a second conductive structure on the permanent carrier, the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction;

[0083] A second redistribution layer is prepared on the permanent carrier, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure.

[0084] In an eleventh aspect, an embodiment of the present invention provides a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, which comprises:

[0085] Preparing a fine interconnection line layer on one surface of a permanent substrate;

[0086] Preparing a supporting insulating material on the fine interconnection line layer in advance, so as to define a concave chip attaching area by the supporting insulating material;

[0087] Preparing a first vertical conductive structure on the supporting insulating material, penetrating the supporting insulating material, the fine interconnection line layer and the permanent carrier;

[0088] Perform chip stacking and pasting in the chip pasting area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection layer is pasted on the fine interconnection layer by adhesive materials;

[0089] Using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip;

[0090] Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction;

[0091] Preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure;

[0092] Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0093] Preparing a second conductive structure on the permanent carrier, the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction;

[0094] A second redistribution layer is prepared on the permanent carrier, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure.

[0095] In a twelfth aspect, an embodiment of the present invention provides another method for preparing a back-to-back three-dimensional stacked fan-out packaging module, which comprises:

[0096] A back-to-back three-dimensional stacked fan-out packaging structure is prepared as a packaging carrier by the method described in any embodiment of the present invention, wherein the prepared packaging carrier includes at least two groups of stacked chips;

[0097] Preparing package external pin pads on the first rewiring layer and / or the second rewiring layer of the package carrier board, which are electrically connected to at least part of the rewiring conductive structures of the corresponding rewiring layer;

[0098] The flip chip with pin bumps prepared in advance is flip-chip soldered on at least part of the package external pin pads, and solder balls or external pins are prepared on other package external pin pads.

[0099] In a thirteenth aspect, an embodiment of the present invention provides another method for preparing a back-to-back three-dimensional stacked fan-out packaging module, which comprises:

[0100] A back-to-back three-dimensional stacked fan-out packaging structure is prepared as a packaging carrier by the method described in any embodiment of the present invention, wherein the prepared packaging carrier includes at least two groups of stacked chips;

[0101] Preparing package external pin pads on the first and second rewiring layers of the package carrier board, which are electrically connected to at least a portion of the rewiring conductive structures of the corresponding rewiring layers;

[0102] A fine circuit transfer board electrically connected to the corresponding package external pin pad is flip-chip soldered on the package external pin pad of the first rewiring layer or the second rewiring layer of the package carrier board,

[0103] Flip-chip soldering a flip chip with pre-prepared pin bumps on a fine circuit adapter, wherein the flip chip is electrically connected to the first or second redistribution layer through the fine circuit adapter;

[0104] Solder balls or external pins are prepared on the external pin pads of the package where the rewiring layer of the fine circuit adapter is not provided.

[0105] The beneficial effect of the embodiment of the present invention lies in that: the solution provided by the embodiment of the present invention has at least one group of stacked chips in the packaging structure, and each group of stacked chips includes at least one chip with a functional surface facing the first direction and at least one chip with a functional surface facing the second direction. Therefore, the packaging structure of the embodiment of the present invention can be interconnected and wired in two different directions respectively. Compared with the packaging structure that can only be interconnected and wired in one direction, the number of chips interconnected in a single direction is reduced in this solution, so that a higher wiring space can be provided for the interconnection of a single chip, so that the wiring density of the interconnection with a single chip can be higher, and the total number of chips that can be integrated in the packaging structure can be greatly increased, thereby effectively improving the integration of the packaging structure. Moreover, the scheme of the embodiment of the present invention is to electrically interconnect the chips in the packaging structure by means of a first rewiring layer arranged in a first direction and the chips facing the first direction, and by means of a second rewiring layer arranged in a second direction and the chips facing the second direction, and at the same time, the first rewiring layer and the second rewiring layer are electrically connected by means of a vertical interconnection conductive structure at least partially arranged in the encapsulation material layer and penetrating the thickness direction of the encapsulation material, thereby realizing electrical interconnection between the chips in the packaging structure. This method avoids the use of TSV technology to make vertical interconnection conductive channels of through silicon vias on the chip, reduces the packaging cost, and can effectively improve the packaging yield. In addition, by electrically connecting the chips in different directions to the rewiring layers arranged in the corresponding directions, respectively, vertical interconnection of the stacked chips based on different directions in the Z-axis direction can be realized, shortening the length of the interconnection line, and increasing the space utilization of the stacked chips in the XY plane, which can effectively reduce the size of the packaging structure, realize the integration of more chips in the packaging structure of the same size, and improve the performance of the packaging structure. At the same time, the solution of the embodiment of the present invention can also avoid the use of expensive materials such as NCF or NCP for filling and the use of expensive TCB equipment for debonding when packaging the stacked chip, further simplifying the packaging process steps of the stacked chip and reducing the packaging cost. In addition, since the packaging structure prepared by the embodiment of the present invention in a three-dimensional stacking manner can integrate the required chips (including chip functions and chip quantity) according to the needs, and the chips can be interconnected at a high density through the first conductive structure, the vertical interconnection conductive structure and the rewiring layer, the preparation cost is low, and the prepared packaging structure has a high transmission bandwidth and transmission rate, which can be widely used in memory. In addition, in the embodiment of the present invention with a support structure, there is only a vertical interconnection conductive structure on the support structure, and there is no need to prepare interconnection lines, so the process of the support structure is simple and the cost is low.Due to these characteristics of the support structure of the embodiment of the present invention, in a preferred embodiment, the support structure of the embodiment of the present invention can also be prepared with thicker thermal conductive materials, such as metals (copper, aluminum, etc.), ceramics (aluminum oxide, aluminum nitride, silicon carbide, etc.), composite materials (double-sided copper clad laminates used in various printed circuit board industries, etc.), which have better heat dissipation effects than HBM packaging and wire bonding packaging processes. In addition, for HBM packaging, its packaging process must use temporary bonding, TSV and TCB many times, but when the preparation process of the embodiment of the present invention is applied to HBM memory packaging, the memory chip stacking does not need to adopt the TSV stacking method at all, and it can also completely avoid using temporary bonding and TCB technology, thereby avoiding the expensive temporary bonding materials and temporary bonding carriers used in the HBM packaging process, reducing costs. In addition, the scheme of the present invention can also be flipped without TCB when the package includes a flip chip, and the flip chip and the stacked chip can be stacked in the Z direction (the stacked chip can be placed above or below the flip chip), so the XY surface space utilization rate of the packaging module is higher, and a larger stacked chip capacity can be supported, which is particularly suitable for scenes requiring large-capacity memory. At the same time, the packaging structure of the embodiment of the present invention can be directly used as a packaging carrier of the packaging module, and there is no need to set up an additional packaging carrier, thereby shortening the length of the interconnection line between the stacked chip and the flip chip, and reducing the number of patch times. Taking CoWoS packaging as an example, in addition to the need for patching between the stacked chips, it is also necessary to flip the stacked chip and the CPU onto the adapter board, and flip the adapter board together with the chip onto a special packaging carrier, so multiple temporary bonding and debonding processes are required. In the preparation method of the embodiment of the present invention, in addition to the need for patching of the stacked chip, only one flip chip patch is required, and even in the embodiment containing the adapter board, only two flip chip patches are required, so the storage cost is lower, and the memory capacity and bandwidth can be larger. BRIEF DESCRIPTION OF THE DRAWINGS

[0106] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0107] Figure 1 A vertical cross-sectional view schematically shows a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention;

[0108] Figure 2 A vertical cross-sectional view schematically shows a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention;

[0109] Figure 3 A vertical cross-sectional view schematically shows a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention;

[0110] Figure 4 Schematically showing a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure according to yet another embodiment of the present invention;

[0111] Figure 5 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention is schematically shown;

[0112] Figure 6 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention is schematically shown;

[0113] Figure 7 A vertical cross-sectional view schematically shows a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention;

[0114] Figure 8 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention is schematically shown;

[0115] Fig. 9 The vertical interconnect packaging structure of an embodiment of the present invention is schematically shown, wherein Fig. 9 (a) is a vertical cross-sectional view of a vertical interconnect packaging structure. Fig. 9 (b) is a top view of the vertical interconnect packaging structure;

[0116] Fig.10 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention;

[0117] Fig.11 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention;

[0118] Fig.12 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention;

[0119] Fig.13 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention;

[0120] Fig.14 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention;

[0121] Fig.15A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention is schematically shown;

[0122] Fig.16 The flowchart of the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to one embodiment of the present invention is schematically shown;

[0123] Fig.17 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention is schematically shown;

[0124] Fig.18 The flowchart of the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to one embodiment of the present invention is schematically shown;

[0125] Fig.19 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure according to an embodiment of the present invention is schematically shown;

[0126] Fig. 20 A flow chart schematically shows a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention;

[0127] Fig.21 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure in some embodiments is schematically shown;

[0128] Fig. 22 A flow chart schematically shows a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure in some embodiments;

[0129] Fig.23 A flow chart schematically shows a method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention;

[0130] Fig.24 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure in some embodiments is schematically shown;

[0131] Fig.25 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention is schematically shown;

[0132] Fig.26 The flowchart of the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention is schematically shown;

[0133] Fig. 27A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention is schematically shown;

[0134] Fig.28 The flowchart of the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to one embodiment of the present invention is schematically shown;

[0135] Fig.29 A cross-sectional view of an intermediate structure corresponding to a preparation process of a back-to-back three-dimensional stacked fan-out packaging structure according to another embodiment of the present invention is schematically shown;

[0136] Fig.30 The flowchart of the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure according to one embodiment of the present invention is schematically shown;

[0137] Fig.31 A flowchart of a method for preparing a back-to-back three-dimensional stacked fan-out packaging module in some embodiments is schematically shown;

[0138] Fig.32 A flow chart of a method for preparing a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0139] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0140] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0141] It should also be noted that the terms used in this application are generally terms commonly used by those skilled in the art. If there is any inconsistency with the commonly used terms, the terms in this application shall prevail.

[0142] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only the way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. Moreover, the terms "include", "comprise", not only include those elements, but also include other elements that are not clearly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of more restrictions, the elements limited by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0143] Herein, the term "chip" refers to any type of semiconductor chip or integrated circuit chip that implements a specific function, and also refers to any type of semiconductor die or integrated circuit die that implements a specific function.

[0144] In this article, the term "flip chip" refers to any type of semiconductor chip or integrated circuit chip that implements a specific function, and also refers to any type of semiconductor die or integrated circuit die that implements a specific function, which can be a single-layer chip or a vertically interconnected stacked chip.

[0145] Herein, the term "functional surface" refers to the surface of the chip where the chip pin pads are arranged, and the term "non-functional surface" refers to the other surface opposite to the functional surface.

[0146] Herein, the term "first direction" is a direction consistent with the stacking direction of the chip, and the term "second direction" is a direction away from the stacking direction of the chip. Therefore, it can be understood that when the stacking direction of the chip changes, the directions referred to by the first direction and the second direction will also change accordingly, that is, the "first direction" and the "second direction" should not be limited to the specific directions shown in the accompanying drawings. Among them, the stacking direction of the chip refers to the direction along which the chips are stacked layer by layer, thereby gradually increasing the height of the stacked chips. Therefore, in the embodiment of the present invention, the direction toward the first direction is defined as the upper layer, and the direction away from the first direction is defined as the lower layer.

[0147] As used herein, the term "back-to-back" refers to a portion of the chips in the stacked chips, which are stacked by attaching their non-functional surfaces together.

[0148] The embodiments of the present invention aim to provide a back-to-back three-dimensional stacked fan-out packaging solution to reduce packaging costs, improve packaging yields, simplify packaging processes, and bring about better heat dissipation and smaller packaging size (especially thinner) while ensuring higher chip interconnection density and integration and higher data transmission rates.

[0149] The solution provided by the embodiment of the present invention will be described in detail below from the perspective of the structure of the packaging device.

[0150] Figure 1 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure 100 according to an embodiment of the present invention, as shown in FIG. Figure 1 As shown, the packaging structure 100 provided by the embodiment of the present invention includes an encapsulation material layer 1, at least one group of stacked chips 2, a first rewiring layer 3 located on one side of the encapsulation material layer, and a second rewiring layer 4 located on the other side of the encapsulation material layer, wherein each group of stacked chips 2 includes at least one chip 2A with a functional surface facing the first direction W1 and at least one chip 2B with a functional surface facing the second direction W2, and the encapsulation material layer 1 encapsulates the stacked chips 2. Preferably, the first direction and the second direction are opposite directions, the first rewiring layer 3 is located on the side of the encapsulation material layer facing the first direction, and is electrically connected to the chip with the functional surface facing the first direction, and the second rewiring layer 4 is located on the side of the encapsulation material layer facing the second direction, and is electrically connected to the chip with the functional surface facing the second direction.

[0151] Among them, the functional surface of each chip in the stacked chip 2 is provided with a chip pin pad 21. In a preferred embodiment, a chip pin bump 22 can be provided on at least part of the chip pin pads 21 of at least part of the chips for electrical connection of the corresponding chips, especially to electrically connect the chips of other layers closest to the rewiring layer with the rewiring layer. Figure 1As shown, in this embodiment, there are four layers of chips stacked on each other, of which two layers of chips are oriented in the first direction W1, and the other two layers of chips are oriented in the second direction W2. Among the chips oriented in the first direction, one layer of chips is closest to the first rewiring layer, and the other layer of chips is farther away from the first rewiring layer. Therefore, chip pin bumps 22 can be set on some pin pads of the chips farther away from the first rewiring layer, so that the chips of this layer can be electrically connected with the first rewiring layer 3 through the chip pin bumps 22. Similarly, among the two layers of chips oriented in the second direction, one layer of chips is closest to the second rewiring layer, and the other layer of chips is farther away from the second rewiring layer. Therefore, chip pin bumps 22 can be set on some pin pads of the chips farther away from the second rewiring layer, so that the chips of this layer can be electrically connected with the second rewiring layer 4 through the chip pin bumps 22. It should be noted that, in the embodiment of the present invention, at least two chips with functional surfaces facing the first direction are stacked together by patch materials. Preferably, the patch material adheres the back of the chip with the functional surface facing the first direction on the upper layer to the functional surface of the chip with the functional surface facing the first direction on the lower layer, but the chip pin bumps of the chip with the functional surface facing the first direction on the lower layer need to be exposed. Similarly, the chips with functional surfaces facing the second direction are also stacked together by at least two patch materials. Specifically, the patch material adheres the functional surface of the chip with the functional surface facing the second direction on the back of the chip with the functional surface facing the second direction on the lower layer, but the chip pin bumps of the chip with the functional surface facing the second direction on the upper layer need to be exposed. And wherein, the patch material also adheres the chip with the functional surface facing the first direction and the chip with the functional surface facing the second direction back to back (that is, the non-functional surface is adhered to the non-functional surface), thereby realizing the back-to-back stacking packaging of multi-layer chips.

[0152] As a possible implementation, Figure 1As shown, the packaging structure 100 also includes a vertical interconnection conductive structure 5 for electrically connecting the first rewiring layer 3 and the second rewiring layer 4, and a first conductive structure 6 disposed on the encapsulation material layer 1, and the entire section of the vertical interconnection conductive structure 5 is completely disposed in the encapsulation material layer 1 and runs through the entire thickness direction of the encapsulation material layer. Wherein, the first rewiring layer 3 and the second rewiring layer 4 both include a rewiring insulating material 8-0 and a rewiring conductive structure 8-1 formed on the rewiring insulating material 8-0, wherein the chip pin pad 21 and the chip pin bump 22 of the chip with the functional surface facing the first direction are electrically connected to the rewiring conductive structure 8-1 of the first rewiring layer 3 through the first conductive structure 6 disposed on the encapsulation material layer, and the rewiring conductive structure 8-1 of the second rewiring layer 4 is directly electrically interconnected with the chip pin pad 21 and the chip pin bump 22 of the chip with the functional surface facing the second direction. Therefore, the chips of the embodiment of the present invention can be arranged back to back, and can be wired and vertically electrically interconnected in two directions when arranged back to back. Since the package of this structure does not need to prepare silicon through vias on the chip, and does not need to interconnect the chips through leads and permanent carriers, its data transmission rate and packaging yield are relatively high, and the packaging cost is also lower. In addition, since some chips of the packaged device of this structure are packaged back to back, interconnection wiring can be performed in different directions respectively. When the number of chips in the package structure is the same, the interconnection wiring density in a single direction is effectively reduced, so that the space for interconnection wiring is multiplied, and the number of chips that can be integrated in the package structure is further increased. In addition, the package structure of the embodiment of the present invention also allows the interconnection between the chip and the rewiring layer to be performed separately up and down, and the interconnection process between the chip with the functional surface facing the corresponding side and the rewiring layer on the same side is simplified, and the preparation is easier. Among them, it should be noted that the type, quantity and implemented functions of the chips in the embodiments of the present invention can be adjusted and configured according to the corresponding application scenarios and expectations. The functions of the chips can be such as chips with storage capacity and computing capacity, etc. The functions of the chips in the same stacked chip can be the same or different. Similarly, the functions of the chips between different stacked chips can also be the same or different.

[0153] Figure 2 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure 100 according to another embodiment of the present invention is schematically shown. Figure 1 The main difference of the embodiment shown is that Figure 2As shown, in this embodiment, the package structure 100 further includes a support structure 6A located between the encapsulation material layer 1 and the second rewiring layer 4. The stacked chip 2 is attached to the support structure 6A by means of an adhesive material 7, and the second rewiring layer 4 is disposed on the surface of the support structure 6A that is not attached to the chip. In this embodiment, the vertical interconnection conductive structure 5 not only penetrates the encapsulation material layer, but also penetrates the support structure 6A and the adhesive material 7 in the thickness direction. In addition, as Figure 2 As shown, in this embodiment, the packaging structure 100 also includes a second conductive structure 8 that penetrates the support structure, and the chip with the functional surface facing the second direction is electrically connected to the second rewiring layer 4 through the second conductive structure 8 that penetrates the support structure 6A. Among them, the support structure 6A can be a substrate made of heat-conducting materials such as metal (copper, aluminum, etc.), ceramic (aluminum oxide, aluminum nitride, silicon carbide, etc.), composite materials (double-sided copper clad boards used in various printed circuit board industries, etc.), or a high-temperature resistant protective film such as PI, Teflon, etc. coated with a high-temperature resistant adhesive film on the surface. When it is a high-temperature resistant protective film, the thickness of the support structure can be set to 50-300um. The support structure of the embodiment of the present invention is provided as a permanent carrier of the packaging structure (i.e., it does not need to be removed during the packaging process), so it can provide support and protection for the packaging structure, especially provide support and fixing for the chip, which helps to improve the mechanical properties of the packaged device. When the support structure is made of heat-conducting materials, the packaging structure can have better heat dissipation performance, avoiding the defect that the heat dissipation performance of the packaging structure is poor due to stacking chips, thereby affecting the performance of the chip. It should be noted that in this embodiment, the adhesive material is not necessary, that is, the stacked chip may not be bonded to the supporting structure through the adhesive material. For example, if the supporting structure is a high-temperature resistant protective film, the stacked chip can be directly bonded to the high-temperature resistant protective film. Therefore, in other possible embodiments, the vertical interconnected conductive structure 5 may also pass through the supporting structure and the encapsulation material layer without the presence of adhesive material.

[0154] Figure 3 Schematically shows a vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging structure 100 according to another embodiment of the present invention, which is Figure 1 The main difference of the embodiment shown is that Figure 3As shown, in this embodiment, the package structure 100 also includes a fine interconnect layer 9 located between the encapsulation material layer 1 and the second rewiring layer 4, and a second conductive structure 8 that penetrates the fine interconnect layer and the adhesive material, wherein the stacked chip 2 is directly attached to the fine interconnect layer 9 through the adhesive material 7, and the second rewiring layer 4 covers the side of the fine interconnect layer 9 away from the stacked chip 2. The chip with the functional surface facing the second direction is electrically connected to the second rewiring layer through the second conductive structure 8 that penetrates the fine interconnect layer and the adhesive material, and the second rewiring layer also needs to be electrically connected to the fine interconnect layer through the second conductive structure, that is, in this embodiment, the second rewiring layer needs to be electrically connected to both the chip with the functional surface facing the second direction and the fine interconnect layer. Figure 3 As shown, the fine interconnection line layer 9 includes a fine interconnection insulating material 9-0 and a fine interconnection conductive structure 9-1. In an embodiment, the vertical interconnection conductive structure 5 not only penetrates the thickness direction of the encapsulation material layer, but also penetrates the fine interconnection insulating material 9-0 and the adhesive material 7 of the fine interconnection line layer. In an embodiment of the present invention, the chip is electrically interconnected with the fine interconnection line layer via the second rewiring layer. As some possible implementations, when bonding the chip, the chip pin pads and chip pin bumps of the chip with the functional surface facing the second direction in the stacked chip can be set corresponding to the fine interconnection conductive structure of the fine interconnection line layer, so as to realize electrical connection between the second rewiring layer and the fine interconnection line layer by penetrating the fine interconnection conductive structure at the corresponding position of the fine interconnection line layer or penetrating the fine interconnection insulating material at the corresponding position of the fine interconnection line layer through the second conductive structure. Taking the example that the chip pin pads and chip pin bumps of the chip with the functional surface facing the second direction are all arranged correspondingly to the fine interconnect conductive structure of the fine interconnect line layer, specifically, the chip pin pads and chip pin bumps are in a one-to-one correspondence with the fine interconnect conductive structure, the second conductive structure can be set to penetrate each fine interconnect conductive structure of the fine interconnect line layer and the adhesive material at the corresponding position, so that the chip with the functional surface facing the second direction and the second rewiring layer, as well as the second rewiring layer and the fine interconnect line layer can all be electrically connected through the second conductive structure. Taking the example that the chip pin pads and chip pin bumps of the chip with the functional surface facing the second direction are all arranged correspondingly to the fine interconnect conductive structure of the fine interconnect line layer, specifically, each chip pin pad or chip pin bump is arranged correspondingly to two mutually spaced fine interconnect conductive structures, the second conductive structure can be specifically set to penetrate the fine interconnect line layer and the fine interconnect insulating material between two mutually spaced fine interconnect conductive structures corresponding to the same chip pin pad or chip pin bump and the adhesive material at the corresponding position, so that the chip with the functional surface facing the second direction and the second rewiring layer, as well as the second rewiring layer and the fine interconnect line layer can all be electrically connected through the second conductive structure. Figure 3 The latter is shown as a specific structural example, such as Figure 3As shown, the adhesive material 7 directly adheres the functional surface of the chip facing the second direction to the fine interconnection line layer 9, and the chip pin pad 21 and the chip pin bump 22 of the chip are adhered to be precisely aligned with the two fine interconnection conductive structures 9-1 spaced apart from each other in the fine interconnection line layer 9, that is, a chip pin pad or a chip pin bump is set on two adjacent fine interconnection conductive structures 9-1 spaced apart, and the second conductive structure 8 passes through the fine interconnection insulating material between the two fine interconnection conductive structures 9-1 spaced apart on which the chip pin pad or chip pin bump is correspondingly set, and the adhesive material at the corresponding position, and is electrically interconnected with the two fine interconnection conductive structures 9-1 spaced apart from each other. In this way, the electrical connection between the chip and the second rewiring layer, and between the second rewiring layer and the fine interconnection line layer can be achieved by means of middle fan-out (i.e., Middle Fanout). In other preferred embodiments, the fine interconnection conductive structure can be set to be an annular structure or an annular external pin pad (or an annular metal structure), that is, it is specifically implemented as a fine interconnection insulating material without metal in the middle, and only a metal ring on the periphery as a fine interconnection conductive structure. In this way, the chip with the functional surface facing the second direction in the stacked chip is bonded so that each chip pin pad and chip pin bump are respectively set corresponding to a fine interconnection conductive structure of an annular structure, and the second conductive structure penetrates the fine interconnection insulating material and the adhesive material at the corresponding position of the annular fine interconnection conductive structure of the fine interconnection line layer corresponding to the same chip pin pad or chip pin bump, so that the chip with the functional surface facing the second direction and the second rewiring layer, as well as the second rewiring layer and the fine interconnection line layer are electrically connected through the second conductive structure. Therefore, the electrical connection between the chip and the second rewiring layer, as well as the second rewiring layer and the fine interconnection line layer can also be achieved by middle fan-out (i.e., Middle Fanout). The packaging structure prepared in this way is provided with a fine interconnection line layer. Because it can achieve higher density electrical interconnection, and it is an intermediate fan-out, the second conductive structure is provided on the fine interconnection insulating material, so there is no need to make holes in the fine interconnection conductive structure, such as the fine interconnection line (because the fine interconnection conductive structure is very small and relatively thin, it is very difficult to make holes in the fine interconnection conductive structure, and the product yield is not high), so it can greatly reduce the difficulty of packaging and improve the packaging yield. At the same time, the chip of this packaging structure is attached to the fine interconnection line layer by an adhesive material. After the adhesive material is cured, the position of the chip is precisely fixed, and there will be no position shift due to plastic packaging, which reduces the difficulty of subsequent photolithography process.Furthermore, the fine interconnection line layer of the embodiment of the present invention is prepared in advance before the plastic packaging (the method part can be seen), and can be multi-layered, so compared with the last fanout, the number of wiring layers is more and there will be no reliability problem of interlayer separation between multiple layers, and the pre-prepared fine interconnection lines can be made finer, because it is difficult to make fine interconnection lines on the surface of the plastic packaging material. In addition, compared with the first fanout, this packaging structure of the embodiment of the present invention avoids the preparation of flip-chip bumps on the chip, and the first fanout needs to use bottom filling or expensive MUF plastic packaging material to fill the bottom space of the flip chip, so the packaging process of this packaging structure of the embodiment of the present invention is simpler and low-cost.

[0155] Figure 4 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out package structure 100 according to another embodiment of the present invention is schematically shown. Figure 3 The main difference of the embodiment shown is that Figure 4 As shown, in this embodiment, the packaging structure further includes a support structure 6A located between the fine interconnection line layer and the second rewiring layer, and the fine interconnection line layer is disposed on the support structure 6A.

[0156] In this embodiment, the vertical interconnection conductive structure 5 not only penetrates the encapsulation material layer, the fine interconnection insulating material 9-0 and the adhesive material 7 of the fine interconnection line layer, but also penetrates the support structure 6A. Accordingly, the second conductive structure 8 not only penetrates the fine interconnection insulating material 9-0 and the adhesive material 7 at the corresponding position between two mutually spaced fine interconnection conductive structures 9-1 corresponding to the same chip pin pad 21 or chip pin bump 22 of the fine interconnection line layer 9, but also penetrates the support structure 6A. The support structure 6A may be Figure 2 The material of the support structure of the illustrated embodiments is the same.

[0157] In other possible implementations, a supporting insulating material higher than the area for mounting the chip can be pre-set, that is, the area for mounting the chip can be designed as a recessed structure, thereby accurately defining the chip mounting area, facilitating rapid mounting of the chip, and reducing the size of the packaged device. The height of the formed supporting insulating material is preferably not lower than the height of the stacked chip, and the supporting insulating material is encapsulated by the encapsulation material layer. In this case, the vertical interconnected conductive structure can also be arranged so that some sections are arranged in the encapsulation material layer, and some sections are arranged in the supporting insulating material. Figures 5 to 8 Such a back-to-back three-dimensional stacked fan-out packaging structure is schematically shown, wherein: Figure 5 The structure and Figure 1Correspondingly, the only difference is that the packaging structure includes a supporting insulating material 10 for defining a concave chip-attaching area, and the vertical interconnection conductive structure 5 includes a first vertical conductive structure 52 disposed in the supporting insulating material and a second vertical conductive structure 51 disposed in the encapsulation material layer, and the first vertical conductive structure 52 and the second vertical conductive structure 51 together form a vertical interconnection conductive structure 5 that electrically connects the first rewiring layer to the second rewiring layer. Accordingly, Figure 6 and Figure 2 Correspondingly, Figure 7 and Figure 3 Correspondingly, Figure 8 and Figure 4 Correspondingly, the difference lies only in the way the vertical interconnection conductive structure is set. Figure 5 and Figure 1 The idea of ​​difference is similar, and Figures 6 to 8 The vertical interconnection conductive structure and Figure 5 The implementation method is similar to that of , which can be intuitively seen and clearly understood from the figure combined with the previous description, so it will not be repeated. Figures 5 to 8 In the embodiment, the number and density of the vertical interconnection conductive structures can be set to Figures 1 to 4 The implementation method is high. The reason is that Figures 1 to 4 In the embodiment, the vertical interconnection conductive structure is arranged in the encapsulation material, so its depth is deep and it is difficult to fill the conductive material, which makes the ratio of the depth and diameter of the vertical interconnection conductive structure not too large, thereby limiting the number and density of the vertical interconnection conductive structure. Figures 1 to 4 In the implementation method, the density of the vertical interconnection conductive structure cannot be very high, which will affect the interconnection density of the packaged device to a certain extent. Figures 5 to 8 In the embodiment shown, the vertical interconnected conductive structure is divided into a first vertical conductive structure 52 arranged in the supporting insulating material 10 and a second vertical conductive structure 51 arranged in the encapsulation material layer. Therefore, the first vertical conductive structure can be prepared in advance before plastic packaging, thereby being able to produce a vertical interconnected conductive structure with a smaller aperture and a higher density, thereby achieving the effect of improving the interconnection density of the packaged device.

[0158] As a preferred embodiment, the second vertical conductive structure in the encapsulation material layer is coaxially electrically connected to the first vertical conductive structure at the corresponding position, thereby shortening the transmission distance between the first vertical conductive structure and the second vertical conductive structure and improving the transmission efficiency.

[0159] In some preferred embodiments, the vertical interconnection conductive structure 5 may be configured to include an outer loop line 5a used as a ground line or a signal shielding line and a vertical conductive line 5b located within the outer loop line 5a used as a conductive line. Fig. 9A cross-sectional view of a vertical interconnect conductive structure 5 of such a structure is shown. Fig. 9 As shown, the center of each individual vertical interconnection conductive structure 5 is a vertical conductive line 5b formed of a solid conductive material (such as copper), and the solid conductive material is surrounded by an insulating material 5c, and the insulating material 5c also includes an outer ring line 5a formed by a conductive material. The vertical interconnection conductive structure of this structure can simultaneously achieve the functions of grounding and electrical interconnection through a single vertical interconnection structure, unlike the traditional vertical interconnection conductive structure formed only by solid conductive material, which requires two vertical interconnection structures as a group to cooperate to achieve the functions of grounding and electrical interconnection. This can greatly save the packaging space occupied by the vertical interconnection structure and improve the packaging density. In addition, since this vertical interconnection conductive structure includes both conductive material and insulating material, it has high mechanical strength and low stress, and high reliability.

[0160] As a possible implementation, the patch material of the mounted chip is preferably a thermally conductive material such as metal alloy solder, silver glue, nano silver glue, etc., to further improve the heat dissipation effect of the packaged device. The adhesive material can be the same material as the patch material. It should be noted that in the embodiment of the present invention, the adhesive material needs to cover the surface of the fine interconnect layer or the support structure. When it covers the surface of the fine interconnect layer, the adhesive material is preferably an insulating viscous material.

[0161] As a preferred embodiment, the chip pin bumps provided on at least part of the chip pin pads of at least part of the chips have different heights, so that the end surfaces of the free ends of the pin bumps of the chips facing the same direction in the stacked chip are located in the same plane, thereby facilitating the electrical connection between the chip and the rewiring conductive structure of the rewiring layer. More preferably, a chip without chip pin bumps can also be mounted on the end of the stacked chip in the corresponding direction, such as setting the chip without chip pin bumps at the position closest to the first redistribution layer in the chip group facing the first direction and setting the chip without chip pin bumps at the position closest to the second redistribution layer in the chip group facing the second direction. At the same time, the height of the pin bumps of other chips is designed so that after all the chips are mounted, the end faces of the free ends of the pin bumps of the chips with functional surfaces along the same direction are flush with the functional surface of the chip closest to the corresponding redistribution layer on the surface (that is, flush with the functional surface of the chip at the end with the functional surface in the same direction). In this way, the pin heights of the chips with the functional surfaces in the same direction can be consistent, so that wiring can be directly performed on the pin pads and pin bumps of the chip, or the depth and size of the openings prepared on the encapsulation material layer for the first conductive structure and the second conductive structure are consistent, thereby making the process parameters of all openings, the process of filling conductive materials, etc. consistent, so that the process is simple, the process is easy to control, and the process cost can be lower.

[0162] It should be noted that what is shown above are only the packaging structures of some implementation methods of the embodiments of the present invention. It is not difficult for those skilled in the art to understand that some features of the above packaging structures can be freely combined, such as the number of layers of the stacked chips can be two layers or three layers or more layers, the number of layers of the chips with the functional surface facing the first direction can be one layer or more layers, the number of layers of the chips with the functional surface facing the second direction can also be one layer or more layers, the number of groups of stacked chips can be two or more groups, the functions of the mounted chips can be the same or completely different, the supporting structure can be provided in the packaging structure or not, the fine interconnection line layer can be provided in the packaging structure or not, the vertical interconnection conductive structure can be a partial design (such as including a first vertical conductive structure and a second vertical conductive structure) or an integrated design, etc. It is obvious that more implementation methods of the packaging structure can be obtained through these free combinations and transformations, and the variations of these packaging structures should all be regarded as within the scope of protection of the present invention.

[0163] In practical applications, package external pin pads and solder balls can be set on the first rewiring layer or the second rewiring layer of the package structure described in the above embodiment, so that the chip in the package structure can achieve electrical conduction with the outside, thereby forming a packaged device or package module that meets the expectations. Since the package structure of the above structure can be wired in the upper and lower directions and realize vertical interconnection of non-TSV stacked chips between chips, the available space in the XY plane of the package structure is larger, and more groups of stacked chips can be integrated. Based on this, as a preferred application method, the back-to-back three-dimensional stacked fan-out package structure of the above structure can also be directly used as a package carrier, and the chip flip-chip welding can be continued on the package carrier, so that the stacked chip in the package structure can be electrically connected with the flip-chip welded chip, thereby forming a package module with richer functions, higher performance and smaller package size. This preferred application scenario will be described below in conjunction with the accompanying drawings.

[0164] Fig.10 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out package module according to an embodiment is shown. Fig.10 As shown, in this application scenario, the packaging module includes a Figure 3The back-to-back three-dimensional stacked fan-out packaging structure described in the embodiment only includes two groups of stacked chips 2 in the packaging structure. In this case, the packaging structure exists as a packaging carrier 200, so that packaging external pin pads are provided on at least part of the rewiring conductive structures of the first rewiring layer and the second rewiring layer of the packaging structure, wherein solder balls 300 are provided on the packaging external pin pads of the first rewiring layer, and flip chips 400 are provided on the packaging external pin pads of the second rewiring layer. In this scenario, pin flip bumps with a higher interconnection density are prepared on the flip chip 400, and the interconnection density of these pin flip bumps is C4 or higher, and the pitch thereof is smaller than the pitch of the solder balls 300. Thus, the interconnection density and chip integration of the packaged device can be further improved, and the higher density packaging module obtained can also be adapted to different application scenarios by adjusting the functional types of the stacked chips and flip chips.

[0165] Fig.11 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment is shown. Fig.11 As shown, in this application scenario, the packaging substrate in the packaging module is based on the above Figure 8 The back-to-back three-dimensional stacked fan-out packaging structure described in the embodiment only includes two groups of stacked chips in the packaging structure. Fig.10 In addition, Fig.11 As shown, the packaging module of the embodiment of the present invention also arranges a heat dissipation enhancement structure 500 around the flip chip 400 to provide heat dissipation and support for the flip chip 400 at the same time, thereby improving the mechanical stability and heat dissipation performance of the packaging module. In this embodiment, the vertical interconnection conductive structure 5 in the packaging structure, in addition to providing electrical interconnection between the first rewiring layer and the second rewiring layer, can also serve as a heat dissipation ring around the flip chip 400 (i.e., the heat generated by the stacked chip is conducted to the other side of the vertical interconnection conductive structure, so as to utilize the heat dissipation enhancement structure of the flip chip to dissipate the heat of the stacked chip), further providing heat dissipation for the packaging module.

[0166] Fig.12 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment is shown. Fig.12 As shown, in this application scenario, the packaging substrate 200 in the packaging module is based on the above Figure 4The back-to-back three-dimensional stacked fan-out packaging structure described in the embodiment only includes two groups of stacked chips in the packaging structure. In this embodiment, the flip chip 400 is arranged on the second rewiring layer 4 as in the previous embodiment, but different from the previous real-time method, the solder ball 300 is arranged on the same side as the flip chip 400, that is, it is also arranged on the second rewiring layer. In this way, the space on the rewiring layer on the other side can be reserved to facilitate the installation of the heat dissipation structure.

[0167] Fig.13 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment is shown. Fig.13 As shown, in this application scenario, the packaging substrate 200 in the packaging module is based on the above Figure 7 The back-to-back three-dimensional stacked fan-out packaging structure described in the embodiment only includes two groups of stacked chips 2. In this embodiment, the arrangement of the flip chip 400 and the solder ball 300 is the same as that of the embodiment. Fig.12 Preferably, in this embodiment, a microchannel heat dissipation structure 600 is also provided on the flip chip 400, and a heat dissipation device 700 is also provided on the first redistribution layer, thereby further improving the heat dissipation effect of the packaging module, ensuring that it has better device performance and longer device life. Exemplarily, the heat dissipation device 700 can be a liquid cooling device, such as a water cooling device.

[0168] Fig.14 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment is shown. Fig.14 As shown, in this application scenario, the packaging substrate 200 in the packaging module is based on the above Figure 1 The back-to-back three-dimensional stacked fan-out packaging structure described in the embodiment only includes eight groups of stacked chips 2. In this embodiment, the flip chip 400 is arranged on the first redistribution layer 3, the solder ball 300 is arranged on the second redistribution layer 4, and the heat dissipation enhancement structure 500 is arranged around the flip chip 400.

[0169] Fig.15 A vertical cross-sectional view of a back-to-back three-dimensional stacked fan-out package module according to another embodiment is shown. Fig.15 As shown, Fig.14 The embodiment shown in the figure is different in that the flip chip 400 of the embodiment of the present invention is arranged on the package carrier 200 through a fine circuit adapter plate 800, that is, Fig.15As shown, the packaging module of this embodiment also includes a fine circuit adapter board arranged on the first rewiring layer of the packaging carrier (it can also be arranged on the second rewiring layer in other embodiments), the fine circuit adapter board 800 is electrically connected to the first rewiring layer through pin bumps (C4 or above) with a higher interconnection density, and the flip chip 400 is arranged on the fine circuit adapter board 800 and electrically connected to the fine circuit adapter board, thereby, the flip chip 400 is electrically connected to the first rewiring layer through the fine circuit adapter board 800, and then interconnected with the stacked chip. The packaging module of this embodiment not only has higher mechanical strength, but also can arrange fine circuits on the fine circuit adapter board 800 according to needs, and because the fine circuit adapter board can achieve higher pin density and more pins, it can further improve the interconnection density and integration of the packaging module. At the same time, the fine circuit adapter board is flatter, so it is more convenient to flip-chip, and it can also reduce the process difficulty of packaging flip chips.

[0170] It should be noted that what are shown above are only packaging modules of some implementations of the embodiments of the present invention. It is not difficult for those skilled in the art to understand that the above packaging modules can also be implemented based on the packaging structure of any other embodiment mentioned above, and are not limited to forming a packaging carrier based on the packaging structure of a specific embodiment selected. Moreover, the features of the packaging modules described in the above embodiments can be freely combined, such as the number of groups of stacked chips, the position of the stacked chips, the setting of the enhanced heat dissipation structure, the setting of the heat dissipation device, the setting of the microchannel heat dissipation structure, the setting position of the solder balls, the setting position of the fine circuit adapter board, etc., which can be freely combined and transformed according to needs. Obviously, more implementation methods of packaging modules can be obtained through these free combinations and transformations, and these variations of packaging modules should be regarded as within the scope of protection of the present invention.

[0171] It should also be noted that the stacked chip and flip chip in the embodiment of the present invention can be any desired functional chip according to the requirements, and the stacked chip and flip chip can be chips with the same function or chips with different functions. For example, the stacked chip can be a memory chip, and the flip chip can be a CPU or a GPU.

[0172] The following will describe in detail the method for preparing the back-to-back three-dimensional stacked fan-out packaging structure with reference to the accompanying drawings.

[0173] Fig.16 and Fig.17 Schematically shows Figure 1 The preparation method of the packaging structure of the structure shown in FIG. Fig.16 and 17 As shown, the preparation method comprises:

[0174] Operation S11, stacking and pasting chips on one of the surfaces of the temporary carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, and the first direction and the second direction are opposite directions. In this operation, different chips are laminated together by pasting materials, and chips with different orientations are pasted together back to back (i.e., non-functional surfaces are pasted), and the bottom chip close to the temporary carrier is pasted on the temporary carrier by a removable material (of course, in some embodiments, the bottom chip can also be pasted on the removable material by an adhesive material). Preferably, the chip is mounted so that the pin bumps of other chips mounted before the chip are all in an exposed state, that is, no matter what the chip orientation is, at least part of the chip pin bumps or chip pin pads are not blocked by other stacked chips to facilitate the electrical connection of each layer of chips. It should be noted that if the position of the chip pin pads makes it easy to block the pin bumps of the chips located in the middle layers when the stack is mounted, the position of the chip pin pads on the corresponding chip can be adjusted through the rewiring process when preparing the chip pin bumps, so as to achieve the effect that the pin bumps of the chips located in the middle layers after mounting are exposed. The stacked chip may include two or more layers. For example, the stacked chip includes a group, and the group of stacked chips includes two layers of chips facing a first direction and two layers of chips facing a second direction. The intermediate of the packaging structure prepared by this step is as follows. Fig.17 As shown in (a) in the figure, the lower chip facing the first direction is provided with chip pin bumps 22, the uppermost chip is not provided with chip pin bumps, the lower chip facing the second direction is not provided with chip pin bumps, and the chip above the lower chip facing the second direction is provided with chip pin bumps. Exemplarily, the patch material can be a thermally conductive patch adhesive such as metal alloy solder, silver glue, nano silver glue, etc.

[0175] Operation S12, using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board where the stacked chip is mounted, to form an encapsulation material layer that encapsulates the stacked chip. The side of the stacked chip away from the temporary carrier board is completely encapsulated by the encapsulation material. The intermediate of the package structure prepared by this step is as follows: Fig.17 As shown in (b) in .

[0176] Operation S13, preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with the functional surface facing the first direction and a vertically interconnected conductive structure penetrating the encapsulation material layer. Among them, through holes and blind holes can be respectively prepared on the encapsulation material layer, and the positions of the blind holes can correspond to the corresponding chip pin bumps and chip pin pads of the chip with the functional surface facing the first direction. Afterwards, the vertically interconnected conductive structure can be formed by filling the through holes with conductive material, and the first conductive structure can be formed by filling the blind holes with conductive material. Among them, laser drilling, photolithography, dry etching and the like can be used to prepare the through holes in the encapsulation material layer, and laser drilling, photolithography, dry etching, grinding and the like can be used to prepare the blind holes at the positions corresponding to the pin bumps and / or pin pads of the chip. The intermediate of the packaging structure prepared by this step is as follows. Fig.17 As shown in (c) in .

[0177] Operation S14, removing the temporary carrier, wherein after the temporary carrier is removed, the chip surface covered by the temporary carrier is exposed on the surface of the encapsulation material layer. According to the material properties of the strippable material on the selected temporary carrier, the temporary carrier can be removed in a manner that is compatible with its material characteristics. For example, heat stripping, chemical stripping, laser stripping, UV light stripping, heating and mechanical stripping, etc. can be used to remove the stripping material and temporary carrier with corresponding characteristics. The effect cross-sectional view of the intermediate structure obtained after removing the temporary carrier is shown in FIG. Fig.17 As shown in (d), the chip surface covered by the temporary carrier and the chip pin bumps of the chip with the functional surface facing the second direction are flush and exposed on the surface of the encapsulation material layer, and the vertical interconnection conductive structure penetrates the encapsulation material layer.

[0178] Step S15, respectively preparing a first rewiring layer electrically connected to the chip facing the first direction and a second rewiring layer electrically connected to the chip facing the second direction on the two surfaces of the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure, the second rewiring layer is directly electrically interconnected with the chip facing the second direction, and the first rewiring layer and the second rewiring layer are electrically connected through the vertical interconnect conductive structure. Through this step, a device such as Figure 1 The package structure shown.

[0179] Fig.18 and Fig.19 Schematically shows Figure 5 The method for preparing the packaging structure of the structure shown in the figure, the packaging structure prepared by the method and Fig.16 and 17 Compared with the method shown in the figure, the main difference is the vertical interconnect packaging structure, such as Fig.18 and 19 As shown, the preparation method comprises:

[0180] Operation S51, pre-prepare a supporting insulating material on one surface of the temporary carrier to define a concave chip-attaching area through the supporting insulating material. The intermediate package structure prepared in this step is as follows: Fig.19 As shown in (a), it includes a supporting insulating material 10 protruding from a temporary carrier 900 and a groove defined as a chip attaching area.

[0181] Operation S52, preparing a first vertical conductive structure penetrating the supporting insulating material on the supporting insulating material. The intermediate of the package structure prepared in this step is as follows: Fig.19 (b) shows that the preparation process of the first vertical conductive structure is as follows: Fig.16 The process for preparing vertical interconnect conductive structures is described in.

[0182] Operation S53, stacking chips in the chip mounting area of ​​the temporary carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and bonded together by bonding materials. The intermediate of the package structure prepared by this step is as follows Fig.19 (c) as shown, wherein the relevant description of the chip is referred to Fig.16 The content described in .

[0183] Operation S54, a packaging material is used to perform plastic packaging on the side of the temporary carrier board on which the stacked chip is mounted, to form a packaging material layer that encapsulates the stacked chip. Fig.19 As shown in (d), the encapsulation material layer completely encapsulates the stacked chips, the supporting insulating material, and the side of the first vertical conductive structure away from the temporary carrier.

[0184] Operation S55, preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with the functional surface facing the first direction and a second vertical conductive structure vertically interconnected with the first vertical conductive structure, and the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure. The intermediate of the package structure prepared by this step is as follows Fig.19 (e) As shown. Among them, the part of preparing the first conductive structure can refer to Fig.16 The relevant description of Fig.16The difference is that, since the encapsulation material layer in this method completely encapsulates the surface of the supporting insulating material and the first vertical conductive structure away from the temporary carrier, in this real-time method, a second vertical conductive structure is also prepared at a position of the encapsulation material layer corresponding to the first vertical conductive structure. The preparation of the second vertical conductive structure can also be a method of first drilling and then filling with conductive material.

[0185] Operation S56, removing the temporary carrier, wherein after removing the temporary carrier, the chip surface covered by the temporary carrier, the chip pin bumps with the functional surface facing the second direction, and the first vertical conductive structure are exposed on the surface of the encapsulation material layer. Fig.19 (f) as shown.

[0186] Operation S57, a first rewiring layer electrically connected to the chip facing the first direction and a second rewiring layer electrically connected to the chip facing the second direction are respectively prepared on the two surfaces of the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure, the second rewiring layer is directly electrically interconnected with the chip facing the second direction, and the first rewiring layer and the second rewiring layer are electrically connected through the vertical interconnect conductive structure. After this step, a device such as Figure 5 The package structure shown.

[0187] Of course, in other possible implementations, the specific preparation process of the supporting insulating material of operation S51 and the first vertical conductive structure of operation S52 can also be implemented to include: firstly, covering the supporting insulating material on the temporary carrier, and then, according to the desired position and number of the first vertical conductive structure, photolithography is performed on the covered supporting insulating material to form a corresponding number and shape of through-hole structures at the desired position, and then the through-hole structure is electroplated to form the first vertical conductive structure, and finally, the excess supporting insulating material is removed to prepare Fig.19 (b) The structural effect shown.

[0188] Fig. 20 and Fig.21 Schematically shows Figure 2 A method for preparing a packaging structure of the structure shown in Fig.16 Compared with the method shown in FIG. 1 , the main difference is that a permanent carrier is used as the support structure, so there is no step of removing the carrier, so Fig.16 The specific details of the same steps are not repeated here, and only the steps with differences are described. Specifically, Fig. 20 and 21 As shown, the preparation method comprises:

[0189] Operation S21, stacking and pasting chips on one surface of the permanent carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are laminated and pasted together by pasting materials. The intermediate of the package structure prepared by this step is as follows Fig.21 (a) shown.

[0190] Operation S22, a packaging material is used to perform plastic packaging on the side of the permanent carrier board on which the stacked chip is mounted, to form a packaging material layer that encapsulates the stacked chip. Fig.21 (b) as shown.

[0191] Operation S23, preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with the functional surface facing the first direction. The intermediate of the package structure prepared in this step is as follows: Fig.21 (c) as shown.

[0192] Operation S24, preparing a vertical interconnected conductive structure penetrating the encapsulation material layer and the permanent carrier on the encapsulation material layer and the permanent carrier. Fig.16 Different from the method of FIG. 1 , in this method, the vertical interconnection conductive structure not only penetrates the encapsulation material layer, but also needs to penetrate the permanent carrier. The intermediate of the packaging structure prepared by this step is as follows: Fig.21 (d) as shown.

[0193] Operation S25, preparing a first redistribution layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first redistribution layer is electrically connected to the chip facing the first direction through the first conductive structure. Fig.21 (e) as shown.

[0194] Operation S26, preparing a second conductive structure on the permanent carrier to electrically connect the second redistribution layer with the chip facing the second direction. In this method, since the permanent carrier exists in the packaging structure as a supporting structure, in order to make the second redistribution layer electrically connected with the chip with the functional surface facing the second direction, it is also necessary to prepare a second conductive structure on the permanent carrier to electrically connect the chip with the functional surface facing the second direction. Specifically, blind holes can be made at positions on the permanent carrier corresponding to the corresponding chip pin bumps and chip pin pads, and then the blind holes are filled with conductive material to form the second conductive structure. The intermediate of the packaging structure prepared by this step is as follows: Fig.21 (f) as shown.

[0195] Operation S27, preparing a second redistribution layer on the permanent carrier that is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and electrically connected to the chip with the functional surface facing the second direction through the second conductive structure. Figure 2 The package structure shown in the figure. Fig.16 Different from the method shown, in this step, the second rewiring layer is prepared on a permanent carrier, and the positions of some of its rewiring conductive structures correspond to the vertical interconnect conductive structures, and the positions of some of its rewiring conductive structures correspond to the second conductive structures.

[0196] Fig. 22 Schematically shows Figure 6 A method for preparing a packaging structure of the structure shown in Fig. 22 Compared with the method shown in the figure, the main difference is that the vertical interconnection conductive structure is different, so the specific implementation of the steps involved is different. Fig.18 Same as or Fig. 20 The same, so the specific details of similar steps are not repeated, and only the steps with differences are described. Specifically, Fig. 22 As shown, the preparation method comprises:

[0197] Operation S61, pre-preparing a supporting insulating material on one surface of the permanent carrier, so as to define a concave chip attaching area by the supporting insulating material;

[0198] Operation S62, preparing a first vertical conductive structure on the supporting insulating material that penetrates the supporting insulating material and the permanent carrier; this step is similar to Fig. 20 The only difference is that the first vertical conductive structure not only penetrates the supporting insulating material, but also penetrates the permanent carrier. The specific effect diagram is shown in Figure 6 Visible in;

[0199] Operation S63, performing chip stacking in the chip mounting area of ​​the permanent carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and bonded together by bonding materials;

[0200] Operation S64, using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; wherein, in this embodiment, the encapsulation material layer completely encapsulates the stacked chip, the first vertical conductive structure, and the supporting insulating material on the side away from the permanent carrier board;

[0201] Operation S65, preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with the functional surface facing the first direction;

[0202] Operation S66, preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure;

[0203] Operation S67, preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure;

[0204] Operation S68, preparing a second conductive structure on the permanent carrier that is electrically connected to the chip with the functional surface facing the second direction;

[0205] In operation S69 , a second redistribution layer is prepared on the permanent carrier, the second redistribution layer being electrically connected to the first redistribution layer through the vertical interconnection conductive structure and being electrically connected to the chip with the functional surface facing the second direction through the second conductive structure.

[0206] Fig.23 and Fig.24 Schematically shows Figure 3 The preparation method of the packaging structure of the structure shown in FIG. Fig.23 and 24 As shown, the preparation method comprises:

[0207] Operation S31, preparing a fine interconnection line layer on one surface of the temporary carrier. The fine interconnection line layer may be directly prepared on the removable material of the temporary carrier, or the pre-prepared fine interconnection line layer may be bonded to the removable material. The intermediate of the package structure prepared in this step is as follows: Fig.24 (a) shown.

[0208] Operation S32, stacking and pasting chips on the fine interconnect layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are laminated together by pasting materials, and the chip of the stacked chips closest to the fine interconnect layer is pasted on the fine interconnect layer by adhesive materials. In this step, in addition to pasting the stacked chips as described above, it is also necessary to note that when pasting the chips, the chip pin pads of the chips directly pasted on the fine interconnect layer and the chip pin bumps of other chips with functional surfaces facing the second direction need to be accurately aligned with the fine interconnect conductive structures of the fine interconnect layer, wherein the correspondence can be one-to-one, or one chip pin bump or one chip pin pad can correspond to two fine interconnect conductive structures with a gap between them. Taking the latter as an example, the intermediate of the obtained packaging structure is as follows: Fig.24(b) as shown.

[0209] Operation S33, a packaging material is used to perform plastic packaging on the side of the temporary carrier board on which the stacked chip is mounted, to form a packaging material layer that encapsulates the stacked chip. The intermediate package structure obtained by this step is as follows: Fig.24 (c) as shown.

[0210] Operation S34, preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with the functional surface facing the first direction. The intermediate of the packaging structure obtained by this step is as follows: Fig.24 (d) as shown.

[0211] Operation S35, preparing a vertical interconnect conductive structure penetrating the encapsulation material layer and the fine interconnect layer on the encapsulation material layer and the fine interconnect layer. The difference between this step and the above-mentioned preparation method embodiment is that the vertical interconnect conductive structure penetrates the fine interconnect insulating material of the encapsulation material layer and the fine interconnect layer at the same time. The intermediate of the package structure obtained by this step is as follows: Fig.24 (e) as shown.

[0212] Operation S36, removing the temporary carrier, wherein after the temporary carrier is removed, the fine interconnection line layer covered by the temporary carrier is exposed on the surface of the encapsulation material layer. The difference between this step and the above-mentioned preparation method embodiment is that the fine interconnection insulating material and the vertical interconnection conductive structure of the fine interconnection line layer are exposed on the surface of the encapsulation material layer, and the stacked chip is covered by the fine interconnection line layer. The intermediate of the packaging structure obtained by this step is as follows: Fig.24 (f) as shown.

[0213] Operation S37, preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure. The intermediate package structure obtained by this step is as follows: Fig.24 (g) as shown.

[0214] Operation S38, preparing a second conductive structure on the adhesive material and the fine interconnection line layer that is electrically connected to the chip with the functional surface facing the second direction. Different from the above-mentioned preparation method embodiments, this embodiment needs to prepare a second conductive structure that penetrates the adhesive material and the fine interconnection line layer, and electrically connect the second conductive structure to the chip with the functional surface facing the second direction. The second conductive structure can be a fine interconnection conductive structure that penetrates the fine interconnection line layer, or it can be a fine interconnection insulating material that penetrates. Taking penetrating the fine interconnection insulating material as an example, based on Fig.24 (g) shows the intermediate structure. The intermediate of the encapsulation structure obtained after this step is as follows Fig.24As shown in (h), the second conductive structure completes the fine interconnection insulating material between two fine interconnection conductive structures corresponding to the same chip pin bump or chip pin pad, and is also electrically connected between two adjacent fine interconnection conductive structures.

[0215] Operation S39, prepare a second rewiring layer on the fine interconnect layer, which is electrically connected to the first rewiring layer through the vertical interconnect conductive structure, and is electrically connected to the fine interconnect layer and the chip with the functional surface facing the second direction through the second conductive structure. In this step, at least part of the rewiring conductive structure of the second rewiring layer needs to be arranged corresponding to the vertical conductive interconnect structure, and at least part of the rewiring conductive structure of the second rewiring layer needs to be arranged corresponding to the second conductive structure, so as to simultaneously realize the electrical connection between the second rewiring layer and the fine interconnect layer and the chip with the functional surface facing the second direction, thereby enabling the fine interconnect layer to be electrically connected to the stacked chip. Through this step, a device such as the following can be prepared: Figure 3 The package structure shown.

[0216] Fig.25 and Fig.26 Schematically shows Figure 7 A method for preparing a packaging structure of the structure shown in Fig.25 The difference between the methods shown mainly lies in the preparation of the vertical interconnect conductive structure, so Fig.25 The implementation details of the corresponding steps can be obtained by combining the preparation of the vertical interconnection conductive structure of the other embodiments described above, so the following only briefly describes the method steps involved and the effects of the corresponding intermediate structures, and no further details are repeated. Fig.23 and 24 As shown, the preparation method comprises:

[0217] Operation S71, preparing a fine interconnection line layer on one surface of the temporary carrier; the intermediate of the package structure obtained by this step is as follows: Fig.25 (a) shown.

[0218] Operation S72, preparing a supporting insulating material on the fine interconnect layer, so as to define a concave chip attaching area by the supporting insulating material; the intermediate of the package structure obtained by this step is as follows: Fig.25 (b) as shown.

[0219] Operation S73, preparing a first vertical conductive structure penetrating the supporting insulating material and the fine interconnection line layer on the supporting insulating material. In this step, the difference from the previous method is that the first vertical conductive structure penetrates both the supporting insulating material and the fine interconnection insulating material of the fine interconnection line layer, and the intermediate of the package structure obtained is as follows: Fig.25Of course, in other embodiments, a first vertical conductive structure penetrating the supporting insulating material and a third vertical conductive structure penetrating the insulating material of the fine interconnection line layer may be prepared separately, and form a vertical interconnection conductive structure with the second vertical conductive structure described below. This is a variation that can be easily thought of by those skilled in the art based on the concept disclosed in the present invention, so it will not be described in detail.

[0220] Operation S74, performing chip stacking and bonding in the chip bonding area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and bonded together by bonding materials, and the chip of the stacked chips closest to the fine interconnection layer is bonded to the fine interconnection layer by bonding materials; the intermediate of the packaging structure obtained by this step is as follows Fig.25 (d) as shown.

[0221] Operation S75, using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; the intermediate package structure obtained by this step is as follows: Fig.25 (e) as shown.

[0222] Operation S76, preparing a first conductive structure electrically connected to the chip with the functional surface facing the first direction on the encapsulation material layer; the intermediate of the package structure obtained by this step is as follows: Fig.25 (f) as shown.

[0223] Operation S77, preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure; the intermediate package structure obtained by this step is as follows: Fig.25 (g) as shown.

[0224] Operation S78, removing the temporary carrier, wherein after removing the temporary carrier, the fine interconnection line layer covered by the temporary carrier is exposed on the surface of the encapsulation material layer; the intermediate package structure obtained by this step is as follows: Fig.25 In the embodiment where the first vertical conductive structure does not penetrate the fine interconnection line layer, a third vertical conductive structure penetrating the fine interconnection insulating material and vertically interconnected with the first vertical conductive structure may be prepared after this step.

[0225] Operation S79, preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; the intermediate package structure obtained by this step is as follows: Fig.25 (i) as shown.

[0226] Operation S70, preparing a second conductive structure electrically connected to the chip with the functional surface facing the second direction on the adhesive material and the fine interconnection line layer; the intermediate package structure obtained by this step is as follows: Fig.25 (j) as shown.

[0227] Operation S80, preparing a second rewiring layer on the fine interconnection line layer, which is electrically connected to the first rewiring layer through the vertical interconnection conductive structure, and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure. Figure 7 The package structure shown.

[0228] Fig. 27 and Fig.28 Schematically shows Figure 4 The specific details of each step in the method can be obtained by combining the implementation details of the corresponding steps of other embodiments described above, so the following only briefly describes the method steps involved and the effects of the corresponding intermediate structures obtained, and no detailed description of each step is repeated. Fig. 27 and 28 As shown, the preparation method comprises:

[0229] Operation S41, preparing a fine interconnection line layer on one surface of the permanent carrier; the intermediate of the package structure obtained by this step is as follows Fig. 27 (a) shown.

[0230] Operation S42, stacking and pasting chips on the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection layer is pasted on the fine interconnection layer by adhesive materials; the intermediate of the packaging structure obtained by this step is as follows Fig. 27 (b) as shown.

[0231] Operation S43, using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; the intermediate package structure obtained by this step is as follows: Fig. 27 (c) as shown.

[0232] Operation S44, preparing a first conductive structure electrically connected to the chip with the functional surface facing the first direction on the encapsulation material layer; the intermediate of the package structure obtained by this step is as follows: Fig. 27 (d) as shown.

[0233] Operation S45, preparing a vertical interconnection conductive structure penetrating the encapsulation material layer, the adhesive material, the fine interconnection line layer and the permanent carrier on the encapsulation material layer and the permanent carrier; the intermediate of the packaging structure obtained by this step is as follows Fig. 27 (e) as shown.

[0234] Operation S46, preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; the intermediate package structure obtained by this step is as follows: Fig. 27 (f) as shown.

[0235] Operation S47, preparing a second conductive structure electrically connected to the chip with the functional surface facing the second direction on the permanent carrier, the adhesive material and the fine interconnection line layer; the intermediate package structure obtained by this step is as follows: Fig. 27 (g) as shown.

[0236] Operation S48, preparing a second rewiring layer on the permanent carrier, which is electrically connected to the first rewiring layer through the vertical interconnection conductive structure, and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure. Figure 4 The package structure shown.

[0237] Fig.29 and Fig.30 Schematically shows Figure 8 The specific details of each step in the method can be obtained by combining the implementation details of the corresponding steps of other embodiments described above, so the following only briefly describes the method steps involved and the effects of the corresponding intermediate structures obtained, and no detailed description of each step is repeated. Fig.29 and 30 As shown, the preparation method comprises:

[0238] Operation S81, preparing a fine interconnection line layer on one surface of the permanent carrier; the intermediate of the package structure obtained by this step is as follows Fig.29 (a) shown.

[0239] Operation S82, pre-prepare a supporting insulating material on the fine interconnect layer, so as to define a concave chip-attaching area by the supporting insulating material; the intermediate of the package structure obtained by this step is as follows: Fig.29 (b) as shown.

[0240] Operation S83, preparing a first vertical conductive structure penetrating the supporting insulating material, the fine interconnection line layer and the permanent carrier on the supporting insulating material; the intermediate of the packaging structure obtained by this step is as follows: Fig.29 (c) as shown.

[0241] Operation S84, performing chip stacking and chip bonding in the chip bonding area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and bonded together by bonding materials, and the chip of the stacked chips closest to the fine interconnection layer is bonded to the fine interconnection layer by bonding materials; the intermediate of the packaging structure obtained by this step is as follows Fig.29 (d) as shown.

[0242] Operation S85, using an encapsulation material to perform plastic encapsulation on the side of the permanent carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; the intermediate package structure obtained by this step is as follows: Fig.29 (e) as shown.

[0243] Operation S86, preparing a first conductive structure electrically connected to the chip with the functional surface facing the first direction on the encapsulation material layer; the intermediate of the package structure obtained by this step is as follows: Fig.29 (f) as shown.

[0244] Operation S87, preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure; the intermediate package structure obtained by this step is as follows: Fig.29 (g) as shown.

[0245] Operation S88, preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; the intermediate package structure obtained by this step is as follows: Fig.29 (h) shown.

[0246] Operation S89, preparing a second conductive structure electrically connected to the chip with the functional surface facing the second direction on the permanent carrier, the adhesive material and the fine interconnection line layer; the intermediate package structure obtained by this step is as follows: Fig.29 (i) as shown.

[0247] Operation S90, preparing a second redistribution layer on the permanent carrier, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure. Figure 8 The package structure shown.

[0248] The following describes a method for preparing a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention.

[0249] Fig.31 The method for preparing a back-to-back three-dimensional stacked fan-out packaging module according to an embodiment of the present invention is schematically shown. Fig.31 As shown, it includes:

[0250] Operation S301 is to prepare a packaging carrier, wherein the packaging carrier may be prepared by the method for preparing a back-to-back three-dimensional stacked fan-out packaging structure of any of the aforementioned embodiments, and the prepared packaging carrier includes at least two groups of stacked chips.

[0251] In operation S302, a package external pin pad electrically connected to at least a portion of the rewiring conductive structure of the corresponding rewiring layer is prepared on the first rewiring layer and / or the second rewiring layer of the package carrier.

[0252] Operation S303, flip-chip soldering the flip chip with flip-chip pin bumps prepared in advance on at least part of the package external pin pads, and preparing solder balls or external pins on other package external pin pads. The flip chip is flip-chip soldered on the package external pin pads of the first rewiring layer or the second rewiring layer by flip-chip reflow soldering or TCB process, and the density of the flip-chip pin bumps on the flip chip is C4bump or higher.

[0253] Fig.32 The method for preparing a back-to-back three-dimensional stacked fan-out packaging module according to another embodiment of the present invention is schematically shown. Fig.32 As shown, it includes:

[0254] Operation S311, preparing a packaging carrier, wherein the packaging carrier can be prepared by the preparation method of the back-to-back three-dimensional stacked fan-out packaging structure of any of the aforementioned embodiments, and the prepared packaging carrier includes at least two groups of stacked chips.

[0255] In operation S312, package external pin pads electrically connected to at least a portion of the rewiring conductive structures of the corresponding rewiring layers are prepared on the first rewiring layer and the second rewiring layer of the package carrier.

[0256] Operation S313 , flip-chip bonding a fine circuit transfer board electrically connected to the corresponding package external pin pads on the first re-wiring layer or the second re-wiring layer of the package carrier.

[0257] In operation S314, the flip chip with pre-prepared pin bumps is flip-chip soldered on a fine circuit transfer board, wherein the flip chip is electrically connected to the first or second redistribution layer through the fine circuit transfer board.

[0258] In operation S315 , solder balls or external pins are prepared on the package external pin pads of the redistribution layer of the fine circuit transfer board that is not provided.

[0259] In other possible implementations, an enhanced heat dissipation structure, a microchannel heat dissipation structure, a heat dissipation device, etc. may be provided on the flip chip to obtain other different embodiments.

[0260] It should be noted that the order of the operating steps described in the embodiments of the present invention is not necessary, but the specific operating order can be flexibly adjusted. In specific applications, the operating steps can be adjusted accordingly according to needs. For example, the order of preparing the second conductive structure and preparing the first redistribution layer can be swapped, etc. This does not affect the effect achieved by the preparation method of the present invention and the structural structure of the obtained product.

[0261] It can be understood that, in other implementations, the steps of the above-mentioned preparation method and the features of the packaging structure described in the embodiments of the present invention can also be freely combined in other ways according to needs to obtain different types of packaging structures, and the embodiments of the present invention are not regarded as limiting the combination of the preparation method steps and the packaging structure features.

[0262] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A back-to-back three-dimensional stacked fan-out packaging structure, characterized in that: include: At least one group of stacked chips, each group of stacked chips includes at least three layers of stacked chips, and the at least three layers of stacked chips include at least two chips with functional surfaces facing a first direction and at least one chip with a functional surface facing a second direction, wherein the first direction and the second direction are opposite directions; An encapsulation material layer encapsulating the laminated chip; A first redistribution layer located on one side of the encapsulation material layer and electrically connected to the chip with the functional surface facing the first direction; A second redistribution layer located on the other side of the encapsulation material layer and electrically connected to the chip with the functional surface facing the second direction; a vertical interconnect conductive structure for electrically connecting the first redistribution layer to the second redistribution layer; and A supporting insulating material defining a concave chip-mounting area, wherein the at least one group of stacked chips is mounted on the chip-mounting area, the supporting insulating material is encapsulated by the encapsulation material layer, and the height of the supporting insulating material is not less than the height of the stacked chips; Wherein, the vertical interconnection conductive structure includes a segment arranged in the encapsulation material layer and a segment arranged in the supporting insulating material, the vertical interconnection conductive structure segment arranged in the supporting insulating material is pre-prepared before forming the encapsulation material layer, and at least part of the vertical interconnection conductive structure segment arranged in the encapsulation material layer is vertically interconnected with the vertical interconnection conductive structure segment arranged in the supporting insulating material; the chip includes a chip pin pad, and at least part of the chip pin pads of at least part of the chips are provided with chip pin bumps; the first rewiring layer and the second rewiring layer both include a rewiring insulating material and a rewiring conductive structure; Among them, a first conductive structure is arranged at a position on the encapsulation material layer corresponding to the chip pin pads and chip pin bumps of the chip with the functional surface facing the first direction, and the chip pin pads and chip pin bumps of the chip with the functional surface facing the first direction are electrically connected to the rewiring conductive structure of the first rewiring layer through the first conductive structure arranged on the encapsulation material layer.

2. The packaging structure according to claim 1, characterized in that: It also includes a support structure located between the encapsulation material layer and the second rewiring layer, and the chip attaching area is defined on the support structure; wherein, The stacked chip is attached to the chip attaching area on the support structure by means of an adhesive material; The chip with the functional surface facing the second direction is electrically connected to the second redistribution layer through the second conductive structure penetrating the support structure and the adhesive material; The vertical interconnect conductive structure also includes a segment that penetrates the support structure and the adhesive material.

3. The packaging structure according to claim 1, characterized in that: It also includes a fine interconnection line layer located between the encapsulation material layer and the second rewiring layer and a second conductive structure penetrating the fine interconnection line layer and the adhesive material, wherein the chip attaching area is defined on the fine interconnection line layer, and the fine interconnection line layer includes a fine interconnection insulating material and a fine interconnection conductive structure; The stacked chip is attached to the chip attaching area on the fine interconnection line layer by means of an adhesive material; The chip with the functional surface facing the second direction is electrically connected to the second redistribution layer through a second conductive structure penetrating the fine interconnection line layer and the adhesive material; Wherein, the second redistribution layer is also electrically connected to the fine interconnection line layer through the second conductive structure; The vertical interconnect conductive structure also includes a fine interconnect insulating material and a segment of the adhesive material that penetrates the fine interconnect line layer.

4. The packaging structure according to claim 3, characterized in that: The chip with the functional surface facing the second direction in the stacked chip is bonded so that the chip pin pads and chip pin bumps are in one-to-one correspondence with the fine interconnection conductive structure of the fine interconnection line layer, and the second conductive structure penetrates each fine interconnection conductive structure of the fine interconnection line layer and the adhesive material at the corresponding position, so that the chip with the functional surface facing the second direction and the second redistribution layer, as well as the second redistribution layer and the fine interconnection line layer are electrically connected through the second conductive structure; or The chip with the functional surface facing the second direction in the stacked chip is bonded so that each chip pin pad and chip pin bump is respectively arranged corresponding to two mutually spaced fine interconnection conductive structures, and the second conductive structure penetrates the fine interconnection insulating material between two mutually spaced fine interconnection conductive structures corresponding to the same chip pin pad or chip pin bump of the fine interconnection line layer and the adhesive material at the corresponding position, so that the chip with the functional surface facing the second direction and the second rewiring layer, as well as the second rewiring layer and the fine interconnection line layer are electrically connected through the second conductive structure; or The chip with the functional surface facing the second direction in the stacked chip is bonded so that each chip pin pad and chip pin bump are respectively arranged corresponding to a fine interconnect conductive structure of an annular structure, and the second conductive structure penetrates the fine interconnect insulating material in the middle of the annular structure of the fine interconnect conductive structure of the annular structure corresponding to the same chip pin pad or chip pin bump of the fine interconnect line layer and the adhesive material at the corresponding position, so that the chip with the functional surface facing the second direction and the second rewiring layer, as well as the second rewiring layer and the fine interconnect line layer are electrically connected through the second conductive structure.

5. The packaging structure according to claim 3, characterized in that: Also included is a support structure located between the fine interconnect line layer and the second rewiring layer, the fine interconnect line layer being disposed on the support structure; Both the vertical interconnect conductive structure and the second conductive structure also penetrate the support structure.

6. The packaging structure according to any one of claims 1 to 5, characterized in that: The vertical interconnection conductive structure includes an outer ring line used as a ground line or a signal shielding line and a vertical conductive line located in the outer ring line used as a conductive line.

7. A back-to-back three-dimensional stacked fan-out packaging module, characterized in that: include: A packaging carrier, wherein the packaging carrier is the back-to-back three-dimensional stacked fan-out packaging structure according to any one of claims 1 to 6, and the packaging structure includes at least two groups of stacked chips; A flip chip, wherein the flip chip is disposed on at least a portion of the rewiring conductive structure of the first rewiring layer or the second rewiring layer of the package carrier and is electrically connected to the corresponding rewiring conductive structure; and A solder ball or an external pin is disposed on the first redistribution layer or the second redistribution layer and is electrically interconnected with at least a portion of the redistribution conductive structure.

8. The packaging module according to claim 7, characterized in that: Also includes a heat dissipation enhancement structure arranged around the flip chip; and / or A microchannel heat dissipation structure provided on a flip chip; and / or A heat sink is provided on a redistribution layer where no flip chip is provided.

9. The packaging module according to claim 8, characterized in that: The stacked chip is a memory chip, and the flip chip is a CPU or a GPU.

10. A back-to-back three-dimensional stacked fan-out packaging module, characterized in that: include: A packaging carrier, wherein the packaging carrier is the back-to-back three-dimensional stacked fan-out packaging structure according to any one of claims 1 to 6, and the packaging structure includes at least two groups of stacked chips; A fine circuit adapter board disposed on the first rewiring layer or the second rewiring layer of the package carrier, the fine circuit adapter board being electrically connected to the corresponding rewiring layer; A flip chip, the flip chip is disposed on the fine circuit adapter and is electrically connected to the fine circuit adapter; and Solder balls or external pins are disposed on the redistribution layer of the fine circuit transfer board and are electrically interconnected with at least a portion of the redistribution conductive structure.

11. The packaging module according to claim 10, characterized in that: A heat dissipation enhancement structure is also arranged around the flip chip.

12. The packaging module according to claim 11, characterized in that: The stacked chip is a memory chip, and the flip chip is a CPU or a GPU.

13. A method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, characterized in that: The method comprises: Preparing a supporting insulating material and a first vertical conductive structure penetrating the supporting insulating material on one surface of the temporary carrier, wherein the supporting insulating material defines a concave chip attaching area; Perform chip stacking and pasting in the chip pasting area of ​​the temporary carrier to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are stacked and pasted together by pasting materials; Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; Preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with a functional surface facing a first direction and a second vertical conductive structure vertically interconnected with the first vertical conductive structure, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure; Removing the temporary carrier, wherein after the temporary carrier is removed, the surface of the chip covered by the temporary carrier is exposed on the surface of the encapsulation material layer; A first rewiring layer electrically connected to the chip facing in a first direction and a second rewiring layer electrically connected to the chip facing in a second direction are respectively prepared on two surfaces of the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing in the first direction through the first conductive structure, the second rewiring layer is directly electrically interconnected with the chip facing in the second direction, and the first rewiring layer and the second rewiring layer are electrically connected through the vertical interconnect conductive structure.

14. A method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, characterized in that: The method comprises: Preparing a supporting insulating material and a first vertical conductive structure penetrating the supporting insulating material and the supporting structure on one surface of the supporting structure, wherein the supporting insulating material defines a concave chip attaching area; Perform chip stacking and pasting in the chip pasting area of ​​the support structure to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, and different chips are pasted together by stacking and pasting materials; Using an encapsulation material to perform plastic encapsulation on the side of the support structure on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; Preparing a first conductive structure on the encapsulation material layer that is electrically connected to the chip with its functional surface facing the first direction; Preparing a second vertical conductive structure vertically interconnected with the first vertical conductive structure on the encapsulation material layer, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure; Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; Preparing a second conductive structure on the support structure that is electrically connected to the chip with the functional surface facing the second direction; A second redistribution layer is prepared on the support structure, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the chip with the functional surface facing the second direction through the second conductive structure.

15. A method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, characterized in that: The method comprises: preparing a fine interconnection line layer on one surface of the temporary carrier; Preparing a supporting insulating material and a first vertical conductive structure penetrating the supporting insulating material and the fine interconnection layer on the fine interconnection layer, wherein the supporting insulating material defines a concave chip attaching area; Perform chip stacking and pasting in the chip pasting area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection layer is pasted on the fine interconnection layer by adhesive materials; Using an encapsulation material to perform plastic encapsulation on the side of the temporary carrier board on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; Preparing a conductive structure on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with a functional surface facing a first direction, and a second vertical conductive structure vertically interconnected with the first vertical conductive structure, wherein the first vertical conductive structure and the second vertical interconnected conductive structure together form a vertical interconnected conductive structure; Removing the temporary carrier, wherein after the temporary carrier is removed, the fine interconnection line layer covered by the temporary carrier is exposed on the surface of the encapsulation material layer; Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; Preparing a second conductive structure on the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction; A second redistribution layer is prepared on the fine interconnection layer, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection layer and the chip with the functional surface facing the second direction through the second conductive structure.

16. A method for preparing a back-to-back three-dimensional stacked fan-out packaging structure, characterized in that: The method comprises: forming a fine interconnection line layer on one of the surfaces of the support structure; Preparing a supporting insulating material and a first vertical conductive structure penetrating the supporting structure, the supporting insulating material and the fine interconnection layer on the fine interconnection layer, wherein the supporting insulating material defines a concave chip attaching area; Perform chip stacking and pasting in the chip pasting area of ​​the fine interconnection layer to form at least one group of stacked chips, wherein each group of stacked chips includes at least one chip with a functional surface facing a first direction and at least one chip with a functional surface facing a second direction, the first direction and the second direction are opposite directions, different chips are stacked and pasted together by pasting materials, and the chip of the stacked chips closest to the fine interconnection layer is pasted on the fine interconnection layer by adhesive materials; Using an encapsulation material to perform plastic encapsulation on the side of the support structure on which the stacked chip is mounted, to form an encapsulation material layer encapsulating the stacked chip; A conductive structure is prepared on the encapsulation material layer, wherein the conductive structure includes a first conductive structure electrically connected to the chip with a functional surface facing a first direction, and A second vertical conductive structure vertically interconnected with the first vertical conductive structure, the first vertical conductive structure and the second vertical interconnected conductive structure together forming a vertical interconnected conductive structure; Preparing a first rewiring layer electrically connected to the chip facing the first direction on the encapsulation material layer, wherein the first rewiring layer is electrically connected to the chip facing the first direction through the first conductive structure; Preparing a second conductive structure on the support structure, the adhesive material and the fine interconnection line layer, which is electrically connected to the chip with the functional surface facing the second direction; A second redistribution layer is prepared on the support structure, which is electrically connected to the first redistribution layer through the vertical interconnection conductive structure and is electrically connected to the fine interconnection line layer and the chip with the functional surface facing the second direction through the second conductive structure.

17. A method for preparing a back-to-back three-dimensional stacked fan-out packaging module, characterized in that: include: A back-to-back three-dimensional stacked fan-out packaging structure is prepared as a packaging carrier by the method described in any one of claims 13 to 16, wherein the prepared packaging carrier includes at least two groups of stacked chips; Preparing package external pin pads on the first rewiring layer and / or the second rewiring layer of the package carrier board, which are electrically connected to at least part of the rewiring conductive structures of the corresponding rewiring layer; The flip chip with pin bumps prepared in advance is flip-chip soldered on at least part of the package external pin pads, and solder balls or external pins are prepared on other package external pin pads.

18. A method for preparing a back-to-back three-dimensional stacked fan-out packaging module, characterized in that: include: A back-to-back three-dimensional stacked fan-out packaging structure is prepared as a packaging carrier by the method described in any one of claims 13 to 16, wherein the prepared packaging carrier includes at least two groups of stacked chips; Preparing package external pin pads on the first and second rewiring layers of the package carrier board, which are electrically connected to at least a portion of the rewiring conductive structures of the corresponding rewiring layers; A fine circuit transfer board electrically connected to the corresponding package external pin pad is flip-chip soldered on the package external pin pad of the first rewiring layer or the second rewiring layer of the package carrier board, Flip-chip soldering a flip chip with pre-prepared pin bumps on a fine circuit adapter, wherein the flip chip is electrically connected to the first or second redistribution layer through the fine circuit adapter; Solder balls or external pins are prepared on the external pin pads of the package where the redistribution layer of the fine circuit adapter is not provided.

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