Single-chip integrated full bridge and method of manufacturing the same

Abstract

Single-chip integrated full bridge and preparation method thereof, relate to the technical field of semiconductor. In the case, the area of the chip is effectively utilized, and only one chip needs to be packaged using the full-bridge rectifier chip in the case. The packaging process steps and cost are reduced, the use amount of chips can be reduced by three quarters using the full-bridge rectifier chip in the case, and the power density is 4 times that of the traditional full-bridge device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a single-chip integrated full-bridge and its fabrication method. Background Technology

[0002] In the field of power electronic device technology, AC to DC conversion has always been an important application area. Currently, rectification methods include diode rectification, half-bridge rectification, and full-bridge rectification.

[0003] Full-bridge rectification, as a commonly used rectification method, is often applied in fields such as power transmission and industrial control. Traditional full-bridge rectifiers package four diode chips into one device, which involves a complex packaging process and a large package body, resulting in a decrease in device power density and an increase in cost. As the requirements for power density and cost-effectiveness of power semiconductors become increasingly stringent, improving the power density of full-bridge rectifiers is attracting more and more attention. Summary of the Invention

[0004] To address the above problems, this invention provides a single-chip integrated full-bridge and its fabrication method that effectively improves the power density of the rectifier full-bridge.

[0005] The technical solution of this invention is:

[0006] A single-chip integrated full-bridge and its fabrication method include the following steps:

[0007] Step S100: Prepare a first lightly doped N-region and a second lightly doped N-region on the epitaxial wafer;

[0008] A first heavily doped N-region and a first heavily doped P-region are prepared inside the first lightly doped N-region;

[0009] A second heavily doped N-region and a second heavily doped P-region are prepared inside the second lightly doped N-region;

[0010] Step S200: A first isolation layer is prepared on the epitaxial wafer, and windows are opened at the first heavily doped N region, the first heavily doped P region, the second heavily doped N region, and the second heavily doped P region, respectively.

[0011] Step S300: Prepare the corresponding first cathode, first anode, second cathode, and second anode at the first heavily doped N region, the first heavily doped P region, the second heavily doped N region, and the second heavily doped P region;

[0012] Step S400: Prepare a third lightly doped N region and a fourth lightly doped N region on the epitaxial wafer;

[0013] A third heavily doped N-region and a third heavily doped P-region are prepared inside the third lightly doped N-region;

[0014] A fourth heavily doped N-region and a fourth heavily doped P-region are prepared inside the fourth lightly doped N-region;

[0015] Step S500: A second isolation layer is prepared on the epitaxial wafer, and windows are opened at the third doped N region, the third doped P region, the fourth doped N region, and the fourth doped P region.

[0016] In step S600, the corresponding third cathode, third anode, fourth cathode, and fourth anode are fabricated in the third doped N region, the third doped P region, the fourth doped N region, and the fourth doped P region, respectively, and the entire device is fabricated.

[0017] Specifically, step S100 includes:

[0018] Step S110: Using photolithography, a mask is used to protect the outer regions of the first lightly doped N region and the second lightly doped N region. The first lightly doped N region and the second lightly doped N region are formed by diffusion or ion implantation.

[0019] Step S120: Using photolithography, a mask is used to protect the outer regions of the first and second heavily doped N regions. The first and second heavily doped N regions are formed by diffusion or ion implantation.

[0020] In step S130, the external regions of the first heavily doped P-region and the second heavily doped P-region are protected by a mask using photolithography, and the first heavily doped P-region and the second heavily doped P-region are formed by diffusion or ion implantation.

[0021] Specifically, step S200 includes:

[0022] Step S210: Prepare the first isolation layer by chemical vapor deposition;

[0023] In step S220, a photolithography process is used to protect the outer regions of the first heavily doped N-region, the first heavily doped P-region, the second heavily doped N-region, and the second heavily doped P-region using a mask, and an etching process is used to create windows in the first heavily doped N-region, the first heavily doped P-region, the second heavily doped N-region, and the second heavily doped P-region.

[0024] Specifically, step S400 includes:

[0025] Step S410: Using photolithography, a mask is used to protect the external regions of the third and fourth lightly doped N regions. The third and fourth lightly doped N regions are formed by diffusion or ion implantation.

[0026] Step S420: Using photolithography, the third and fourth doped N regions and the external region are protected by a mask. The third and fourth doped N regions are formed by diffusion or ion implantation.

[0027] In step S430, the external regions of the third and fourth doped P-regions are protected by a photolithography mask, and the third and fourth doped P-regions are formed by diffusion or ion implantation.

[0028] Specifically, step S500 includes:

[0029] Step S510: Prepare the second isolation layer by chemical vapor deposition;

[0030] In step S520, the external regions of the third doped N region, the third doped P region, the fourth doped N region, and the fourth doped P region are protected by a photolithography process using a mask, and windows are opened at the third doped N region, the third doped P region, the fourth doped N region, and the fourth doped P region using an etching process.

[0031] A single-chip integrated full-bridge includes a second isolation layer, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top.

[0032] The epitaxial wafer includes:

[0033] A first lightly doped N-region extends downward from the top surface of the second intrinsic silicon region of the epitaxial wafer; the top surface of the first lightly doped N-region is provided with a first heavily doped N-region and a first heavily doped P-region extending downward at intervals.

[0034] The second lightly doped N-region extends downward from the top surface of the second intrinsic silicon region of the epitaxial wafer; the top surface of the second lightly doped N-region is provided with a second heavily doped N-region and a second heavily doped P-region extending downward at intervals.

[0035] The third lightly doped N region extends upward from the bottom surface of the first intrinsic silicon region of the epitaxial wafer; the bottom surface of the third lightly doped N region is provided with a third heavily doped N region and a third heavily doped P region extending upward at intervals.

[0036] The fourth lightly doped N region extends upward from the bottom surface of the first intrinsic silicon region of the epitaxial wafer; the bottom surface of the fourth lightly doped N region is provided with a fourth heavily doped N region and a fourth heavily doped P region extending upward at intervals.

[0037] The top surface of the first isolation layer is provided with a downward extending:

[0038] The first cathode is connected to the first heavily doped N-region;

[0039] The first anode is connected to the first heavily doped P-region;

[0040] The second cathode is connected to the second heavily doped N-region;

[0041] The second anode is connected to the second heavily doped P-region;

[0042] The bottom surface of the second isolation layer has an upwardly extending:

[0043] The third cathode is connected to the third heavily doped N-region;

[0044] The third anode is connected to the third heavily doped P-region;

[0045] The fourth cathode is connected to the fourth heavily doped N-region;

[0046] The fourth anode is connected to the fourth heavily doped P-region.

[0047] Specifically, the epitaxial wafer is an SOI epitaxial wafer, which, from bottom to top, includes a first intrinsic silicon region, an oxide isolation layer, and a second intrinsic silicon region.

[0048] Specifically, the thickness of the first intrinsic silicon region is 50-1000um.

[0049] Specifically, the thickness of the second intrinsic silicon region is 50-1000um.

[0050] Specifically, the thickness of the oxide isolation layer is 1-10 μm.

[0051] Beneficial effects of this invention:

[0052] Traditional full-bridge rectifiers require packaging four diode chips, resulting in a complex packaging process, large package size, reduced power density, and increased cost. In this design, the full-bridge rectifier chip integrates four laterally conductive diodes onto a single chip. The first anode and second cathode form a metal interconnect connected to one end of the AC power supply. The third cathode and fourth anode form a metal interconnect connected to the other end of the AC power supply. The third anode and second anode form an electrical interconnect connected to one end of the load via the package or PCB board. The first cathode and fourth cathode form an electrical interconnect connected to one end of the load via the package or PCB board. A positive voltage is applied to the first anode and second cathode side, and current flows through the first anode, the first heavily doped P-region, the first lightly doped N-region, the first heavily doped N-region, and the first cathode to the load. The current flows through the load into the third anode, the third heavily doped P-region, the third lightly doped N-region, the third heavily doped N-region, the third cathode, and finally into the other end of the AC power supply. When a positive voltage is applied to the third cathode and the fourth anode, the current flows through the fourth anode, the fourth heavily doped P-region, the fourth lightly doped N-region, the fourth heavily doped N-region, the fourth cathode to the load, and then through the load into the second anode, the second heavily doped P-region, the second lightly doped N-region, the second heavily doped N-region, the second cathode, and finally into the other end of the AC power supply. In this case, the full-bridge rectifier chip effectively utilizes the chip area. Using the full-bridge rectifier chip in this case only requires packaging one chip, reducing packaging process steps and costs. Using the full-bridge rectifier chip in this case can reduce the number of chips used by three-quarters, and the power density is four times that of traditional full-bridge devices. Attached Figure Description

[0053] Figure 1 This is a process flow diagram of the present invention;

[0054] Figure 2 This is a schematic diagram of the cross-sectional structure of an SOI epitaxial wafer;

[0055] Figure 3 This is a schematic diagram of the cross-sectional structure of the device in step S100;

[0056] Figure 4 This is a schematic diagram of the cross-sectional structure of the device in step S200;

[0057] Figure 5 This is a schematic diagram of the cross-sectional structure of the device in step S300;

[0058] Figure 6 This is a schematic diagram of the cross-sectional structure of the device in step S400;

[0059] Figure 7 This is a schematic diagram of the cross-sectional structure of the device in step S500;

[0060] Figure 8 This is a schematic diagram of the cross-sectional structure of the device in step S600;

[0061] In the figure, 1 is the SOI epitaxial wafer, 2 is the first lightly doped N-region, 3 is the second lightly doped N-region, 4 is the first heavily doped N-region, 5 is the second heavily doped N-region, 6 is the first heavily doped P-region, 7 is the second heavily doped P-region, 8 is the first isolation layer, 9 is the first cathode, 10 is the second cathode, 11 is the first anode, 12 is the second anode, 13 is the third lightly doped N-region, 14 is the fourth lightly doped N-region, 15 is the third heavily doped N-region, 16 is the fourth heavily doped N-region, 17 is the third heavily doped P-region, 18 is the fourth heavily doped P-region, 19 is the second isolation layer, 20 is the third cathode, 21 is the fourth cathode, 22 is the third anode, 23 is the fourth anode, 24 is the first intrinsic silicon region, 25 is the oxide isolation layer, and 26 is the second intrinsic silicon region. Detailed Implementation

[0062] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0063] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0064] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0065] The present invention will now be described with reference to Figures 1-8;

[0066] A single-chip integrated full-bridge and its fabrication method include the following steps:

[0067] Step S100, in such Figure 2 A first lightly doped N-region 2 and a second lightly doped N-region 3 are fabricated on the epitaxial wafer 1 shown.

[0068] A first heavily doped N-region 4 and a first heavily doped P-region 6 are prepared inside the first lightly doped N-region 2;

[0069] A second heavily doped N-region 5 and a second heavily doped P-region 7 are prepared inside the second lightly doped N-region 3; for example... Figure 3 As shown;

[0070] Step S110: Using photolithography, a mask is used to protect the external regions of the first lightly doped N region 2 and the second lightly doped N region 3. The first lightly doped N region 2 and the second lightly doped N region 3 are formed by diffusion or ion implantation.

[0071] Step S120: Using photolithography, a mask is used to protect the external regions of the first heavily doped N-region 4 and the second heavily doped N-region 5. The first heavily doped N-region 4 and the second heavily doped N-region 5 are formed by diffusion or ion implantation.

[0072] In step S130, the external regions of the first heavily doped P-region 6 and the second heavily doped P-region 7 are protected by a photolithography process using a mask, and the first heavily doped P-region 6 and the second heavily doped P-region 7 are formed by diffusion or ion implantation processes.

[0073] Accordingly, the epitaxial wafer is an SOI epitaxial wafer. From bottom to top, epitaxial wafer 1 consists of a first intrinsic silicon region 24, an oxide isolation layer 25, and a second intrinsic silicon region 26. The epitaxial wafer thickness is 101-2010 μm. The thickness of the first intrinsic silicon region 24 is 50-1000 μm, the thickness of the second intrinsic silicon region 26 is 50-1000 μm, the thickness of the oxide isolation layer 25 is 1-10 μm, the junction depth of the first lightly doped N-region 2 is 50-1000 μm, and the junction depth of the first heavily doped N-region 4 and the first heavily doped P-region 6 are located inside the first lightly doped N-region 2. Their upper surfaces are level with the upper surface of epitaxial wafer 1, and their lower surfaces are higher than the lower surface of the first lightly doped N-region 2. The junction depth is set to 1-100 μm, and the width is set to 1-100 μm. In the first lightly doped N-region 4 and the first lightly doped P-region 6, the two regions are not connected, and the distance between them is set to 10-500 μm. The junction depth of the second lightly doped N-region 3 is 50-1000 μm. The second heavily doped N-region 5 and the second heavily doped P-region 7 are located inside the second lightly doped N-region 3. Their upper surfaces are level with the upper surface of the epitaxial wafer 1, and their lower surfaces are higher than the lower surface of the second lightly doped N-region 3. The junction depth and width are set to 1-100 μm. The second heavily doped N-region 5 and the second lightly doped P-region 7 are not connected, and the distance between them is set to 10-500 μm. The first lightly doped N-region 2 and the second lightly doped N-region 3 are not connected, and the distance between them is set to 10-100 μm. The doping concentration of all lightly doped regions is 1e. 13 .cm -3 to 1e 17 .cm -3 The doping concentration in the heavily doped region is 1e 19 .cm -3 to 1e 21 .cm -3 The N-type doping element is phosphorus or arsenic, and the P-type doping element is boron. The relevant parameter settings are related to the electrical design of the device.

[0074] In this embodiment, the epitaxial wafer 1 has a thickness of 405 μm, the first intrinsic silicon region 24 has a thickness of 200 μm, the second intrinsic silicon region 26 has a thickness of 200 μm, the oxide isolation layer 25 has a thickness of 5 μm, the junction depth of the first lightly doped N-region 2 and the second lightly doped N-region 3 is 200 μm, the distance between them is 30 μm, the doping element is phosphorus, and the doping concentration is 1e. 14. cm -3 The width of the first-doped N-region 4, the second-doped N-region 5, the first-doped P-region 6, and the second-doped P-region 7 is 30 μm, and the junction depth is 30 μm. The doping element of the first-doped N-region 4 and the second-doped N-region 5 is phosphorus, and the doping concentration is 2e. 19 .cm -3 The first doped P-region 6 and the second doped P-region 7 are doped with boron, and the doping concentration is 2e⁻. 19 .cm -3The first heavily doped N region 4 and the first heavily doped P region 6 are not connected, and the distance between them is 70 μm. The second heavily doped N region 5 and the second heavily doped P region 7 are not connected, and the distance between them is 70 μm. The first lightly doped N region 2, the second lightly doped N region 3, the first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5, and the second heavily doped P region 7 are prepared using a diffusion process.

[0075] Step S200: A first isolation layer 8 is prepared on the epitaxial wafer 1, and windows are opened at the first heavily doped N-region 4, the first heavily doped P-region 6, the second heavily doped N-region 5, and the second heavily doped P-region 7, respectively; Figure 4 As shown;

[0076] Step S210: Prepare the first isolation layer 8 by chemical vapor deposition;

[0077] In step S220, the external regions of the first heavily doped N-region 4, the first heavily doped P-region 6, the second heavily doped N-region 5, and the second heavily doped P-region 7 are protected by a photolithography process using a mask, and windows are opened at the first heavily doped N-region 4, the first heavily doped P-region 6, the second heavily doped N-region 5, and the second heavily doped P-region 7 by an etching process.

[0078] Correspondingly, the first isolation layer 8 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It is windowed using ICP dry etching, and the relevant parameter settings are related to the electrical design of the device.

[0079] In this embodiment, Si3N4 is used as the first isolation layer 8 with a thickness of 200nm. CF4 is used for ICP dry etching at a rate of 10nm / min to ensure etching accuracy. The etching time is set to 21min to ensure successful windowing.

[0080] Step S300: First cathode 9, first anode 11, second cathode 10, and second anode 12 are fabricated at the first heavily doped N-region 4, first heavily doped P-region 6, second heavily doped N-region 5, and second heavily doped P-region 7 using a stripping or etching process; Figure 5 As shown;

[0081] Accordingly, the first cathode 9, the first anode 11, the second cathode 10, the second anode 12 and the lower first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5 and the second heavily doped P region 7 are in contact to form a good ohmic contact, and their upper surfaces are horizontal with the upper surface of the first isolation layer 8. The first anode 11 and the second cathode 10 form a metal interconnect.

[0082] In this embodiment, a first cathode 9, a first anode 11, a second cathode 10, and a second anode 12 are prepared using a metal stripping process. Four layers of metal, Al / Ti / Ni / Ag, are used as ohmic contact metals, and the first anode 11 and the second cathode 10 form a metal interconnect.

[0083] Step S400: Prepare a third lightly doped N region 13 and a fourth lightly doped N region 14 on the epitaxial wafer 1;

[0084] A third heavily doped N-region 15 and a third heavily doped P-region 17 are prepared inside the third lightly doped N-region 13;

[0085] A fourth heavily doped N-region 16 and a fourth heavily doped P-region 18 are prepared inside the fourth lightly doped N-region 14; as follows: Figure 6 As shown;

[0086] Step S410: Using photolithography, a mask is used to protect the external regions of the third lightly doped N region 13 and the fourth lightly doped N region 14. The third lightly doped N region 13 and the fourth lightly doped N region 14 are formed by diffusion or ion implantation.

[0087] Step S420: Using photolithography, a mask is used to protect the third doped N region 15 and the fourth doped N region 16, as well as the external region. The third doped N region 15 and the fourth doped N region 16 are formed by diffusion or ion implantation.

[0088] In step S430, the external regions of the third doped P-region 17 and the fourth doped P-region 18 are protected by a photolithography process using a mask, and the third doped P-region 17 and the fourth doped P-region 18 are formed by diffusion or ion implantation processes.

[0089] Accordingly, the junction depth of the third lightly doped N-region 13 is 50-1000 μm. The third heavily doped N-region 15 and the third heavily doped P-region 17 are located inside the third lightly doped N-region 13, with their lower surfaces level with the lower surface of the epitaxial wafer 1, and their upper surfaces lower than the upper surface of the third lightly doped N-region 13. The junction depth and width are set to 1-100 μm. The third heavily doped N-region 15 and the third heavily doped P-region 17 are not connected, and the distance between them is set to 10-500 μm. The junction depth of the fourth lightly doped N-region 14 is 50-1000 μm. The N-doped region 16 and the fourth heavily doped P-region 18 are located inside the fourth lightly doped N-region 14. Their lower surfaces are level with the lower surface of the epitaxial wafer 1, and their upper surfaces are lower than the upper surface of the fourth lightly doped N-region 14. The junction depth is set to 1-100 μm, and the width is set to 1-100 μm. The fourth heavily doped N-region 16 and the fourth heavily doped P-region 18 are not connected, and the distance between them is set to 10-500 μm. The third lightly doped N-region 13 and the fourth lightly doped N-region 14 are not connected, and the distance between them is set to 10-100 μm. The relevant parameter settings are related to the electrical design of the device.

[0090] In this embodiment, the junction depth of the third lightly doped N-region 13 and the fourth lightly doped N-region 14 is 200 μm, the distance between them is 30 μm, the doping element is phosphorus, and the doping concentration is 1e. 14. cm -3 The width of the third-doped N-region 15, the fourth-doped N-region 16, the third-doped P-region 17, and the fourth-doped P-region 18 is 30 μm, and the junction depth is 30 μm. The doping element of the third-doped N-region 15 and the fourth-doped N-region 16 is phosphorus, and the doping concentration is 2e. 19 .cm -3 The third-fold doped P-region 17 and the fourth-fold doped P-region 18 are doped with boron, and the doping concentration is 2e⁻. 19 .cm -3 The third heavily doped N region 15 and the third heavily doped P region 17 are not connected, and the distance between them is 70 μm. The fourth heavily doped N region 16 and the fourth heavily doped P region 18 are not connected, and the distance between them is 70 μm. The third lightly doped N region 13, the fourth lightly doped N region 14, the third heavily doped N region 15, the fourth heavily doped N region 16, the third heavily doped P region 17, and the fourth heavily doped P region 18 are prepared using a diffusion process.

[0091] Step S500: A second isolation layer 19 is prepared on the epitaxial wafer 1, and windows are opened at the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18; as shown Figure 7 As shown;

[0092] Step S510: Prepare the second isolation layer 19 by chemical vapor deposition;

[0093] In step S520, the external regions of the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18 are protected by a photolithography process using a mask, and windows are opened at the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18 by an etching process.

[0094] Correspondingly, the second isolation layer 19 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It is windowed using ICP dry etching, and the relevant parameter settings are related to the electrical design of the device.

[0095] In this embodiment, Si3N4 is used as the second isolation layer 19 with a thickness of 200nm. CF4 is used for ICP dry etching at a rate of 10nm / min to ensure etching accuracy. The etching time is set to 21min to ensure successful windowing.

[0096] In step S600, the corresponding third cathode 20, third anode 22, fourth cathode 21, and fourth anode 23 are fabricated in the third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16, and the fourth heavily doped P region 18 by a stripping or etching process, as follows: Figure 8 As shown, the entire device has been fabricated.

[0097] Accordingly, the third cathode 20, the third anode 22, the fourth cathode 21, the fourth anode 23 and the lower third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 are in contact to form a good ohmic contact, and their lower surfaces are horizontal to the lower surface of the second isolation layer 19. The third cathode 20 and the fourth anode 23 form a metal interconnect.

[0098] In this embodiment, the third cathode 20, the third anode 22, the fourth cathode 21, and the fourth anode 23 are fabricated using a metal stripping process. Four layers of metal, Al / Ti / Ni / Ag, are used as ohmic contact metals. The third cathode 20 and the fourth anode 23 form a metal interconnect, and the entire device is fabricated.

[0099] A single-chip integrated full-bridge includes a second isolation layer 19, an epitaxial wafer 1, and a first isolation layer 8 arranged sequentially from bottom to top;

[0100] The epitaxial wafer 1 includes:

[0101] The first lightly doped N region 2 extends downward from the top surface of the second intrinsic silicon region 26 of the epitaxial wafer 1, and its lower surface is not lower than the upper surface of the oxide isolation layer 25; the top surface of the first lightly doped N region 2 is provided with a first heavily doped N region 4 and a first heavily doped P region 6 extending downward at intervals; the lower surfaces of the first heavily doped N region 4 and the first heavily doped P region 6 are both higher than the lower surface of the first lightly doped N region 2.

[0102] The second lightly doped N-region 3 extends downward from the top surface of the second intrinsic silicon region 26 of the epitaxial wafer 1, and its lower surface is not lower than the upper surface of the oxide isolation layer 25; the second lightly doped N-region 3 is spaced apart from the first lightly doped N-region 2; the top surface of the second lightly doped N-region 3 is provided with a second heavily doped N-region 5 and a second heavily doped P-region 7 extending downward at intervals; the lower surfaces of the second heavily doped N-region 5 and the second heavily doped P-region 7 are both higher than the lower surface of the second lightly doped N-region 3;

[0103] That is, the first cathode 9, the first anode 11, the second cathode 10, the second anode 12 and the lower first heavily doped N region 4, the first heavily doped P region 6, the second heavily doped N region 5 and the second heavily doped P region 7 are in contact to form a good ohmic contact, and their upper surfaces are horizontal with the upper surface of the first isolation layer 8, and the first anode 11 and the second cathode 10 form a metal interconnect.

[0104] The third lightly doped N-region 13 extends upward from the bottom surface of the first intrinsic silicon region 24 of the epitaxial wafer 1, and its upper surface is not higher than the lower surface of the oxide isolation layer 25; the bottom surface of the third lightly doped N-region 13 is provided with a third heavily doped N-region 15 and a third heavily doped P-region 17 extending upward at intervals; the upper surfaces of the third heavily doped N-region 15 and the third heavily doped P-region 17 are both lower than the upper surface of the third lightly doped N-region 13.

[0105] The fourth lightly doped N-region 14 extends upward from the bottom surface of the first intrinsic silicon region 24 of the epitaxial wafer 1, and its upper surface is not higher than the lower surface of the oxide isolation layer 25; the bottom surface of the fourth lightly doped N-region 14 is provided with a fourth heavily doped N-region 16 and a fourth heavily doped P-region 18 extending upward at intervals; the upper surfaces of the fourth heavily doped N-region 16 and the fourth heavily doped P-region 18 are both lower than the upper surface of the third lightly doped N-region 13;

[0106] The first lightly doped N-region 2 and the third lightly doped N-region 13 are spaced apart; the second lightly doped N-region 3 and the fourth lightly doped N-region 14 are spaced apart.

[0107] The top surface of the first isolation layer 8 is provided with a downwardly extending:

[0108] The first cathode 9 is connected to the first heavily doped N-region 4;

[0109] The first anode 11 is connected to the first heavily doped P-region 6;

[0110] The second cathode 10 is connected to the second heavily doped N-region 5;

[0111] The second anode 12 is connected to the second heavily doped P-region 7;

[0112] The bottom surface of the second isolation layer 19 is provided with an upwardly extending:

[0113] The third cathode 20 is connected to the third heavily doped N region 15;

[0114] The third anode 22 is connected to the third heavily doped P-region 17;

[0115] The fourth cathode 21 is connected to the fourth heavily doped N-region 16;

[0116] The fourth anode 23 is connected to the fourth heavily doped P-region 18.

[0117] That is, the third cathode 20, the third anode 22, the fourth cathode 21, the fourth anode 23 and the upper third heavily doped N region 15, the third heavily doped P region 17, the fourth heavily doped N region 16 and the fourth heavily doped P region 18 are in contact to form a good ohmic contact, and their lower surfaces are horizontal with the lower surface of the second isolation layer 19. The third cathode 20 and the fourth anode 23 form a metal interconnect.

[0118] The doping concentration of the lightly doped region in this case is 1e. 13 .cm -3 to 1e 17 .cm -3 The doping concentration in the heavily doped region is 1e 19 .cm -3 to 1e 21 .cm -3 The element doped with N-type is phosphorus or arsenic, and the element doped with P-type is boron.

[0119] Further specifying, the epitaxial wafer 1 is an SOI epitaxial wafer, which includes, from bottom to top, a first intrinsic silicon region 24, an oxide isolation layer 25, and a second intrinsic silicon region 26.

[0120] Further specified, the thickness of the first intrinsic silicon region 24 is 50-1000um.

[0121] Further specifying, the thickness of the second intrinsic silicon region 26 is 50-1000um.

[0122] Further specified, the oxide isolation layer 25 has a thickness of 1-10 μm.

[0123] The present invention has the following advantages:

[0124] Traditional full-bridge rectifiers require packaging four diode chips, resulting in a complex packaging process, large package size, reduced power density, and increased cost. In this design, the full-bridge rectifier chip integrates four laterally conductive diodes onto a single chip. The first anode 11 and the second cathode 10 form a metal interconnect connected to one end of the AC power supply. The third cathode 20 and the fourth anode 23 form a metal interconnect connected to the other end of the AC power supply. The third anode 22 and the second anode 12 form an electrical interconnect connected to one end of the load via the package or PCB board. The first cathode 9 and the fourth cathode 21 form an electrical interconnect connected to one end of the load via the package or PCB board. A positive voltage is applied to one side of the first anode 11 and the second cathode 10. Current flows from the first anode 11, through the first heavily doped P-region 6, the first lightly doped N-region 2, the first heavily doped N-region 4, and the first cathode 9 to the load. The current flows into the third anode 22, the third heavily doped P-region 17, the third lightly doped N-region 13, the third heavily doped N-region 15, the third cathode 20, and finally into the other end of the AC power supply. When the third cathode 20 and the fourth anode 23 are connected to a positive voltage, the current flows through the fourth anode 23, the fourth heavily doped P-region 18, the fourth lightly doped N-region 14, the fourth heavily doped N-region 16, and the fourth cathode 21 to the load, and then flows through the load into the second anode 12, the second heavily doped P-region 7, the second lightly doped N-region 3, the second heavily doped N-region 5, the second cathode 10, and finally into the other end of the AC power supply. In this case, the full-bridge rectifier chip effectively utilizes the chip area. Using the full-bridge rectifier chip in this case only requires packaging one chip, reducing packaging process steps and costs. Using the full-bridge rectifier chip in this case can reduce the amount of chip used by three-quarters, and the power density is four times that of traditional full-bridge devices.

[0125] Regarding the information disclosed in this case, the following points need to be clarified:

[0126] 1. The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case; other structures can refer to the general design.

[0127] 2. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0128] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a single-chip integrated full-bridge, characterized in that, Includes the following steps: Step S100: Prepare a first lightly doped N region (2) and a second lightly doped N region (3) on the epitaxial wafer (1); A first heavily doped N region (4) and a first heavily doped P region (6) are prepared inside the first lightly doped N region (2), and a second heavily doped N region (5) and a second heavily doped P region (7) are prepared inside the second lightly doped N region (3). Step S200: A first isolation layer (8) is prepared on the epitaxial wafer (1), and windows are opened at the first heavily doped N region (4), the first heavily doped P region (6), the second heavily doped N region (5), and the second heavily doped P region (7), respectively. In step S300, a first cathode (9), a first anode (11), a second cathode (10), and a second anode (12) are prepared at the first heavily doped N region (4), the first heavily doped P region (6), the second heavily doped N region (5), and the second heavily doped P region (7). In step S400, a third lightly doped N region (13) and a fourth lightly doped N region (14) are prepared on the epitaxial wafer (1); then a third heavily doped N region (15) and a third heavily doped P region (17) are prepared on the third lightly doped N region (13), and a fourth heavily doped N region (16) and a fourth heavily doped P region (18) are prepared on the fourth lightly doped N region (14). Step S500: A second isolation layer (19) is prepared on the epitaxial wafer (1), and windows are opened at the third doped N region (15), the third doped P region (17), the fourth doped N region (16) and the fourth doped P region (18); In step S600, the corresponding third cathode (20), third anode (22), fourth cathode (21) and fourth anode (23) are prepared in the third doped N region (15), the third doped P region (17), the fourth doped N region (16) and the fourth doped P region (18), and the entire device is prepared. The epitaxial wafer (1) includes, from bottom to top, a first intrinsic silicon region (24), an oxide separator (25), and a second intrinsic silicon region (26); The first lightly doped N region (2) extends downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1); the top surface of the first lightly doped N region (2) is provided with a first heavily doped N region (4) and a first heavily doped P region (6) extending downward at intervals. The second lightly doped N region (3) extends downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1); the top surface of the second lightly doped N region (3) is provided with a second heavily doped N region (5) and a second heavily doped P region (7) extending downward at intervals. The third lightly doped N region (13) extends upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); the bottom surface of the third lightly doped N region (13) is provided with a third heavily doped N region (15) and a third heavily doped P region (17) extending upward at intervals. The fourth lightly doped N region (14) extends upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); the bottom surface of the fourth lightly doped N region (14) is provided with a fourth heavily doped N region (16) and a fourth heavily doped P region (18) extending upward at intervals. The first lightly doped N region (2) and the third lightly doped N region (13) are spaced apart; the second lightly doped N region (3) and the fourth lightly doped N region (14) are spaced apart; The first cathode (9), the first anode (11), the second cathode (10), and the second anode (12) are in contact with the corresponding first heavily doped N region (4), first heavily doped P region (6), second heavily doped N region (5), and second heavily doped P region (7) below, forming a good ohmic contact.

2. The method for fabricating a single-chip integrated full-bridge according to claim 1, characterized in that, Step S100 specifically includes: Step S110: Using photolithography, a mask is used to protect the external regions of the first lightly doped N region (2) and the second lightly doped N region (3). The first lightly doped N region (2) and the second lightly doped N region (3) are formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the external regions of the first heavily doped N region (4) and the second heavily doped N region (5). The first heavily doped N region (4) and the second heavily doped N region (5) are formed by diffusion or ion implantation. In step S130, the external regions of the first heavily doped P region (6) and the second heavily doped P region (7) are protected by a mask using photolithography. The first heavily doped P region (6) and the second heavily doped P region (7) are formed by diffusion or ion implantation.

3. The method for fabricating a single-chip integrated full-bridge according to claim 1, characterized in that, Step S200 specifically includes: Step S210: Prepare the first isolation layer (8) by chemical vapor deposition; In step S220, the external regions of the first heavily doped N region (4), the first heavily doped P region (6), the second heavily doped N region (5), and the second heavily doped P region (7) are protected by a photolithography process using a mask, and windows are opened at the first heavily doped N region (4), the first heavily doped P region (6), the second heavily doped N region (5), and the second heavily doped P region (7) using an etching process.

4. The method for fabricating a single-chip integrated full-bridge according to claim 1, characterized in that, Step S400 specifically includes: Step S410: Using photolithography, a mask is used to protect the external regions of the third lightly doped N region (13) and the fourth lightly doped N region (14). The third lightly doped N region (13) and the fourth lightly doped N region (14) are formed by diffusion or ion implantation. Step S420: Using photolithography, a mask is used to protect the external regions of the third doped N region (15) and the fourth doped N region (16). The third doped N region (15) and the fourth doped N region (16) are formed by diffusion or ion implantation. In step S430, the external regions of the third doped P region (17) and the fourth doped P region (18) are protected by a mask using a photolithography process, and the third doped P region (17) and the fourth doped P region (18) are formed by diffusion or ion implantation processes.

5. The method for fabricating a single-chip integrated full-bridge according to claim 1, characterized in that, Step S500 includes: Step S510: Prepare a second isolation layer (19) by chemical vapor deposition. In step S520, the external regions of the third doped N region (15), the third doped P region (17), the fourth doped N region (16) and the fourth doped P region (18) are protected by photolithography using a mask, and windows are opened at the third doped N region (15), the third doped P region (17), the fourth doped N region (16) and the fourth doped P region (18) using an etching process.

6. A single-chip integrated full-bridge, fabricated by the method described in claim 1, characterized in that, It includes a second isolation layer (19), an epitaxial wafer (1) and a first isolation layer (8) arranged sequentially from bottom to top; The epitaxial wafer (1) includes: The first lightly doped N region (2) extends downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1); the top surface of the first lightly doped N region (2) is provided with a first heavily doped N region (4) and a first heavily doped P region (6) extending downward at intervals. The second lightly doped N region (3) extends downward from the top surface of the second intrinsic silicon region (26) of the epitaxial wafer (1); the top surface of the second lightly doped N region (3) is provided with a second heavily doped N region (5) and a second heavily doped P region (7) extending downward at intervals. The third lightly doped N region (13) extends upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); the bottom surface of the third lightly doped N region (13) is provided with a third heavily doped N region (15) and a third heavily doped P region (17) extending upward at intervals. The fourth lightly doped N region (14) extends upward from the bottom surface of the first intrinsic silicon region (24) of the epitaxial wafer (1); the bottom surface of the fourth lightly doped N region (14) is provided with a fourth heavily doped N region (16) and a fourth heavily doped P region (18) extending upward at intervals. The top surface of the first isolation layer (8) is provided with a downwardly extending: The first cathode (9) is connected to the first heavily doped N region (4); The first anode (11) is connected to the first heavily doped P region (6); The second cathode (10) is connected to the second heavily doped N region (5); The second anode (12) is connected to the second heavily doped P-region (7); The bottom surface of the second isolation layer (19) is provided with an upwardly extending: The third cathode (20) is connected to the third heavily doped N region (15); The third anode (22) is connected to the third heavily doped P-region (17); The fourth cathode (21) is connected to the fourth heavily doped N region (16); The fourth anode (23) is connected to the fourth heavily doped P region (18).

7. The single-chip integrated full-bridge according to claim 6, characterized in that, The thickness of the first intrinsic silicon region (24) is 50-1000um.

8. The single-chip integrated full-bridge according to claim 6, characterized in that, The thickness of the second intrinsic silicon region (26) is 50-1000um.

9. The single-chip integrated full-bridge according to claim 6, characterized in that, The oxide isolation layer (25) has a thickness of 1-10 μm.

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