Power device and preparation method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a power device and a preparation method, a power module, a power conversion circuit and a vehicle. The power device includes: a silicon carbide substrate; a first silicon carbide epitaxial layer, wherein the first silicon carbide epitaxial layer is located on one side of the silicon carbide substrate; a mobility-enhancing semiconductor layer, wherein the mobility-enhancing semiconductor layer is located on the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility-enhancing semiconductor layer is greater than the mobility of silicon carbide; a second silicon carbide epitaxial layer, wherein the second silicon carbide epitaxial layer is located on the side of the mobility-enhancing semiconductor layer away from the first silicon carbide epitaxial layer; wherein a body region and an active region are arranged on the surface of the second silicon carbide epitaxial layer away from the mobility-enhancing semiconductor layer; and a planar gate structure, wherein the planar gate structure is located on the surface of the second silicon carbide epitaxial layer away from the mobility-enhancing semiconductor layer. The technical solution provided by the embodiment of the present invention reduces the on-resistance of the power device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Planar silicon carbide metal-oxide field-effect transistor (SiC MOSFET) power devices are increasingly used in the field of electronic devices due to their excellent properties such as large bandgap, high critical breakdown electric field, and high temperature resistance.

[0003] However, the on-resistance of planar SiC metal-oxide field effect transistor power devices is relatively large. Summary of the invention

[0004] The present invention provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the power device.

[0005] According to one aspect of the present invention, there is provided a power device, comprising:

[0006] Silicon carbide substrate;

[0007] A first silicon carbide epitaxial layer, wherein the first silicon carbide epitaxial layer is located on one side of the silicon carbide substrate;

[0008] A mobility-enhancing semiconductor layer, the mobility-enhancing semiconductor layer being located on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility-enhancing semiconductor layer is greater than the mobility of silicon carbide;

[0009] A second silicon carbide epitaxial layer, the second silicon carbide epitaxial layer is located on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer; wherein a body region and an active region are arranged on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0010] A planar gate structure, wherein the planar gate structure is located on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0011] A source electrode, the source electrode being located on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0012] A drain electrode is located on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0013] Optionally, the mobility-enhancing semiconductor layer comprises a semiconductor epitaxial graphene buffer layer;

[0014] The semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are orderly bonded and connected via covalent bonds.

[0015] Optionally, the thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

[0016] Optionally, at the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than the mobility of silicon.

[0017] Optionally, a protective layer is further included, and the protective layer is located on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer.

[0018] Optionally, the protective layer includes a gold protective layer or an aluminum oxide protective layer.

[0019] According to another aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0020] Providing a silicon carbide substrate;

[0021] forming a first silicon carbide epitaxial layer on one side of the silicon carbide substrate;

[0022] forming a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility enhancing semiconductor layer is greater than the mobility of silicon carbide;

[0023] forming a second silicon carbide epitaxial layer on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer, wherein a body region and an active region are arranged on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0024] forming a planar gate structure on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0025] forming a source electrode on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer;

[0026] A drain is formed on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0027] Optionally, forming a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate comprises:

[0028] The side of the first silicon carbide epitaxial layer away from the silicon carbide substrate is heated to a preset temperature so that silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer serves as the mobility enhancing semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are orderly bonded and connected via covalent bonds.

[0029] Optionally, heating a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature so that silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, comprises:

[0030] Disposing the silicon carbide semiconductor layer and the first silicon carbide epitaxial layer opposite to each other away from the surface of the silicon carbide substrate;

[0031] The side of the first silicon carbide epitaxial layer away from the silicon carbide substrate and the silicon carbide semiconductor layer are heated to a preset temperature, so that the carbon surface of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is a silicon surface;

[0032] Silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is evaporated, thereby forming a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

[0033] Optionally, before forming the second silicon carbide epitaxial layer on the side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer, the method further includes:

[0034] A protective layer is formed on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer by an atomic layer deposition process.

[0035] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one power device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the power device.

[0036] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0037] The power conversion circuit includes a circuit board and at least one power device according to any one of the embodiments of the present invention, wherein the power device is electrically connected to the circuit board.

[0038] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as in any embodiment of the present invention, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and input the converted alternating current and / or direct current into the load.

[0039] The technical solution provided by the embodiment of the present invention is that a mobility enhancing semiconductor layer with a mobility greater than that of silicon carbide is arranged between the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer of a planar silicon carbide metal-oxide field effect transistor power device, and the mobility enhancing semiconductor layer is located in the conduction channel under the planar gate structure, which significantly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device, improving the on-current and power density, reducing power loss, and enhancing heat dissipation performance and device reliability; the carriers in the power device have a faster migration rate, so that the power device has a faster response speed.

[0040] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a schematic structural diagram of a planar silicon carbide metal-oxide field effect transistor power device provided by the prior art;

[0043] Figure 2 is a schematic structural diagram of a power device provided by an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of the structure of another power device provided by an embodiment of the present invention;

[0045] Figure 4 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention;

[0046] Figure 5-Figure 9 yes Figure 4 The structural schematic diagram corresponding to each step in the figure;

[0047] Fig.10 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0048] Fig.11 yes Fig.10 The schematic diagram of the process included in S1301;

[0049] Fig.12 yes Fig.11 The structural schematic diagram corresponding to each step in the figure;

[0050] Fig.13 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0051] Figure 14-16 yes Fig.13 Schematic diagram of the structures corresponding to steps S1401-S170. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or devices that are not clearly listed or inherent to these processes, methods, products or devices.

[0054] As described in the background art above, the on-resistance of planar silicon carbide metal-oxide field effect transistor power devices is relatively large. Figure 1 As shown, Figure 1It is a structural schematic diagram of a planar silicon carbide metal-oxide field effect transistor power device provided by the prior art, and the power device includes: a substrate 001, an epitaxial layer 002, a planar gate structure 003, a source 004 and a drain 005, wherein the epitaxial layer 002 is provided with a drift region 006, a body region 007 and an active region 008. The planar gate structure 003 includes a gate dielectric layer 009 and a gate 010. There is a JFET (Junction Field Effect Transistor) resistance in the drift region 006 between the two active regions 008, and the resistance is relatively large, resulting in a relatively large on-resistance of the entire planar silicon carbide metal-oxide field effect transistor power device. Due to the limitation of the size of the planar silicon carbide metal-oxide field effect transistor power device, it is impossible to reduce the on-resistance of the power device by thinning the thickness of the substrate 001 or the epitaxial layer 002.

[0055] In view of the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0056] like Figure 2 As shown, Figure 2 1 is a schematic diagram of a power device provided by an embodiment of the present invention, the power device comprising: a silicon carbide substrate 100; a first silicon carbide epitaxial layer 101, wherein the first silicon carbide epitaxial layer 101 is located on one side of the silicon carbide substrate 100; a mobility enhancing semiconductor layer 102, wherein the mobility enhancing semiconductor layer 102 is located on a side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, wherein at the same preset temperature, the mobility of the mobility enhancing semiconductor layer 102 is greater than the mobility of silicon carbide; a second silicon carbide epitaxial layer 103, wherein the second silicon carbide epitaxial layer 103 is located on the side of the mobility enhancing semiconductor layer 102 away from the silicon carbide substrate 100; The strong semiconductor layer 102 is located on a side away from the first silicon carbide epitaxial layer 101; wherein, a body region 104 and an active region 105 are arranged on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102; a planar gate structure 106, which is located on a side of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102; a source 107, which is located on a side of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102; and a drain 108, which is located on a side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101.

[0057] Exemplarily, the active region 105 includes a first conductivity type active region 109 and a second conductivity type active region 110, and the conductivity type of the first conductivity type active region 109 is opposite to the conductivity type of the body region 104. The conductivity type of the second conductivity type active region 110 is the same as the conductivity type of the body region 104. In other embodiments, the active region 105 may include only the first conductivity type active region 109. The planar gate structure 106 includes a gate dielectric layer 111 and a gate 112.

[0058] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the mobility enhancing semiconductor layer 102 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the electron movement resistance in the mobility enhancing semiconductor layer 102 is less than the movement resistance of the carriers in silicon carbide, thereby significantly increasing the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device.

[0059] The technical solution provided by the embodiment of the present invention is that a mobility enhancing semiconductor layer 102 with a mobility greater than that of silicon carbide is arranged between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 of the planar silicon carbide metal-oxide field effect transistor power device, and the mobility enhancing semiconductor layer 102 is located in the conduction channel under the planar gate structure 106, which significantly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device, improving the on-current and power density, reducing power loss, and enhancing heat dissipation performance and device reliability; the carriers in the power device have a faster migration rate, so that the power device has a faster response speed.

[0060] It should be noted that, in an embodiment of the present invention, a planar silicon carbide metal-oxide field effect transistor power device may include an N-channel planar silicon carbide metal-oxide field effect transistor power device or a P-channel planar silicon carbide metal-oxide field effect transistor power device. For an N-channel planar silicon carbide metal-oxide field effect transistor power device, a mobility enhancing semiconductor layer 102 having a mobility greater than the mobility of silicon carbide is provided between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103, which significantly increases the mobility of electrons in the channel of the power device. For a P-channel planar silicon carbide metal-oxide field effect transistor power device, a mobility enhancing semiconductor layer 102 having a mobility greater than the mobility of silicon carbide is provided between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103, which significantly increases the mobility of holes in the channel of the power device. Exemplarily, for an N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N-substrate, the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 are N-silicon carbide epitaxial layers, the first conductive type active region 109 is an N++ active region, the second conductive type active region 110 is a P++ active region, and the body region 104 is a P-type body region.

[0061] Optionally, based on the above technical solution, Figure 2As shown, the mobility enhancing semiconductor layer 102 includes a semiconductor epitaxial graphene buffer layer; the semiconductor epitaxial graphene buffer layer as the mobility enhancing semiconductor layer 102 and the first silicon carbide epitaxial layer 101 are orderly bonded and connected via covalent bonds.

[0062] Specifically, the preparation of the semiconductor epitaxial graphene buffer layer uses a heated first silicon carbide epitaxial layer 101. During the heating process, silicon evaporates before carbon, so that the semiconductor epitaxial graphene buffer layer is spontaneously crystallized on the surface of the first silicon carbide epitaxial layer 101. Among them, the semiconductor epitaxial graphene buffer layer is connected to the first silicon carbide epitaxial layer 101 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The semiconductor epitaxial graphene buffer layer is a two-dimensional semiconductor material as the mobility enhancement semiconductor layer 102. The mobility enhancement semiconductor layer 102 and the first silicon carbide epitaxial layer 101 are orderly bonded by covalent bonds. The semiconductor epitaxial graphene buffer layer has a very high mobility. Therefore, the technical solution of setting an epitaxial graphene buffer layer between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 greatly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. In addition, the semiconductor epitaxial graphene buffer layer also has the advantages of high strength and high thermal conductivity.

[0063] Optionally, based on the above technical solution, Figure 2 As shown, when the semiconductor epitaxial graphene buffer layer is used as the mobility enhancing semiconductor layer 102, its thickness is greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

[0064] Specifically, when the semiconductor epitaxial graphene buffer layer is used as the mobility enhancing semiconductor layer 102, the essence of the semiconductor epitaxial graphene buffer layer is a single layer of carbon atoms in the silicon carbide epitaxial layer, and its thickness is equivalent to the thickness of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2nm and less than or equal to 0.3nm, and its average thickness is about 0.25nm. The bonding between the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 is orderly and periodically arranged, which can ensure that the semiconductor epitaxial graphene buffer layer is a two-dimensional semiconductor material when used as the mobility enhancing semiconductor layer 102. The band gap of the semiconductor epitaxial graphene buffer layer is smaller than the band gap of silicon, which is about 0.6ev.

[0065] Optionally, based on the above technical solution, at the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than the mobility of silicon.

[0066] Exemplarily, under the same selected room temperature conditions, the room temperature mobility of the semiconductor epitaxial graphene buffer layer is greater than the room temperature mobility of silicon, and the maximum mobility can reach 5500cm 2 V -1 s -1 , which is about 10 times the room temperature mobility of silicon, greatly increasing the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. Room temperature is also called normal temperature or general temperature, generally defined as 25 degrees Celsius, and sometimes set to 300K (about 27 degrees Celsius).

[0067] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3 1 is a schematic diagram of the structure of another power device provided by an embodiment of the present invention. The power device further includes a protective layer 113 . The protective layer 113 is located on a side of the mobility enhancing semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 .

[0068] Specifically, the protective layer 113 is a thin film formed by an atomic layer deposition process, which is used to protect the mobility-enhancing semiconductor layer 102 from being away from the surface of the first silicon carbide epitaxial layer 101, and to avoid damage to the mobility-enhancing semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and subsequent film layers, thereby ensuring that the mobility-enhancing semiconductor layer 102 has a high mobility, thereby increasing the structural stability of the power device. Optionally, the thickness of the protective layer 113 is relatively thin, and the minimum thickness of the protective layer 113 is 5 nm. On the basis of achieving the function of protecting the mobility-enhancing semiconductor layer 102 from being away from the surface of the first silicon carbide epitaxial layer 101, the on-resistance of the power device is not greatly affected.

[0069] Optionally, based on the above technical solution, Figure 3 As shown, the protection layer 113 includes a gold protection layer or an aluminum oxide protection layer.

[0070] Specifically, the physical and chemical properties of the gold protective layer or the aluminum oxide protective layer are stable, and can protect the mobility enhancing semiconductor layer 102 away from the surface of the first silicon carbide epitaxial layer 101, thereby avoiding damage to the mobility enhancing semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and subsequent film layers.

[0071] The embodiment of the present invention also provides a method for preparing a power device. Figure 4 As shown, Figure 4 1 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, and the method for preparing a power device includes:

[0072] S110 . Provide a silicon carbide substrate.

[0073] like Figure 5 As shown, a silicon carbide substrate 100 is provided.

[0074] S120 , forming a first silicon carbide epitaxial layer on one side of the silicon carbide substrate.

[0075] like Figure 6 As shown, a first silicon carbide epitaxial layer 101 is formed on one side of a silicon carbide substrate 100 by an epitaxial process. The epitaxial process mainly includes at least one of evaporation growth, liquid phase epitaxy (LPE), molecular beam epitaxy (MBE) and chemical vapor deposition (CVD).

[0076] S130, forming a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility enhancing semiconductor layer is greater than the mobility of silicon carbide.

[0077] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the mobility enhancing semiconductor layer 102 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the electron movement resistance in the mobility enhancing semiconductor layer 102 is less than the movement resistance of the carriers in silicon carbide, thereby significantly increasing the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device.

[0078] like Figure 7 As shown, a mobility enhancing semiconductor layer 102 having a mobility greater than that of silicon carbide is formed on a side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and the resistance to the movement of carriers in the mobility enhancing semiconductor layer 102 is less than the resistance to the movement of carriers in the first silicon carbide epitaxial layer 101, thereby significantly increasing the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device.

[0079] S140, forming a second silicon carbide epitaxial layer on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer, wherein a body region and an active region are disposed on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer.

[0080] like Figure 8As shown, a second silicon carbide epitaxial layer 103 is formed on a side of the mobility enhancing semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 by an epitaxial process, wherein a body region 104 and an active region 105 are arranged on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102. Exemplarily, the active region 105 includes a first conductive type active region 109 and a second conductive type active region 110, and the conductive type of the first conductive type active region 109 is opposite to the conductive type of the body region 104. The conductive type of the second conductive type active region 110 is the same as the conductive type of the body region 104. In other embodiments, the active region 105 may include only the first conductive type active region 109.

[0081] S150, forming a planar gate structure on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer.

[0082] like Fig. 9 As shown, a planar gate structure 106 is formed on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancement semiconductor layer 102. The planar gate structure 106 includes a gate dielectric layer 111 and a gate 112. The gate dielectric layer 111 can be prepared by an atomic layer deposition (ALD) process, and the gate 112 can be a polysilicon gate, which can be prepared by a low pressure chemical vapor deposition (LPCVD) process.

[0083] S160, forming a source electrode on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer.

[0084] like Fig. 9 As shown, a source electrode 107 is formed on a surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102. The source electrode 107 is connected to the active region 105 and can be formed by a sputtering process.

[0085] S170, forming a drain on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0086] like Figure 2 As shown, a drain 108 is formed on a side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101 by a sputtering process. Exemplarily, the drain 108 includes a stack of Ti / Ni / Ag. Optionally, the silicon carbide substrate 100 may be thinned before forming the drain 108 to improve the heat dissipation performance of the power device.

[0087] The technical solution provided by the embodiment of the present invention forms a mobility enhanced semiconductor layer 102 with a mobility greater than that of silicon carbide between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 of a planar silicon carbide metal-oxide field effect transistor power device. The mobility enhanced semiconductor layer 102 is located in the conduction channel under the planar gate structure 106, which significantly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device, increasing the on-current and power density, reducing power loss, and enhancing heat dissipation performance and device reliability; the carriers in the power device have a faster migration rate, so that the power device has a faster response speed.

[0088] Optionally, based on the above technical solution, Fig.10 As shown, Fig.10 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, Fig.10 The power device manufacturing method and Figure 4 The difference between the power device preparation method shown is that Fig.10 for Figure 1 S130 is further defined in the embodiment, wherein S130 forms a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, including:

[0089] S1301. Heat the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer serves as a mobility enhancing semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by covalent bonding.

[0090] like Figure 7 As shown, the side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a preset temperature, so that the silicon on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, wherein the semiconductor epitaxial graphene buffer layer serves as a mobility enhancing semiconductor layer 102, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 are connected by covalent bonding.

[0091] Specifically, the preparation of the semiconductor epitaxial graphene buffer layer uses a heated first silicon carbide epitaxial layer 101. During the heating process, silicon evaporates before carbon, so that the semiconductor epitaxial graphene buffer layer is spontaneously crystallized on the surface of the first silicon carbide epitaxial layer 101. Among them, the semiconductor epitaxial graphene buffer layer is connected to the first silicon carbide epitaxial layer 101 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The semiconductor epitaxial graphene buffer layer is a two-dimensional semiconductor material as the mobility enhancement semiconductor layer 102. The mobility enhancement semiconductor layer 102 and the first silicon carbide epitaxial layer 101 are orderly bonded by covalent bonds. The semiconductor epitaxial graphene buffer layer has a very high mobility. Therefore, the technical solution of setting an epitaxial graphene buffer layer between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 greatly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. In addition, the semiconductor epitaxial graphene buffer layer also has the advantages of high strength and high thermal conductivity.

[0092] Optionally, based on the above technical solution, Fig.11 , Fig.11 yes Fig.10 The process diagram included in S1301, S1301 heats the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, including:

[0093] S1301a, arranging the silicon carbide semiconductor layer and the first silicon carbide epitaxial layer relatively away from the surface of the silicon carbide substrate.

[0094] like Fig.12 As shown, a silicon carbide semiconductor layer 114 is provided. The carbon surface of the silicon carbide semiconductor layer 114 is arranged opposite to the silicon surface of the first silicon carbide epitaxial layer 101 .

[0095] S1301b. Heat the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate and the silicon carbide semiconductor layer to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is the silicon surface.

[0096] like Fig.12As shown, the side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 and the silicon carbide semiconductor layer 114 are heated to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer 114 and the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is the silicon surface.

[0097] S1301c, silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is evaporated, thereby forming a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

[0098] like Fig.12 As shown, during the heating process, silicon evaporates before carbon, so that a semiconductor epitaxial graphene buffer layer is spontaneously crystallized on the surface of the first silicon carbide epitaxial layer 101, wherein the semiconductor epitaxial graphene buffer layer is connected to the first silicon carbide epitaxial layer 101 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. Since the carbon surface of the silicon carbide semiconductor layer 114 and the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at a preset temperature, a semiconductor epitaxial graphene buffer layer with a thickness equal to the thickness of a single layer of carbon atoms can be formed on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. When the semiconductor epitaxial graphene buffer layer is used as the mobility-enhancing semiconductor layer 102, the essence of the semiconductor epitaxial graphene buffer layer is a single layer of carbon atoms in the silicon carbide epitaxial layer, and its thickness is equivalent to the thickness of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2nm and less than or equal to 0.3nm, and its average thickness is about 0.25nm. The bonding between the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 is orderly and periodically arranged, which can ensure that the semiconductor epitaxial graphene buffer layer is a two-dimensional semiconductor material when used as the mobility enhancement semiconductor layer 102. The band gap of the semiconductor epitaxial graphene buffer layer is smaller than the band gap of silicon, which is about 0.6ev.

[0099] Optionally, based on the above technical solution, at the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than the mobility of silicon.

[0100] Exemplarily, under the same selected room temperature conditions, the room temperature mobility of the semiconductor epitaxial graphene buffer layer is greater than the room temperature mobility of silicon, and the maximum mobility can reach 5500cm 2 V -1 s -1, which is about 10 times the room temperature mobility of silicon, greatly increasing the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. Room temperature is also called normal temperature or general temperature, generally defined as 25 degrees Celsius, and sometimes set to 300K (about 27 degrees Celsius).

[0101] Optionally, based on the above technical solution, Fig.13 As shown, Fig.13 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, Fig.13 The power device manufacturing method and Figure 4 as well as Fig. 9 The difference between the manufacturing method of the power device shown is that a protective layer is formed before S140. Specifically, S140 further includes the following steps before forming the second silicon carbide epitaxial layer on the side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer:

[0102] S1401, forming a protective layer on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer through an atomic layer deposition process.

[0103] like Fig.14 As shown, a protective layer 113 is formed on the side of the mobility-enhancing semiconductor layer away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process. The protective layer 113 is a thin film formed by an atomic layer deposition process, and has excellent deposition uniformity and consistency due to the highly controllable deposition parameters (making its thickness, composition and structure). The protective layer 113 is used to protect the mobility-enhancing semiconductor layer 102 away from the surface of the first silicon carbide epitaxial layer 101, avoiding damage to the mobility-enhancing semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and the subsequent film layers, thereby ensuring that the mobility-enhancing semiconductor layer 102 has a high mobility, thereby increasing the structural stability of the power device. Optionally, the thickness of the protective layer 113 is relatively thin, and the minimum thickness of the protective layer 113 is 5nm. On the basis of achieving the function of protecting the mobility-enhancing semiconductor layer 102 away from the surface of the first silicon carbide epitaxial layer 101, the on-resistance of the power device is not greatly affected.

[0104] Optionally, a protective layer 113 including a gold protective layer or an aluminum oxide protective layer is formed on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process.

[0105] Specifically, the physical and chemical properties of the gold protective layer or the aluminum oxide protective layer are stable, and can protect the mobility enhancing semiconductor layer 102 away from the surface of the first silicon carbide epitaxial layer 101, thereby avoiding damage to the mobility enhancing semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and subsequent film layers.

[0106] like Fig.15 As shown, after forming a protective layer 113 on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process, it also includes: forming a second silicon carbide epitaxial layer 103 on a side of the mobility enhancing semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 by an epitaxial process, wherein a body region 104 and an active region 105 are set on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102.

[0107] like Fig.16 As shown, a planar gate structure 106 is formed on a surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102. A source electrode 107 is formed on a surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancing semiconductor layer 102. Figure 3 As shown, a drain 108 is formed on a side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101 by a sputtering process.

[0108] The embodiment of the present invention further provides a power module, which includes a substrate and at least one power device described in any of the above embodiments, and the substrate is used to carry the power device. Therefore, the power module provided by the embodiment of the present invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0109] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and any power device described in the above embodiments, and the power device is electrically connected to the circuit board. Therefore, the power conversion circuit provided by the embodiment of the present invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0110] An embodiment of the present invention further provides a vehicle, which includes a load and a power conversion circuit as described in any of the above embodiments, wherein the power conversion circuit is used to convert AC and / or DC into AC and / or DC and then input it into the load. Among them, the scheme in which the power conversion circuit is used to convert AC and / or DC into AC and / or DC and then input it into the load includes: the power conversion circuit is used to convert AC into AC and then input it into the load. The power conversion circuit is used to convert AC into DC and then input it into the load. The power conversion circuit is used to convert DC into AC and then input it into the load. The power conversion circuit is used to convert DC into DC and then input it into the load. Therefore, the vehicle provided by the embodiment of the present invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0111] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0112] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: Silicon carbide substrate; A first silicon carbide epitaxial layer, wherein the first silicon carbide epitaxial layer is located on one side of the silicon carbide substrate; A mobility-enhancing semiconductor layer, the mobility-enhancing semiconductor layer being located on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility-enhancing semiconductor layer is greater than the mobility of silicon carbide; A second silicon carbide epitaxial layer, the second silicon carbide epitaxial layer is located on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer; wherein a body region and an active region are arranged on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; A planar gate structure, wherein the planar gate structure is located on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; a source electrode, the source electrode being located on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; a drain electrode, the drain electrode being located on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer; The mobility-enhancing semiconductor layer includes a semiconductor epitaxial graphene buffer layer; The semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are orderly bonded and connected via covalent bonds.

2. The power device according to claim 1, characterized in that: The thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

3. The power device according to claim 1 or 2, characterized in that: At the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than the mobility of silicon.

4. The power device according to claim 1, characterized in that: The invention also includes a protection layer, wherein the protection layer is located on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer.

5. The power device according to claim 4, characterized in that: The protective layer includes a gold protective layer or an aluminum oxide protective layer.

6. A method for preparing a power device, characterized in that: include: Providing a silicon carbide substrate; forming a first silicon carbide epitaxial layer on one side of the silicon carbide substrate; forming a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility enhancing semiconductor layer is greater than the mobility of silicon carbide; forming a second silicon carbide epitaxial layer on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer, wherein a body region and an active region are arranged on a surface of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; forming a planar gate structure on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; forming a source electrode on a side of the second silicon carbide epitaxial layer away from the mobility enhancing semiconductor layer; forming a drain electrode on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer; Forming a mobility enhancing semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate comprises: The side of the first silicon carbide epitaxial layer away from the silicon carbide substrate is heated to a preset temperature so that silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer serves as the mobility enhancing semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are orderly bonded and connected via covalent bonds.

7. The method for preparing a power device according to claim 6, characterized in that: Heating a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature so that silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, thereby forming a semiconductor epitaxial graphene buffer layer on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, comprising: Disposing the silicon carbide semiconductor layer and the first silicon carbide epitaxial layer opposite to each other away from the surface of the silicon carbide substrate; The side of the first silicon carbide epitaxial layer away from the silicon carbide substrate and the silicon carbide semiconductor layer are heated to a preset temperature, so that the carbon surface of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is a silicon surface; Silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is evaporated, thereby forming a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

8. The method for preparing a power device according to claim 6, characterized in that: Before forming a second silicon carbide epitaxial layer on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer, the method further includes: A protective layer is formed on a side of the mobility enhancing semiconductor layer away from the first silicon carbide epitaxial layer by an atomic layer deposition process.

9. A power module, characterized in that: It comprises a substrate and at least one power device according to any one of claims 1 to 5, wherein the substrate is used to support the power device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one power device according to any one of claims 1 to 5, wherein the power device is electrically connected to the circuit board.

11. A vehicle, characterized in that: It comprises a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input the converted alternating current and / or direct current into the load.

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