Low power consumption dynamic comparator with dual clock edge comparison and control method

Abstract

The present application relates to a low-power dynamic comparator with dual-clock edge comparison, comprising: designing the pre-amplification stage of the dynamic comparator to be a structure that includes both NMOS and PMOS input pairs, wherein when the PMOS input pair compares the comparator input signal, the NMOS input pair assists in the comparison, and utilizes the characteristic that nodes DA and DB are finally charged to VDD to reset the next operation of the NMOS input pair; similarly, when the NMOS input pair is compared, the PMOS input pair assists in the comparison, and nodes DA and DB are finally discharged to VSS to reset the next operation of the PMOS input pair; NMOS and PMOS alternately dominate the comparison process, so that the comparator compares at both the rising and falling edges of the clock CLK; in addition, an additional group of NMOS and PMOS input pairs with smaller size that are controlled by the clock are introduced; the present application can significantly reduce the power consumption of the comparator, greatly improve the speed of the comparator, reduce the clock load, and significantly broaden the common-mode voltage input range of the comparator.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a low-power dynamic comparator for dual-clock edge comparison and a control method. Background Art

[0002] In recent years, with the development of technologies such as the Internet of Things, wearable devices, and biomedicine, a large number of devices that need to work continuously for a long time have been designed, and low power consumption has become a key technical requirement for comparators. In addition, in some high-speed circuits with asynchronous timing control, such as asynchronous clock successive approximation analog-to-digital converters, reducing the speed requirement of the clock required by the comparator is conducive to improving the operating speed of the entire circuit and reducing the load on the clock.

[0003] The working process of the traditional dynamic comparator is divided into two stages: reset and comparison. The reset stage is triggered by the rising edge of the clock CLK, and the parasitic capacitances of the two output nodes DA and DB of the pre-amplifier stage of the comparator are charged to VDD. The comparison stage is triggered by the falling edge of the clock CLK, and the parasitic capacitances of the DA and DB nodes of the pre-amplifier stage of the comparator are respectively controlled by the input signals VIP and VI N to discharge from the NMOS input pair to VSS at different speeds. The latch stage of the comparator obtains a differential and stable comparison result according to the order of the discharge speeds of DA and DB to the judgment level.

[0004] There are three problems with traditional structure dynamic comparators: First, the input common mode range of traditional comparators is limited. For example, when the common mode voltage of the input signal of the pre-amplifier stage of the NMOS input pair is low, the working speed is seriously reduced and even the correct comparison result cannot be obtained; second, the parasitic capacitance of the two output nodes DA and DB of the pre-amplifier stage of the traditional comparator is charged from VSS to VDD in the reset phase, and discharged to VSS in the subsequent comparison phase, consuming a total power consumption of C*VDD2 and only obtaining one comparison result, which results in a large power consumption required for each comparison of the traditional comparator; third, the reset and comparison processes of the traditional comparator are controlled by the rising edge and falling edge of the clock CLK respectively, so each comparison requires a complete clock cycle, so the traditional comparator pair needs a faster control clock, which has a large clock load.

[0005] To summarize, the pre-amplifier stage of the NMOS input pair of the traditional dynamic comparator in the prior art has a serious drop in working speed and may even fail to obtain a correct comparison result when the common-mode voltage of the input signal is low, the traditional comparator requires high power consumption for each comparison, and the traditional comparator pair requires a faster control clock, which puts a heavy clock load on the clock. The present application makes corresponding explorations to solve these problems. Summary of the invention

[0006] The purpose of the present application is to solve the above-mentioned problem and to provide a low-power dynamic comparator with dual clock edge comparison and a control method, an electronic device, a computer device, and a computer-readable storage medium.

[0007] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0008] A low-power dynamic comparator with dual clock edge comparison proposed to meet one of the purposes of the present application includes a pre-amplification stage, a P-input latch stage and an N-input latch stage;

[0009] The pre-amplification stage includes NMOS transistors M0, M1, M2, M3, M4 and PMOS transistors M5, M6, M7, M8, M9, wherein the gates of the NMOS input pair of NMOS transistors M1 and M2 are respectively connected to input signals VIP and VI N, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the NMOS transistors M3 and M4 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the NMOS transistor M0 is grounded to VSS, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ; the gates of the PMOS input pair of PMOS transistors M5 and M6 are respectively connected to input signals VI N and VIP, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the PMOS transistors M7 and M8 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the PMOS transistor M9 is connected to the power supply VDD, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ;

[0010] The P input latch stage includes PMOS transistors M10, M11, M12, M13 and NMOS transistors M14, M15, M16, M17, wherein the gates of the PMOS input pair PMOS transistors M10 and M11 are connected to the pre-amplifier stage output nodes DA and DB respectively, the drains are connected to the latch stage output nodes PLP and PLN respectively, and the sources are connected to the drains of the PMOS transistors M12 and M13 respectively; the sources of the PMOS transistors M12 and M13 are connected to the power supply VDD, and the gates are connected to the nodes PLN and PLP respectively; the sources of the NMOS transistors M14 and M15 are connected to the ground VSS, the gates are connected to the nodes PLN and PLP respectively, and the drains are connected to the nodes PLP and PLN respectively; the sources of the NMOS transistors M16 and M17 are connected to the ground VSS, the gates are connected to the clock signal CLKB, and the drains are connected to the nodes PLP and PLN respectively;

[0011] The N-input latch stage includes NMOS transistors M18, M19, M20, and M21, and PMOS transistors M22, M23, M24, and M25; wherein, the gates of the NMOS input pair NMOS transistors M18 and M19 are respectively connected to the pre-amplifier stage output nodes DB and DA, the drains are respectively connected to the latch stage output nodes NLP and NLN, and the sources are respectively connected to the drains of M20 and M21; the sources of the NMOS transistors M20 and M21 are connected to the ground VSS, and the gates are respectively connected to the nodes NLN and NLP; the sources of the PMOS transistors M22 and M23 are connected to the power supply VDD, the gates are respectively connected to the nodes NLN and NLP, and the drains are respectively connected to the nodes NLP and NLN; the sources of the PMOS transistors M24 and M25 are connected to the power supply VDD, the gates are respectively connected to the clock signal CLKB, and the drains are respectively connected to the nodes NLP and NLN, and the inverted signals of NLP and NLN are respectively connected to the PLP and PLN through the OR gate to obtain the entire comparator outputs OUTP and OUTN.

[0012] A dual-clock edge comparison low-power dynamic comparator control method proposed to meet another purpose of the present application is applied to the dual-clock edge comparison low-power dynamic comparator as claimed in claim 1, comprising:

[0013] The N input comparison stage starts from the rising edge of the clock signal CLK. In this stage, the NMOS input pair in the pre-amplifier stage leads the comparison process, and the PMOS input pair assists the comparison. CLK is at a high level, so that the PMOS transistors M9, M7, and M8 in the pre-amplifier stage are turned off, and the NMOS transistor M0 is turned on. The NMOS input pair and the NMOS transistors M1 and M2 are controlled by the input signals VIP and VI N, respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is discharged from VDD through the latch decision level at different speeds, and finally discharged to VSS;

[0014] The PMOS input pair M5 and M6 are controlled by the input signals VI N and VIP respectively, assisting the discharge process of the NMOS input pair; the small-size NMOS transistors M3 and M4 are turned on by CLK control to ensure that the nodes DA and DB are finally discharged to VSS;

[0015] At this stage, CLKB is at a low level, so that the PMOS transistors M24 and M25 in the N-input latch stage are turned on, and the output terminals NLP and NLN are reset to the digital code "1 1"; at this stage, CLKB is at a low level, so that the NMOS transistors M16 and M17 in the P-input latch stage are turned off, and the PMOS input pair PMOS transistors M10 and M11 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of the PMOS transistors M12 and M13 and the NMOS transistors M14 and M15, so that the output terminals PLP and PLN of the P-input latch stage finally output the digital code "1 0" or "0 1".

[0016] Optionally, according to the above-mentioned low-power dynamic comparator control method for dual-clock edge comparison, it also includes:

[0017] The P input comparison phase starts from the falling edge of the clock signal CLK. In this phase, the comparison process is dominated by the PMOS input pair in the pre-amplifier stage, and the NMOS input pair assists the comparison. CLK is at a low level, so that the NMOS transistors M0, M3, and M4 in the pre-amplifier stage are turned off, and the PMOS transistor M9 is turned on. The PMOS input pairs M5 and M6 are controlled by the input signals VI N and VIP, respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is charged from VSS to the latch decision level at different speeds, and finally charged to VDD.

[0018] The NMOS input pair NMOS transistors M1 and M2 are controlled by input signals VIP and VI N respectively, assisting the discharge process of the PMOS input pair; the small-size PMOS transistors M7 and M8 are turned on by CLK control to ensure that the nodes DA and DB are finally charged to VDD;

[0019] At this stage, CLKB is at a high level, so that the NMOS transistors M16 and M17 in the P input latch stage are turned on, and the output terminals PLP and PLN are reset to the digital code "0 0"; at this stage, CLKB is at a high level, so that the PMOS transistors M24 and M25 in the N input latch stage are turned off, and the NMOS input pair NMOS transistors M18 and M19 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of NMOS transistors M20 and M21 and PMOS transistors M22 and M23, so that the output terminals NLP and NLN of the N input latch stage finally output the digital code "0 1" or "1 0".

[0020] An electronic device proposed to meet another purpose of the present application uses the above-mentioned low-power dynamic comparator with dual clock edge comparison.

[0021] A computer device proposed to meet another purpose of the present application includes a memory and a processor, wherein the memory stores a computer program implemented according to any of the methods described above, and when the processor executes the computer program, it implements any of the low-power dynamic comparator control methods for dual-clock edge comparison described above.

[0022] A computer-readable storage medium is proposed to meet another purpose of the present application, which stores a computer program implemented according to any of the above methods in the form of computer-readable instructions. When the computer program is called and executed by a computer, it executes the steps included in the corresponding method.

[0023] Compared with the prior art, the present application aims at the problems that the pre-amplifier stage of the NMOS input pair of the traditional structure dynamic comparator in the prior art seriously reduces the working speed and even fails to obtain the correct comparison result when the common mode voltage of the input signal is low, the traditional comparator requires large power consumption for each comparison, and the traditional comparator pair requires a faster control clock, which has a large clock load. The present application includes but is not limited to the following beneficial effects:

[0024] First, the pre-amplification stage of the comparator of the present application includes both NMOS and PMOS input pairs, and the structure in which the dominant input pair and the auxiliary input pair work simultaneously improves the equivalent transconductance of the pre-amplification stage, improves the working speed of the comparator, and significantly broadens the common-mode voltage input range of the comparator;

[0025] Secondly, the two groups of input pairs of NMOS and PMOS in the comparator of the present application alternately dominate the comparison process, and the comparison process is also reset for the next comparison, which saves the power consumption required in the reset stage of the traditional single input pair structure. Therefore, the average power consumption of the pre-amplifier stage per comparison is reduced from C*VDD2 to 0.5*C*VDD2, which has the advantage of low power consumption;

[0026] Thirdly, in the comparator of the present application, the comparison process is dominated by the NMOS input pair at the rising edge of the clock CLK, and the comparison process is dominated by the PMOS input pair at the falling edge of the clock CLK. Two comparisons can be performed in each clock cycle, so that the clock speed requirement required by the comparator is reduced by 50% compared with the traditional structure, and the clock load is significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0028] Figure 1 This is a circuit schematic diagram of a low-power dynamic comparator for dual-clock edge comparison in an embodiment of the present application;

[0029] Figure 2A schematic diagram of a pre-amplification stage of a low-power dynamic comparator with dual clock edge comparison in an embodiment of the present application and a pre-amplification stage of a dynamic comparator with a traditional structure;

[0030] Figure 3 Schematic diagram of the on-off status of the MOS tube and the current flow direction (left) and its equivalent circuit (right) in the N-input comparison stage in the embodiment of the present application;

[0031] Figure 4 Schematic diagram of the on-off status of the MOS tube and the current flow direction (left) and its equivalent circuit (right) in the P input comparison stage in the embodiment of the present application;

[0032] Figure 5 A schematic diagram of a simulated node voltage waveform and a power supply current waveform of a low-power dynamic comparator with dual clock edge comparison in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of a simulation node voltage waveform and a power supply current waveform of a conventional structure comparator in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of average power consumption per comparison for different input signal voltage differences in an embodiment of the present application;

[0035] Figure 8 This is a schematic diagram of the average time consumption for each comparison when the common mode voltage of the input signal is different in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0037] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0038] Unless the mutually exclusive relationship between the embodiments to be disclosed in this application is explicitly stated, the relevant technical features involved in each embodiment can be cross-combined to flexibly construct a new embodiment, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or solve certain deficiencies in the prior art. Those skilled in the art should be aware of this flexibility.

[0039] See also Figure 1 as well as Figure 2 , the low-power dynamic comparator with dual clock edge comparison of the present application, in one embodiment thereof, comprises a pre-amplification stage, a P-input latch stage and an N-input latch stage;

[0040] The pre-amplification stage includes NMOS transistors M0, M1, M2, M3, M4 and PMOS transistors M5, M6, M7, M8, M9, wherein the gates of the NMOS input pair of NMOS transistors M1 and M2 are respectively connected to input signals VIP and VI N, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the NMOS transistors M3 and M4 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the NMOS transistor M0 is grounded to VSS, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ; the gates of the PMOS input pair of PMOS transistors M5 and M6 are respectively connected to input signals VI N and VIP, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the PMOS transistors M7 and M8 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the PMOS transistor M9 is connected to the power supply VDD, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ;

[0041] The P input latch stage includes PMOS transistors M10, M11, M12, M13 and NMOS transistors M14, M15, M16, M17, wherein the gates of the PMOS input pair PMOS transistors M10 and M11 are connected to the pre-amplifier stage output nodes DA and DB respectively, the drains are connected to the latch stage output nodes PLP and PLN respectively, and the sources are connected to the drains of the PMOS transistors M12 and M13 respectively; the sources of the PMOS transistors M12 and M13 are connected to the power supply VDD, and the gates are connected to the nodes PLN and PLP respectively; the sources of the NMOS transistors M14 and M15 are connected to the ground VSS, the gates are connected to the nodes PLN and PLP respectively, and the drains are connected to the nodes PLP and PLN respectively; the sources of the NMOS transistors M16 and M17 are connected to the ground VSS, the gates are connected to the clock signal CLKB, and the drains are connected to the nodes PLP and PLN respectively;

[0042] The N-input latch stage includes NMOS transistors M18, M19, M20, and M21, and PMOS transistors M22, M23, M24, and M25; wherein, the gates of the NMOS input pair NMOS transistors M18 and M19 are respectively connected to the pre-amplifier stage output nodes DB and DA, the drains are respectively connected to the latch stage output nodes NLP and NLN, and the sources are respectively connected to the drains of M20 and M21; the sources of the NMOS transistors M20 and M21 are connected to the ground VSS, and the gates are respectively connected to the nodes NLN and NLP; the sources of the PMOS transistors M22 and M23 are connected to the power supply VDD, the gates are respectively connected to the nodes NLN and NLP, and the drains are respectively connected to the nodes NLP and NLN; the sources of the PMOS transistors M24 and M25 are connected to the power supply VDD, the gates are respectively connected to the clock signal CLKB, and the drains are respectively connected to the nodes NLP and NLN, and the inverted signals of NLP and NLN are respectively connected to the PLP and PLN through the OR gate to obtain the entire comparator outputs OUTP and OUTN.

[0043] A dual-clock edge comparison low-power dynamic comparator control method proposed to meet one of the purposes of the present application is applied to the above-mentioned dual-clock edge comparison low-power dynamic comparator, including:

[0044] The N-input comparison phase of the low-power dynamic comparator starts from the rising edge of the clock signal CLK. In this phase, the NMOS input pair in the preamplifier stage leads the comparison process, and the PMOS input pair assists the comparison. Figure 3 ,like Figure 3 As shown, CLK is at a high level, so that the PMOS transistors M9, M7, and M8 in the pre-amplifier stage are turned off, the NMOS transistor M0 is turned on, and the NMOS input pair NMOS transistors M1 and M2 are controlled by the input signals VIP and VI N, respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is discharged from VDD through the Latch decision level at different speeds, and finally discharged to VSS;

[0045] The PMOS input pair M5 and M6 are controlled by the input signals VI N and VIP respectively, assisting the discharge process of the NMOS input pair; the small-size NMOS transistors M3 and M4 are turned on by CLK control to ensure that the nodes DA and DB are finally discharged to VSS;

[0046] At this stage, CLKB is at a low level, so that the PMOS transistors M24 and M25 in the N-input latch stage are turned on, and the output terminals NLP and NLN are reset to the digital code "1 1"; at this stage, CLKB is at a low level, so that the NMOS transistors M16 and M17 in the P-input latch stage are turned off, and the PMOS input pair PMOS transistors M10 and M11 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of the PMOS transistors M12 and M13 and the NMOS transistors M14 and M15, so that the output terminals PLP and PLN of the P-input latch stage finally output the digital code "1 0" or "0 1".

[0047] Furthermore, according to the above-mentioned low-power dynamic comparator control method for dual-clock edge comparison, it also includes:

[0048] The P input comparison phase of the low power dynamic comparator starts from the falling edge of the clock signal CLK. In this phase, the PMOS input pair in the preamplifier stage leads the comparison process, and the NMOS input pair assists the comparison. Figure 4 , the equivalent circuit diagram is as follows Figure 4 As shown, CLK is at a low level, so that the NMOS transistors M0, M3, and M4 in the pre-amplifier stage are turned off, the PMOS transistor M9 is turned on, and the PMOS input pairs M5 and M6 are controlled by the input signals VI N and VIP respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is charged from VSS through the latch decision level at different speeds, and finally charged to VDD;

[0049] The NMOS input pair NMOS transistors M1 and M2 are controlled by input signals VIP and VI N respectively, assisting the discharge process of the PMOS input pair; the small-size PMOS transistors M7 and M8 are turned on by CLK control to ensure that the nodes DA and DB are finally charged to VDD;

[0050] At this stage, CLKB is at a high level, so that the NMOS transistors M16 and M17 in the P input latch stage are turned on, and the output terminals PLP and PLN are reset to the digital code "0 0"; at this stage, CLKB is at a high level, so that the PMOS transistors M24 and M25 in the N input latch stage are turned off, and the NMOS input pair NMOS transistors M18 and M19 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of NMOS transistors M20 and M21 and PMOS transistors M22 and M23, so that the output terminals NLP and NLN of the N input latch stage finally output the digital code "0 1" or "1 0".

[0051] In some embodiments, based on the 65nm CMOS process library, Cadence simulation software is used to build a low-power dynamic comparator with dual clock edge comparison of the present application, and a traditional structure comparator is built for comparative simulation tests. In order to eliminate the influence of factors such as size and parasitic capacitance on the comparative test, the low-power dynamic comparator of the present application and the traditional comparator use MOS tubes of the same size at corresponding circuit positions, wherein the NMOS input pair size W / L is 5um / 120nm, and the PMOS input pair size W / L is 10um / 120nm. The power supply voltage VDD is 1.2V, the common mode voltage of the comparator input signal VIP and VI N is 0.6V, and the differential mode voltage is 50mV. The frequency of the external input clock CLK of the comparator of the present application is 1GHz, and the CLK frequency of the traditional comparator is changed to 2GHz. Trans i ent simulation is performed on both the traditional structure comparator and the comparator of the present application to obtain the input, output, and internal node voltage waveforms and the current waveform obtained from the power supply. Figure 5 , Figure 6 As shown, the simulation waveform shows that the voltage waveform of each node of the comparator of the present application meets the design requirements, the function is normal, and the comparison result is correct; the comparator of the present application requires an average of 0.5 clock cycles to generate a comparison result, while the traditional comparator requires 1 clock cycle, so the clock speed requirement required for the comparator of the present application can be reduced by 50%; the average time consumption for each comparison is 117.3ps, compared with 141.5ps of the traditional comparator, the speed is improved by about 17%; the average power consumption for each comparison is 34.67fJ, compared with 50.85fJ of the traditional comparator, which is a reduction of about 32% in power consumption, which is basically consistent with the theoretical analysis. The comparative experiment finally proves that the comparator of the present application has the advantages of fast speed, low power consumption and low clock speed requirement.

[0052] In some embodiments, the power consumption saved by the comparator of the present application under different input signal voltage differences is tested, VIP-VI N is adjusted from 0.1mV to 500mV in steps, and the common mode voltage of the input signal is kept unchanged. The current waveform obtained from the source is simulated, and the average power consumption of each comparison is calculated and compared with the traditional structure comparator. Figure 7 As shown, with the change of input signal voltage, the average power consumption of each comparison of the comparator of the present application is only about 65% of that of the traditional structure comparator. Comparative tests show that the comparator of the present application has the advantage of low power consumption.

[0053] In some embodiments, the working speed of the comparator of the present application is tested under different input signal common mode voltages, the input signal common mode voltage is adjusted from 0.2V to 1.0V, and the input signal voltage difference is kept unchanged. The time difference from each comparison clock edge to the time when the comparator obtains the comparison result is simulated, and the average time consumption of each comparison is calculated and compared with the traditional structure comparator, such as Figure 8When the input signal common-mode voltage is lower than 0.5V, the speed of the traditional comparator is significantly reduced, and when it is lower than 0.3V, it is even impossible to obtain the correct comparison result; while the comparator of the present application can obtain the correct comparison result under the common-mode voltage close to "rail-to-rail" in the test, and it takes less time. The comparative test shows that the comparator of the present application significantly broadens the common-mode input range and works faster.

[0054] The comparator of the present application overcomes the problems of limited input common mode range, high power consumption and high clock speed requirements of traditional dynamic comparators through an improved pre-amplification stage circuit design. It is a low-power, high-speed dynamic comparator that can perform comparisons on both the rising and falling edges of the clock CLK.

[0055] The present application designs the pre-amplification stage of the dynamic comparator to include both NMOS and PMOS input pairs, wherein when the PMOS input pair compares the comparator input signal, the NMOS input pair assists in the comparison, and utilizes the characteristic that the nodes DA and DB are finally charged to VDD to reset the next NMOS input pair operation. Similarly, when the NMOS input pair is compared, the PMOS input pair assists in the comparison, and the nodes DA and DB are finally discharged to VSS to reset the next PMOS input pair operation. NMOS and PMOS alternately dominate the comparison process, and the comparator is compared at both the rising and falling edges of the clock CLK. In addition, an additional group of smaller NMOS and PMOS input pairs controlled by the clock are introduced to speed up the charging and discharging of the capacitor when the voltage difference of the comparator input signal is large.

[0056] The structure in which the dominant input pair and the auxiliary input pair work simultaneously improves the equivalent transconductance of the pre-amplifier stage, which can effectively improve the operating speed of the comparator. At the same time, the complementary characteristics of the conduction capabilities of NMOS and PMOS under different input common-mode voltages are utilized to allow the input signal common-mode voltage to change close to "rail-to-rail", significantly widening the common-mode voltage input range of the comparator.

[0057] Compared with the traditional comparator, the pre-amplifier stage consumes C*VDD2 power consumption in one clock cycle and completes only one comparison. The pre-amplifier stage of the comparator of the present application consumes C*VDD2 power consumption in one clock cycle and completes two comparisons. The average power consumption of each comparison is only 0.5*C*VDD2, which saves 50% of the power consumption from the pre-amplifier stage. Since the pre-amplifier stage accounts for about 70% of the power consumption of the entire comparator, the comparator of the present application saves about 35% of the power consumption compared with the traditional comparator.

[0058] In addition, since the comparator compares the input signal at both the rising and falling edges of the clock CLK, the speed requirement of the clock required by the comparator is reduced by 50%, effectively reducing the load of the comparator on the clock.

[0059] It can be seen from the above embodiments that, compared with the prior art, the present application aims at the problems that the pre-amplifier stage of the NMOS input pair of the traditional structure dynamic comparator in the prior art seriously reduces the working speed and even fails to obtain the correct comparison result when the common mode voltage of the input signal is low, the traditional comparator requires large power consumption for each comparison, and the traditional comparator pair requires a faster control clock, which has a large clock load. The present application includes but is not limited to the following beneficial effects:

[0060] First, the pre-amplification stage of the comparator of the present application includes both NMOS and PMOS input pairs, and the structure in which the dominant input pair and the auxiliary input pair work simultaneously improves the equivalent transconductance of the pre-amplification stage, improves the working speed of the comparator, and significantly broadens the common-mode voltage input range of the comparator;

[0061] Secondly, the two groups of input pairs of NMOS and PMOS in the comparator of the present application alternately dominate the comparison process, and the comparison process is also reset for the next comparison, which saves the power consumption required in the reset stage of the traditional single input pair structure. Therefore, the average power consumption of the pre-amplifier stage per comparison is reduced from C*VDD2 to 0.5*C*VDD2, which has the advantage of low power consumption;

[0062] Thirdly, in the comparator of the present application, the comparison process is dominated by the NMOS input pair at the rising edge of the clock CLK, and the comparison process is dominated by the PMOS input pair at the falling edge of the clock CLK. Two comparisons can be performed in each clock cycle, so that the clock speed requirement required by the comparator is reduced by 50% compared with the traditional structure, and the clock load is significantly reduced.

[0063] The present application also proposes an electronic device, which uses the above-mentioned low-power dynamic comparator with dual clock edge comparison.

[0064] The present application also proposes a computer device, including a memory and a processor, wherein the memory stores a computer program implemented according to any of the methods described above, and when the processor executes the computer program, it implements any of the low-power dynamic comparator control methods for dual-clock edge comparison described above.

[0065] The present application also proposes a computer-readable storage medium, which stores a computer program implemented according to any of the above methods in the form of computer-readable instructions. When the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

[0066] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

[0067] In summary, the comparator of the present application includes both NMOS and PMOS input pairs, and the dominant input pair and the auxiliary input pair work simultaneously, which can greatly reduce the power consumption of the comparator, increase the speed of the comparator, reduce the clock load, and significantly widen the common-mode voltage input range of the comparator.

Claims

1. A low-power dynamic comparator with dual clock edge comparison, characterized in that: It includes a pre-amplifier stage, a P-input latch stage and an N-input latch stage; The pre-amplification stage includes NMOS transistors M0, M1, M2, M3, M4 and PMOS transistors M5, M6, M7, M8, M9, wherein the gates of the NMOS input pair NMOS transistors M1 and M2 are respectively connected to input signals VIP and VIN, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the NMOS transistors M3 and M4 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the NMOS transistor M0 is grounded to VSS, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ; the gates of the PMOS input pair PMOS transistors M5 and M6 are respectively connected to input signals VIN and VIP, the drains are respectively connected to pre-amplification stage output nodes DA and DB, and the sources are connected to the node VQ; the gates of the PMOS transistors M7 and M8 are connected to the clock signal CLK, the drains are respectively connected to the nodes DA and DB, and the sources are connected to the node VQ; the source of the PMOS transistor M9 is connected to the power supply VDD, the gate is connected to the clock signal CLK, and the drain is connected to the node VQ; The P input latch stage includes PMOS transistors M10, M11, M12, M13 and NMOS transistors M14, M15, M16, M17, wherein the gates of the PMOS input pair PMOS transistors M10 and M11 are connected to the pre-amplifier stage output nodes DA and DB respectively, the drains are connected to the latch stage output nodes PLP and PLN respectively, and the sources are connected to the drains of the PMOS transistors M12 and M13 respectively; the sources of the PMOS transistors M12 and M13 are connected to the power supply VDD, and the gates are connected to the nodes PLN and PLP respectively; the sources of the NMOS transistors M14 and M15 are connected to the ground VSS, the gates are connected to the nodes PLN and PLP respectively, and the drains are connected to the nodes PLP and PLN respectively; the sources of the NMOS transistors M16 and M17 are connected to the ground VSS, the gates are connected to the clock signal CLKB, and the drains are connected to the nodes PLP and PLN respectively; The N-input latch stage includes NMOS transistors M18, M19, M20, and M21, and PMOS transistors M22, M23, M24, and M25; wherein, the gates of the NMOS input pair NMOS transistors M18 and M19 are respectively connected to the pre-amplifier stage output nodes DB and DA, the drains are respectively connected to the latch stage output nodes NLP and NLN, and the sources are respectively connected to the drains of M20 and M21; the sources of the NMOS transistors M20 and M21 are connected to the ground VSS, and the gates are respectively connected to the nodes NLN and NLP; the sources of the PMOS transistors M22 and M23 are connected to the power supply VDD, the gates are respectively connected to the nodes NLN and NLP, and the drains are respectively connected to the nodes NLP and NLN; the sources of the PMOS transistors M24 and M25 are connected to the power supply VDD, the gates are respectively connected to the clock signal CLKB, and the drains are respectively connected to the nodes NLP and NLN, and the inverted signals of NLP and NLN are respectively connected to the PLP and PLN through the OR gate to obtain the entire comparator outputs OUTP and OUTN.

2. A dual-clock edge comparison low-power dynamic comparator control method, applied to the dual-clock edge comparison low-power dynamic comparator as claimed in claim 1, characterized in that: include: The N input comparison stage starts from the rising edge of the clock signal CLK. In this stage, the NMOS input pair in the pre-amplifier stage leads the comparison process, and the PMOS input pair assists the comparison. CLK is at a high level, so that the PMOS transistors M9, M7, and M8 in the pre-amplifier stage are turned off, and the NMOS transistor M0 is turned on. The NMOS input pair and the NMOS transistors M1 and M2 are controlled by the input signals VIP and VIN respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is discharged from VDD through the latch decision level at different speeds, and finally discharged to VSS; The PMOS input pair M5 and M6 are controlled by the input signals VIN and VIP respectively, assisting the discharge process of the NMOS input pair; the small-size NMOS transistors M3 and M4 are turned on by CLK control to ensure that the nodes DA and DB are finally discharged to VSS; At this stage, CLKB is at a low level, so that the PMOS transistors M24 and M25 in the N-input latch stage are turned on, and the output terminals NLP and NLN are reset to the digital code "1 1"; at this stage, CLKB is at a low level, so that the NMOS transistors M16 and M17 in the P-input latch stage are turned off, and the PMOS input pair PMOS transistors M10 and M11 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of PMOS transistors M12 and M13 and NMOS transistors M14 and M15, so that the output terminals PLP and PLN of the P-input latch stage finally output the digital code "1 0" or "0 1".

3. The low power consumption dynamic comparator control method of dual clock edge comparison according to claim 2, characterized in that: Also includes: The P input comparison phase starts from the falling edge of the clock signal CLK. In this phase, the comparison process is dominated by the PMOS input pair in the pre-amplifier stage, and the NMOS input pair assists the comparison. CLK is at a low level, so that the NMOS transistors M0, M3, and M4 in the pre-amplifier stage are turned off, and the PMOS transistor M9 is turned on. The PMOS input pairs M5 and M6 are controlled by the input signals VIN and VIP respectively, so that the parasitic capacitance at the output nodes DA and DB of the pre-amplifier stage is charged from VSS to the latch decision level at different speeds, and finally charged to VDD. The NMOS input pair of NMOS transistors M1 and M2 are controlled by input signals VIP and VIN respectively, assisting the discharge process of the PMOS input pair; the small-size PMOS transistors M7 and M8 are turned on by CLK control to ensure that the nodes DA and DB are finally charged to VDD; At this stage, CLKB is at a high level, so that the NMOS transistors M16 and M17 in the P input latch stage are turned on, and the output terminals PLP and PLN are reset to the digital code "0 0"; at this stage, CLKB is at a high level, so that the PMOS transistors M24 and M25 in the N input latch stage are turned off, and the NMOS input pair NMOS transistors M18 and M19 detect the order in which the DA and DB nodes pass through the threshold voltage, and control the positive feedback cross-coupling pair composed of NMOS transistors M20 and M21 and PMOS transistors M22 and M23, so that the output terminals NLP and NLN of the N input latch stage finally output the digital code "0 1" or "1 0".

4. An electronic device, characterized in that: A low-power dynamic comparator with dual clock edge comparison as claimed in claim 1 is used.

5. A computer device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program implemented according to the method described in any one of claims 2 to 3, and the processor implements any one of the low-power dynamic comparator control methods for dual-clock edge comparison when executing the computer program.

6. A computer-readable storage medium, characterized in that: It stores a computer program implemented according to the method described in any one of claims 2 to 3 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

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