Automated connection verification method, device, terminal, medium and program product for chip interconnect manager

Abstract

The present application provides an automated connection verification method, device, terminal, medium and program product for a chip interconnection manager, the method comprising: obtaining a design form of a chip design to be verified; performing macro definition processing on the design form to generate a macro definition file for the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified; constructing a test case file according to the obtained target chip design verification requirements and the macro definition file; writing the HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running it, so that the verification platform can perform automated connection verification based on the interconnection manager on the chip design to be verified. The present application can automatically generate a corresponding macro definition file as the version of the chip design is updated, so as to automatically connect the modules inside the chip design during the verification process, making the verification process simple, efficient and intuitive.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an automated connection verification method, device, terminal, medium and program product for a chip interconnect manager. Background Art

[0002] When verifying the chip design, the modules inside the chip often need to be interconnected and work together. In the verification scheme of the prior art, manual configuration is generally used to connect each module one by one to verify the connection status and the correctness of the received and sent data. However, for chips with complex and cumbersome connections between internal modules and hundreds of connection ports, the use of manual configuration and one-by-one connection during verification will generate a huge workload, and it is difficult or impossible to cover all aspects, especially when multiple modules are sending and receiving data at the same time. In addition, with the update of the chip design version, the register configuration bits corresponding to different modules are changed to new positions or increased or decreased. Each time a new version is released, each module needs to be checked and changed in turn, and then the test cases and test platforms are manually changed. The verification work is complicated, cumbersome, time-consuming, labor-intensive, poorly readable and prone to errors. Summary of the invention

[0003] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide an automated connection verification method, device, terminal, medium and program product for a chip interconnect manager, which is used to solve the problem that the manual modification method during chip verification in the prior art makes the verification work complicated, tedious, time-consuming, labor-intensive, poorly readable and prone to errors.

[0004] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an automated connection verification method for a chip interconnection manager, comprising: obtaining a design table of a chip design to be verified; performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between modules connected through the interconnection manager within the chip design to be verified; constructing a test case file based on the obtained target chip design verification requirements and the macro definition file; writing a HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running it, so that the verification platform can perform automated connection verification on the chip design to be verified based on the interconnection manager.

[0005] In some embodiments of the first aspect of the present application, the design table is macro-defined to generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified, and the process includes: using a set separation identifier to separate the modules connected through the interconnection manager inside the chip design to be verified in the design table; determining multiple module input ports and multiple module output ports inside the chip design to be verified based on the port information of each module; and generating a macro definition file for describing the connection relationship between the modules inside the chip design to be verified through an automatic string generation method based on index values ​​based on the determined multiple module input ports and multiple module output ports.

[0006] In some embodiments of the first aspect of the present application, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values. The process includes: assigning values ​​to each module input port and each module output port according to the order of the ports in the design table to obtain the port index value of each module input port and each module output port; generating multiple macro definition strings for describing the connection relationship between the module ports according to the set string structure in the order of the port index values, thereby obtaining a macro definition file for describing the internal module connection relationship of the chip design to be verified.

[0007] In some embodiments of the first aspect of the present application, the string structure includes: a module input port name, a connection relationship identifier, and a module output port name.

[0008] In some embodiments of the first aspect of the present application, each macro definition string also carries corresponding register configuration information; wherein, when performing chip design verification, the corresponding ports are connected according to the register configuration information carried by each macro definition string.

[0009] In some embodiments of the first aspect of the present application, the method for obtaining the register configuration information corresponding to each macro-defined string includes: determining the access address of each macro-defined string based on the port index value of the module output port in each macro-defined string and the base address of the register; determining the port index value of the module input port in each macro-defined string as the configuration information of each macro-defined string; and outputting the access address and configuration information of each macro-defined string as the register configuration information corresponding to each macro-defined string.

[0010] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an automated connection verification device for a chip interconnection manager, including: an acquisition module, used to acquire a design table of a chip design to be verified; a macro definition module, connected to the acquisition module, used to perform macro definition processing on the design table, and generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager within the chip design to be verified; a test case construction module, connected to the macro definition module, used to construct a test case file based on the acquired target chip design verification requirements and the macro definition file; a verification module, connected to the test case construction module, used to write a HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and run it, so that the verification platform can perform automated connection verification on the chip design to be verified based on the interconnection manager.

[0011] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the automatic connection verification method for the chip interconnect manager is implemented.

[0012] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code is run on a computer, the computer implements the automated connection verification method for the chip interconnect manager.

[0013] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the automated connection verification method for the chip interconnect manager.

[0014] As described above, the method, device, terminal, medium and program product for automatic connection verification of a chip interconnect manager of the present application have the following beneficial effects:

[0015] This application can automatically generate corresponding macro definition files as the version of the chip design is updated, thereby automatically connecting the various modules within the chip design during the verification process, making the verification process simple, efficient and intuitive. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a flowchart of an automated connection verification method for a chip interconnect manager in one embodiment of the present application.

[0017] Figure 2Shown is a schematic diagram of the connection structure of a chip design and verification platform in one embodiment of the present application.

[0018] Figure 3 Shown is a structural schematic diagram of an automatic connection verification device for a chip interconnect manager in one embodiment of the present application.

[0019] Figure 4 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0021] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0022] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0023] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0024] The present application provides an automated connection verification method, device, terminal, medium and program product for a chip interconnection manager, the method comprising: obtaining a design form of a chip design to be verified; performing macro definition processing on the design form to generate a macro definition file for the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified; constructing a test case file according to the obtained target chip design verification requirements and the macro definition file; writing the HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running it, so that the verification platform can perform automated connection verification based on the interconnection manager on the chip design to be verified. The present application can automatically generate a corresponding macro definition file as the version of the chip design is updated, so as to automatically connect the modules inside the chip design during the verification process, making the verification process simple, efficient and intuitive.

[0025] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The flowchart of an automatic connection verification method for a chip interconnect manager in an embodiment of the present invention is shown. The automatic connection verification method for a chip interconnect manager in this embodiment mainly includes the following steps:

[0026] Step S101: Obtain a design spreadsheet of a chip design to be verified.

[0027] It should be noted that the design table is used to describe the modules in the chip design to be verified and the connection relationship between the modules.

[0028] In one embodiment, the design spreadsheet is in a .csv format.

[0029] Step S102: performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between the modules connected by the interconnection manager inside the chip design to be verified.

[0030] It should be noted that the interconnection manager supports multiple inputs and multiple outputs. These input and output ports can be assigned to the modules connected to the interconnection manager as their inputs or outputs. On this product, the input and output signals of multiple modules can be connected to each other, so that multiple modules can be used together. The interconnection manager can configure these connections.

[0031] In one embodiment, the design table is macro-defined to generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified. The process includes: using a set separation identifier to separate the modules connected through the interconnection manager inside the chip design to be verified in the design table; determining multiple module input ports and multiple module output ports inside the chip design to be verified based on the port information of each module; and generating a macro definition file for describing the connection relationship between the modules inside the chip design to be verified through an automatic string generation method based on index values ​​based on the determined multiple module input ports and multiple module output ports.

[0032] In one embodiment, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values. The process includes: assigning values ​​to each module input port and each module output port according to the order of the ports in the design table to obtain the port index value of each module input port and each module output port; generating multiple macro definition strings for describing the connection relationship between the module ports according to the set string structure in the order of the port index values, thereby obtaining a macro definition file for describing the internal module connection relationship of the chip design to be verified.

[0033] In a specific embodiment, the macro definition file is a file in .h format.

[0034] In one embodiment, the string structure includes: a module input port name, a connection relationship identifier, and a module output port name.

[0035] The following is a detailed explanation of the process of generating macro definition strings:

[0036] In the design table, the modules inside the chip design are separated by a set separator (the separator may be a comma, a semicolon, etc., which is not limited here).

[0037] Furthermore, the separated design table (in .csv format) is input into Python, and multiple module input ports and multiple module output ports are determined according to the port information of each module using Python language.

[0038] Furthermore, the split function in Python is used to split the determined multiple module input ports and multiple module output ports into two queues, namely queue 1 (queue1) and queue 2 (queue2).

[0039] It should be noted that the split() function is a built-in method of Python strings, which is used to split a string into multiple substrings according to the specified delimiter and store these substrings in a list. The basic syntax is as follows: str.split(str="",num=string.count(str))[n]. Where str is the delimiter, which defaults to all empty characters, including spaces, newlines (\n), tabs (\t), etc. num is the number of splits. If the parameter num exists, it will only be split into num+1 substrings, and each substring can be assigned to a new variable. The default is -1, which means to split all. [n]: means to select the nth slice.

[0040] Queue: In multithreaded programming, when multiple threads need to access shared data, race conditions can easily occur, that is, multiple threads try to access and modify the same data at the same time, resulting in inconsistent or lost data. A queue is a data structure used to solve this problem. It provides a thread-safe way to manage data, ensuring that multiple threads can safely access and modify it.

[0041] Furthermore, according to the order of the ports in the design table, each module input port and each module output port are assigned a value to obtain a port index value of each module input port and each module output port.

[0042] It should be noted that the port index values ​​of the ports have a sequence, and the sequence of the index values ​​reflects the connection sequence of the ports.

[0043] Furthermore, in the order of the port index values, multiple macro definition strings for describing the connection relationship between the module ports are generated according to the string structure of the module input port name, the connection relationship identifier symbol and the module output port name.

[0044] For example, the connection relationship identifier symbol is "__", the input port a1 of module A and the output port b2 of module B have a connection relationship, and the corresponding macro definition string is "a1__b2".

[0045] It should be noted that the present invention does not limit the connection relationship identification symbol, and those skilled in the art can set it according to actual needs.

[0046] Furthermore, using the write() function in the Python language, the multiple macro definition strings generated in the above steps are written into a blank .h file and saved to obtain a macro definition file for describing the internal module connection relationship of the chip design to be verified.

[0047] It should be noted that after opening a file in write mode, you can use the write() function to write data to the file. The parameter of the write() function is the data to be written to the file, and the data type can be a string or a byte stream.

[0048] In one embodiment, each macro definition string also carries corresponding register configuration information.

[0049] In one embodiment, a method for obtaining register configuration information corresponding to each macro definition string includes: determining an access address of each macro definition string based on a port index value of a module output port in each macro definition string and a base address of a register; determining a port index value of a module input port in each macro definition string as configuration information of each macro definition string; and outputting the access address and configuration information of each macro definition string as register configuration information corresponding to each macro definition string.

[0050] In a specific embodiment, the access address of each macro definition string is calculated by the following equation:

[0051] The access address of the macro definition string = the base address of the general register + 4 × the port index value of the module output port in the macro definition string;

[0052] Among them, the port index value of the module output port in the 4× macro definition string is the offset address of the register corresponding to the macro definition string.

[0053] Step S103: construct a test case file according to the acquired target chip design verification requirements and the macro definition file.

[0054] In a specific embodiment, the test case is used to verify the function of the internal module of the chip design to be verified. In the constructed test case file, the macro definition string in the macro definition file is used to define the connection relationship of the internal module of the chip design to be verified.

[0055] In a specific embodiment, the test case file is a file in .c format.

[0056] Step S104: writing a HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running the file, so that the verification platform can perform automatic connection verification on the chip design to be verified based on the interconnection manager.

[0057] It should be noted that HEX file is a hexadecimal encoded file format, mainly used to store and transmit binary data. Files in this format are very common in the fields of electronics and computer engineering, especially in firmware programming and embedded system development.

[0058] In one embodiment, if Figure 2 As shown, the obtained HEX file is written into the RAM of the chip design to run the HEX file through the RAM; through the HEX file running, the chip interconnect manager is used to automatically connect the ports of each module in the chip design.

[0059] In one embodiment, the automatic connection between the ports of each module in the chip design is performed by running a HEX file using a chip interconnect manager, including:

[0060] For each macro definition string in the HEX file, the corresponding register is accessed according to the access address in the register configuration information carried by the macro definition string. Then the configuration information in the register configuration information carried by the macro definition string is configured to the register to complete the connection between the module input port and the module output port corresponding to the macro definition string. This process is completed by the interconnection manager.

[0061] For example, for the macro definition string "a1__b2", the process of connecting the input port a1 of module A and the output port b2 of module B specifically includes: accessing the corresponding register through the access address in the register address information carried by the macro definition string "a1__b2". Then configuring the configuration information in the register address information carried by the macro definition string to the register, so as to complete the connection between the input port a1 and the output port b2 corresponding to the macro definition string "a1__b2".

[0062] It should be noted that in an embodiment of the present invention, since the connection configuration in the test case is replaced with a macro definition string, as the version is updated, the test case can be automatically updated to the latest connection configuration when performing chip design verification without the need to manually change the configuration.

[0063] In a specific embodiment, the interconnection manager may use an S32K3XX trigger MUX module. It should be noted that the present invention does not limit the model of the interconnection manager, and those skilled in the art may select it according to actual needs.

[0064] In a specific embodiment, if Figure 2 As shown, the verification platform is built using Verilog language or System Verilog language. The chip design is verified through the Driver and Monitor in the verification platform;

[0065] Among them, Driver is a test component used to simulate external signals or stimuli to test the hardware design. At the port of the module, the Driver is responsible for providing input signals, which can be fixed values, periodically changing signals, or complex waveforms dynamically generated according to test requirements. Drivers can be simple, providing only a few predefined values, or complex, capable of simulating various characteristics of signals in the real world. In Verilog, Driver can be implemented in the following ways: Use initial or always blocks to generate test vectors. Use parameterized or programmatic methods to dynamically change input signals. Combine with the #delay operator to control the timing of signal changes.

[0066] A monitor is a test component used to observe and record the behavior and response of a hardware design during testing. Monitors are usually connected to the output ports of a design, capturing changes in the output signal and comparing it with the expected results to verify the correctness of the design. In Verilog, monitors can be implemented in the following ways: Use initial or always blocks to observe output signals. Record changes in signals, which may involve writing data to a file or displaying it in a simulation environment. Use assertions to check whether the signal is as expected, such as using the $display or $monitor system tasks.

[0067] In chip design verification, drivers and monitors are often used together to create a complete test environment. The driver provides input signals, and the monitor observes the output response and verifies whether the design behaves as expected.

[0068] In one embodiment, errors and warnings in chip design can be quickly located through macro definition strings.

[0069] Figure 3 It is a schematic block diagram of an automatic connection verification device for a chip interconnect manager provided in an embodiment of the present application.

[0070] like Figure 3 As shown, the automatic connection verification device for the chip interconnect manager includes:

[0071] An acquisition module 31 is used to acquire a design table of a chip design to be verified;

[0072] A macro definition module 32, connected to the acquisition module 31, for performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between the modules connected by the interconnection manager inside the chip design to be verified;

[0073] A test case construction module 33, connected to the macro definition module 32, is used to construct a test case file according to the acquired target chip design verification requirements and the macro definition file;

[0074] The verification module 34 is connected to the test case construction module 33, and is used to write the HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and run it, so that the verification platform can perform automated connection verification on the chip design to be verified based on the interconnection manager.

[0075] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0076] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0077] In one embodiment, the design table is macro-defined to generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified. The process includes: using a set separation identifier to separate the modules connected through the interconnection manager inside the chip design to be verified in the design table; determining multiple module input ports and multiple module output ports inside the chip design to be verified based on the port information of each module; and generating a macro definition file for describing the connection relationship between the modules inside the chip design to be verified through an automatic string generation method based on index values ​​based on the determined multiple module input ports and multiple module output ports.

[0078] In one embodiment, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values. The process includes: assigning values ​​to each module input port and each module output port according to the order of the ports in the design table to obtain the port index value of each module input port and each module output port; generating multiple macro definition strings for describing the connection relationship between the module ports according to the set string structure in the order of the port index values, thereby obtaining a macro definition file for describing the internal module connection relationship of the chip design to be verified.

[0079] In one embodiment, the string structure includes: a module input port name, a connection relationship identifier, and a module output port name.

[0080] In one embodiment, each macro definition string also carries corresponding register configuration information; wherein, when performing chip design verification, the corresponding port is connected according to the register configuration information carried by each macro definition string.

[0081] In one embodiment, a method for obtaining register configuration information corresponding to each macro definition string includes: determining an access address of each macro definition string based on a port index value of a module output port in each macro definition string and a base address of a register; determining a port index value of a module input port in each macro definition string as configuration information of each macro definition string; and outputting the access address and configuration information of each macro definition string as register configuration information corresponding to each macro definition string.

[0082] Figure 4 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 4 As shown, the electronic terminal includes: at least one processor 401, a memory 402, at least one network interface 403 and a user interface 405. The various components in the device are coupled together through a bus system 404. It can be understood that the bus system 404 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 404 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 4 In the specification, various buses are labeled as bus systems.

[0083] The user interface 405 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0084] It is understood that the memory 402 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0085] The memory 402 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 400. Examples of these data include: any executable program used to operate on the electronic terminal 400, such as an operating system 4021 and an application 4022; the operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 4022 may include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The automatic connection verification method for the chip interconnect manager provided in the embodiment of the present invention may be included in the application 4022.

[0086] The automatic connection verification method for the chip interconnection manager disclosed in the above embodiment of the present invention can be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 401 or the instruction in the form of software. The above processor 401 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 401 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 401 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0087] In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0088] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes Figure 1 Automated connection verification for a chip interconnect manager in the illustrated embodiment.

[0089] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable storage medium, which stores a program code, and when the program code is run on a computer, the computer executes Figure 1 Automated connection verification for a chip interconnect manager in the illustrated embodiment.

[0090] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0091] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0093] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0094] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0096] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0097] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0098] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0099] In summary, the present application provides an automated connection verification method, device, terminal, medium and program product for a chip interconnection manager, the method comprising: obtaining a design form of a chip design to be verified; performing macro definition processing on the design form to generate a macro definition file for the connection relationship between the modules connected through the interconnection manager inside the chip design to be verified; constructing a test case file according to the obtained target chip design verification requirements and the macro definition file; writing the HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running it, so that the verification platform can perform automated connection verification based on the interconnection manager on the chip design to be verified. The present application can automatically generate a corresponding macro definition file as the version of the chip design is updated, thereby automatically connecting the modules inside the chip design during the verification process, making the verification process simple, efficient and intuitive.

[0100] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An automated connection verification method for a chip interconnect manager, characterized in that: include: Obtaining a design spreadsheet of a chip design to be verified; Performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between modules connected by the interconnection manager inside the chip design to be verified; The process of performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between modules connected by the interconnection manager inside the chip design to be verified includes: Using the set separation identifier, in the design table, separates the modules connected by the interconnection manager inside the chip design to be verified; Determine multiple module input ports and multiple module output ports within the chip design to be verified according to the port information of each module; According to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values; And wherein, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values, and the process includes: According to the order of the ports in the design table, each module input port and each module output port are assigned a value to obtain a port index value of each module input port and each module output port; According to the order of the port index values ​​and the set string structure, a plurality of macro definition strings for describing the connection relationship between the module ports are generated, thereby obtaining a macro definition file for describing the internal module connection relationship of the chip design to be verified; Constructing a test case file according to the obtained target chip design verification requirements and the macro definition file; A HEX file obtained by compiling the macro definition file and the test case file is written into the chip design to be verified and run, so that the verification platform can perform automated connection verification on the chip design to be verified based on the interconnection manager.

2. The automatic connection verification method for a chip interconnect manager according to claim 1, characterized in that: The character string structure includes: a module input port name, a connection relationship identifier, and a module output port name.

3. The automatic connection verification method for a chip interconnect manager according to claim 1, characterized in that: Each macro definition string also carries corresponding register configuration information; wherein, when performing chip design verification, the corresponding port is connected according to the register configuration information carried by each macro definition string.

4. The automatic connection verification method for a chip interconnect manager according to claim 3, characterized in that: The method for obtaining the register configuration information corresponding to each macro definition string includes: determining the access address of each macro definition string according to the port index value of the module output port in each macro definition string and the base address of the register; determining the port index value of the module input port in each macro definition string as the configuration information of each macro definition string; and outputting the access address and configuration information of each macro definition string as the register configuration information corresponding to each macro definition string.

5. An automatic connection verification device for a chip interconnect manager, characterized in that: include: An acquisition module, used for acquiring a design table of a chip design to be verified; A macro definition module, connected to the acquisition module, for performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between the modules connected by the interconnection manager inside the chip design to be verified; The process of performing macro definition processing on the design table to generate a macro definition file for describing the connection relationship between modules connected by the interconnection manager inside the chip design to be verified includes: Using the set separation identifier, in the design table, separates the modules connected by the interconnection manager inside the chip design to be verified; Determine multiple module input ports and multiple module output ports within the chip design to be verified according to the port information of each module; According to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values; And wherein, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the internal module connection relationship of the chip design to be verified is generated by an automatic string generation method based on index values, and the process includes: According to the order of the ports in the design table, each module input port and each module output port are assigned a value to obtain a port index value of each module input port and each module output port; According to the order of the port index values ​​and the set string structure, a plurality of macro definition strings for describing the connection relationship between the module ports are generated, thereby obtaining a macro definition file for describing the internal module connection relationship of the chip design to be verified; A test case construction module, connected to the macro definition module, is used to construct a test case file according to the acquired target chip design verification requirements and the macro definition file; A verification module is connected to the test case construction module, and is used to write a HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and run it, so that the verification platform can perform automated connection verification on the chip design to be verified based on the interconnection manager.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

7. A computer program product, characterized in that The computer program product includes a computer program code, and when the computer program code is executed on a computer, the computer is enabled to implement the method according to any one of claims 1 to 4.

8. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 4.

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