A system chip data interaction system and method

Abstract

The invention discloses a system chip data interaction system and method, belonging to the field of system chip design, using a CRC controller to check data received by a DMA controller, if the check result value is consistent with a preset check value stored in the CRC controller, the received data is transmitted to a target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends, and the CRC controller simultaneously notifies a processor core to process data received by the DMA controller that is inconsistent with the preset check value, after ensuring that there are no errors in the data in the storage body and on the transmission path, the data is transmitted to the target address through the DMA controller, and at the same time, it is ensured that no erroneous data has been transmitted to the target address by the DMA controller during the period when the CRC controller notifies the processor core. The invention does not require additional performance trade-offs, finds a time window for DMA to transport data, and improves data interaction reliability without affecting performance.

Description

Technical Field

[0001] The present invention belongs to the field of system chip design, and in particular relates to a system chip data interaction system and method. Background Art

[0002] Computer system chip data interaction refers to the data transmission and exchange process between chips within a system or between chips and external devices through specific communication protocols and interfaces. This interaction is a key link in realizing system functions and improving system performance. Computer system chip data interaction usually relies on multiple communication protocols, which are classified according to different data transmission methods, clock synchronization methods, and data flow directions.

[0003] There are many ways to implement data interaction between computer system chips, such as directly connecting chips or chips with external devices through wires or cables to achieve data transmission and communication. Or connect multiple chips or devices through a bus to achieve data sharing and communication. The bus can be an internal bus or an external bus. In more complex systems, data transmission and communication between chips or between chips and external devices may be carried out through the network. This usually requires the use of network communication protocols and interfaces to achieve this.

[0004] In the process of data transmission, in order to avoid excessive consumption of processor cores, computer system chips usually use DMA (Direct Memory Access) controllers for data transmission, copying data from one address space to another, and providing high-speed data transmission between peripherals and memories or between memories. During the system data transmission process, it is generally necessary to effectively verify the data transmitted by the system. However, when DMA moves data, the reliability of the moved data is difficult to guarantee due to the complex data sources, large data volume, long data paths and other reasons. Summary of the invention

[0005] The object of the present invention is to provide a system chip data interaction system and method to overcome the problem of poor reliability in the system chip data transmission process in the prior art.

[0006] A system chip data interaction system includes a DMA controller and a CRC controller connected to an interface of the DMA controller, wherein the DMA controller is connected to a processor core, peripherals and a storage body through a bus;

[0007] The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends. The CRC controller also notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value.

[0008] Preferably, the DMA controller is provided with a plurality of transmission channels, each transmission channel being capable of processing a DMA request from a different source.

[0009] Preferably, a FIFO structure is provided inside each transmission channel of the DMA controller, which is used as a temporary storage area before the source data is transmitted to the target address.

[0010] Preferably, the CRC controller includes multiple channels, and a CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is simultaneously transmitted to the CRC signature register. The CRC controller calculates the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register for judgment.

[0011] Preferably, the CRC controller further comprises a CRC interrupt generation logic module, a calibration timer, a calibration preload timer and a calibration module;

[0012] The check timer is used to compare the timing operation. When the check timer ends, the check result value calculated by the check module in the CRC controller is compared with the preset check value once;

[0013] The check timer is loaded with an initial value through the check preload timer. The check preload timer and the check timer are configured according to the time when the data on the DMA controller is transferred to the CRC value register and the CRC signature register. When the next check result value reaches the CRC value register, the check timer is reset to the initial value of the check preload timer.

[0014] The check module is used to check the data received by the DMA controller. When the check result value of the check module is inconsistent with the preset check value stored in the CRC value register, the CRC interrupt generation logic module initiates a check error interrupt, and the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends.

[0015] A system chip data interaction method comprises the following steps:

[0016] The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends. The CRC controller also notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value.

[0017] Preferably, multiple transmission channels of the DMA controller are utilized to perform DMA request processing, and each transmission channel is capable of processing a DMA request from a different source.

[0018] Preferably, a CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is simultaneously transmitted to the CRC signature register. The CRC controller calculates the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register for judgment.

[0019] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned system chip data interaction method when executing the computer program.

[0020] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the system chip data interaction method as described above is implemented.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects:

[0022] The present invention provides a system chip data interaction system, which utilizes a CRC controller to check data received by a DMA controller. If the check result value is consistent with a preset check value stored in the CRC controller, the received data is transmitted to a target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends, and the CRC controller simultaneously notifies a processor core to process data received by the DMA controller that is inconsistent with the preset check value, and after ensuring that there are no errors in the data in the storage body and on the transmission path, the data is transmitted to the target address through the DMA controller, and at the same time, it is ensured that no erroneous data has been transmitted to the target address by the DMA controller during the period when the CRC controller notifies the processor core. The present invention does not require additional performance trade-offs, and improves the reliability of data interaction without affecting performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the structure of the system chip data interaction system in an embodiment of the present invention.

[0024] Figure 2 FIG. 4 is a structural diagram of a DMA controller in an embodiment of the present invention.

[0025] Figure 3 Schematic diagram of the CRC controller in an embodiment of the present invention.

[0026] Figure 4 This is an architecture diagram for improving data interaction reliability in normal mode in an embodiment of the present invention.

[0027] Figure 5 This is a flow chart of improving data interaction reliability in normal mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] like Figure 1 As shown, the present invention provides a system chip data interaction system, including a DMA controller and a CRC controller (Cyclic Redundancy Check Controller) connected to an interface of the DMA controller, wherein the DMA controller is connected to a processor core, a peripheral device and a storage body through a bus;

[0031] The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends, and the CRC controller simultaneously notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value, that is, the processor core processing error; the present invention uses the CRC controller to check the data on the interface of the DMA controller to realize the whole-chip data interaction process, ensures that there are no errors in the data in the storage body and on the transmission path, and then transmits it to the target address through the DMA controller, and at the same time ensures that the erroneous data has not been transmitted to the target address by the DMA controller during the period when the CRC controller notifies the processor core, thereby improving the reliability of data interaction.

[0032] When the CRC controller checks the data received by the DMA controller and the check result value is inconsistent with the preset check value stored in the CRC controller, the check result on the CRC controller shows that the data is wrong.

[0033] The DMA controller is used to complete the whole-chip data interaction process and realize data read and write transmission. The whole-chip data interaction includes data transmission from storage to peripherals, from peripherals to storage, and from storage to storage.

[0034] The CRC controller is integrated on the interface of the DMA controller, and the CRC controller can analyze the data received on the interface of the DMA controller. The CRC controller automatically checks the data received on the interface of the DMA controller without intervention of the processor core.

[0035] The DMA controller has multiple transmission channels. The DMA controller supports multiple DMA requests. Each transmission channel can process a DMA request from a different source. Multiple transmission channels can simultaneously support the transmission of multiple data streams with different data lengths, source addresses, and destination addresses.

[0036] Each transmission channel of the DMA controller has a FIFO structure (First In First Out structure) inside, which is used as a temporary storage area before the source data is transferred to the target address; the FIFO structure can be configured as FIFO mode (First In First Out mode) or direct mode. In FIFO mode, data transmission is triggered when the data in the FIFO structure reaches the FIFO set threshold; in direct mode, the transmission of the storage data is directly started.

[0037] When the CRC controller reads the data received by the DMA controller, it obtains a signature representing the content of the data. The CRC controller verifies the integrity of the data transmitted on the DMA controller through checksum calculation.

[0038] In a specific implementation of the present application, the CRC controller can implement multi-channel parallel encoding and decoding, and can be configured to perform calculations on data sizes of 8, 16, 32, or 64 according to the bit width of the interface data bus of the DMA controller.

[0039] The CRC controller includes multiple channels. A CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is also transmitted to the CRC signature register of the CRC controller. The CRC controller starts to calculate the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register.

[0040] Among the multiple CRC value registers, each CRC value register is preset to store a preset check value corresponding to the current transmission data of the DMA controller.

[0041] like Figure 2 As shown in the figure, the control registers in the DMA controller are set through the bus slave programming interface on the DMA controller to configure the DMA controller; the bus host port on the DMA controller is used to access the storage and peripherals; the arbiter in the DMA controller is used to manage the priority of each data stream. A FIFO structure is set inside each transmission channel in the DMA controller as a temporary storage area before the source data is transferred to the target address.

[0042] like Figure 3 As shown, the CRC controller includes a CRC value register, a CRC signature register, a CRC interrupt generation logic module, a DMA logic request module, a data counter, a check timer, a check preload timer, a check module and a check value sending threshold configuration module; the check module can configure the check calculation of 32 bit, 64 bit, and 128 bit data sizes. The selection of the calculation polynomial should be consistent with the polynomial used for the preset check value in the CRC value register. The check timer is used to compare the timing operation. When the check timer ends, the check result value calculated by the check module in the CRC controller is compared with the preset check value once. The check timer loads the initial value through the check preload timer, configures the check preload timer and the check timer according to the time when the data on the DMA controller is transferred to the CRC value register and the CRC signature register, and when the next check result value reaches the CRC value register, the check timer is reset to the initial value of the check preload timer.

[0043] When the check result value of the check module is inconsistent with the preset check value stored in the CRC value register, the CRC interrupt generation logic module initiates a check error interrupt, and the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends; in addition, when the CRC value register has finished timing the check timer, and no new preset check value has arrived and is stored in the CRC value register, a check timeout interrupt is initiated to ensure the consistency of the checked data and the preset check value. Each CRC channel that can be calculated in parallel can initiate a check error interrupt and a check timeout interrupt.

[0044] The data counter and the check value sending threshold configuration module determine how many check result values ​​in the CRC value register are sent to the target address. When data transmission starts, the data counter is reset to 0. Every time the check timer is reset, the value of the data counter is increased by 1, and the check result value of one data is stored in a CRC value register. When the data counter counts to the check result value sending threshold, the check result value sending DMA request is generated through the DMA logic request module, and the check result value sending threshold and the check result value are sent to the target address. The check result value sending threshold is configured to be equal to the FIFO setting threshold in a channel of the DMA controller. For example, the check result value sending threshold of the CRC controller and the FIFO setting threshold of a channel of the DMA controller are both configured to 4, then a check result value sending DMA request of the CRC controller will have 4 data and 4 check result values ​​corresponding to the 4 data transmitted to their respective target addresses.

[0045] In a specific implementation of the present application, the CRC controller is set to four working modes, including normal mode, coding mode 1 only, coding mode 2 only and no working mode.

[0046] In normal mode, comparison verification is performed, and the DMA logic request module of the CRC controller generates a preset check value DMA request and a check result value to send a DMA request;

[0047] In the encoding-only mode 1, comparison verification is performed and only a preset checksum value DMA request is generated, which is suitable for transmission from the storage body to the peripheral device.

[0048] In encoding-only mode 2, no comparison and verification is performed, only the check result value is generated to send a DMA request, which is applicable to the first calculation of the check result value of the data, and the check result value is stored in the target address. When the data is transmitted for the second time, the CRC controller is configured to normal mode, and the check result value calculated for the first time is used as the preset check value to ensure that the data does not change between the two transmissions, thereby improving the reliability of data interaction. In encoding-only mode 2, since there is no predetermined preset check value, the check result value calculated by the CRC controller will be directly stored in the address mapping of the CRC value register.

[0049] In the specific implementation of the present application, a three-channel DMA controller is taken as an example for explanation. Figure 4 As shown, after the processor core configures the DMA controllers of the three channels, the comparison and verification are automatically performed without the participation of the processor core. In the embodiment, the DMA channel 1 of the DMA controller is used to transmit the enhanced data. When the data passes through the DMA controller, it is captured by the CRC controller and placed in the CRC signature register for verification and calculation of the verification result value; the DMA channel 2 of the DMA controller is used to transmit the preset verification value to the CRC value register for comparison and verification; the DMA channel 3 of the DMA controller is used to transmit the verification result value confirmed to be correct after comparison to the target address as the preset verification value predetermined for the next transmission; if an error occurs in the comparison, it means that the data has been changed, and the DMA controller is notified immediately.

[0050] like Figure 5As shown, in a specific implementation of the present application, the CRC controller protects the reliability of data interaction in normal mode. After resetting the CRC controller and initializing the DMA controller, the DMA requests of the three channels are configured. The functions of the three DMA channels of the DMA controller are as described above. DMA channel 1 is configured as required; DMA channel 2 sets the source address to the starting address of the check result value sent by the CRC controller last time, sets the target address to the address mapping of the first CRC value register, and sets the source address addressing mode to the incremental addressing mode. The incremental size is determined according to the data bit width of the DMA controller interface. The target address addressing mode is set to a fixed addressing mode or a loopback addressing mode according to the FIFO setting threshold on a channel of the DMA controller and the check result value sending threshold. When the check result value sending threshold is 1, the DMA controller is in direct mode. The CRC controller sends a DMA request for the check result value generated every time it compares a data. At this time, the target address addressing mode needs to be set to a fixed addressing mode. When the threshold is not set to 1, the target address addressing mode is set to loop addressing mode, and the loop size is determined according to the threshold setting size; DMA channel 3 sets the source address to the address mapping of the first CRC value register, sets the target address to the starting address where the preset checksum value is to be placed, and the source address addressing mode is set to fixed addressing mode or loop addressing mode.

[0051] After the CRC controller is initialized and the three DMA channels of the DMA controller are configured, the data of DMA channel 1 and the preset checksum value of DMA channel 2 begin to be transmitted. The data arrives at the CRC signature register, and the corresponding preset checksum value arrives at the CRC value register. If the checksum comparison result is correct, a DMA channel 3 request is initiated to send the checksum result value to the target address. If the checksum comparison result is wrong, a checksum error interrupt signal is generated to the DMA controller, and an interrupt is initiated to notify the processor core to handle the error.

[0052] The above is a specific implementation method proposed by the present invention for improving the reliability of data interaction of the system chip. Without affecting the performance, the reliability of data interaction is improved, and it has the advantages of simple structure and strong universality, which can improve the competitiveness of the product.

[0053] In a specific embodiment of the present invention, a system chip data interaction method is provided, comprising the following steps:

[0054] The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller; otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends. The CRC controller also notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value.

[0055] Preferably, multiple transmission channels of a DMA controller are used to perform DMA request processing, the DMA controller supports multiple DMA requests, and each transmission channel can process a DMA request from a different source.

[0056] Preferably, a CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is simultaneously transmitted to the CRC signature register. The CRC controller calculates the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register for judgment.

[0057] In another embodiment of the present invention, a terminal device is provided, the terminal device includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor specifically adopts a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the system chip data interaction method.

[0058] In another embodiment of the present invention, the present invention further provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory (Random Access Memory, i.e., random access memory) or a non-volatile memory (non-volatile memory), such as at least one disk memory. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the system chip data interaction method in the above embodiment.

[0059] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, read-only optical disk, optical storage, etc.) containing computer-usable program codes.

[0060] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0061] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0062] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A system chip data interaction system, characterized in that: It includes a DMA controller and a CRC controller connected to an interface of the DMA controller, wherein the DMA controller is connected to a processor core, peripherals and a storage body through a bus; The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller; Otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends, and the CRC controller also notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value; The CRC controller includes multiple channels, and a CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is simultaneously transmitted to the CRC signature register. The CRC controller calculates the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register for judgment; The CRC controller also includes a CRC interrupt generation logic module, a check timer, a check preload timer and a check module; The check timer is used to compare the timing operation. When the check timer ends, the check result value calculated by the check module in the CRC controller is compared with the preset check value once; The check timer is loaded with an initial value through the check preload timer. The check preload timer and the check timer are configured according to the time when the data on the DMA controller is transferred to the CRC value register and the CRC signature register. When the next check result value reaches the CRC value register, the check timer is reset to the initial value of the check preload timer. The check module is used to check the data received by the DMA controller. When the check result value of the check module is inconsistent with the preset check value stored in the CRC value register, the CRC interrupt generation logic module initiates a check error interrupt, and the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends.

2. A system chip data interaction system according to claim 1, characterized in that: The DMA controller has multiple transfer channels, each of which can handle a DMA request from a different source.

3. A system chip data interaction system according to claim 2, characterized in that: A FIFO structure is set inside each transmission channel of the DMA controller, which is used as a temporary storage area before the source data is transferred to the target address.

4. A system chip data interaction method, characterized in that: The following steps are involved: The CRC controller is used to check the data received by the DMA controller. If the check result value is consistent with the preset check value stored in the CRC controller, the received data is transmitted to the target address through the DMA controller. Otherwise, the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends, and the CRC controller also notifies the processor core to process the data received by the DMA controller that is inconsistent with the preset check value; The CRC controller also includes a CRC interrupt generation logic module, a calibration timer, a calibration preload timer and a calibration module; The check timer is used to compare the timing operation. When the check timer ends, the check result value calculated by the check module in the CRC controller is compared with the preset check value once; The check timer is loaded with an initial value through the check preload timer. The check preload timer and the check timer are configured according to the time when the data on the DMA controller is transferred to the CRC value register and the CRC signature register. When the next check result value reaches the CRC value register, the check timer is reset to the initial value of the check preload timer. The check module is used to check the data received by the DMA controller. When the check result value of the check module is inconsistent with the preset check value stored in the CRC value register, the CRC interrupt generation logic module initiates a check error interrupt, and the CRC controller notifies the DMA controller to release the bus after the current bus cycle ends.

5. A system chip data interaction method according to claim 4, characterized in that: The DMA request processing is performed using multiple transmission channels of the DMA controller, and each transmission channel can process a DMA request from a different source.

6. A system chip data interaction method according to claim 5, characterized in that: A CRC signature register and multiple CRC value registers are set in each channel of the CRC controller. When the DMA controller transmits data, the data transmitted to the DMA controller is also transmitted to the CRC signature register. The CRC controller calculates the check result value of the data in the CRC signature register. After the single-cycle calculation is completed, the calculated check result value is compared with the preset check value in the CRC value register.

7. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the system chip data interaction method as claimed in any one of claims 4 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the system chip data interaction method according to any one of claims 4 to 5 is implemented.

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