Semiconductor power device and method of manufacturing the same

Abstract

The application provides a semiconductor power device and a preparation method thereof. The semiconductor power device comprises: a plurality of spaced first doped layers, the first doped layers are located in the drift layer on both sides of the gate structure along a first direction and on one side of the well region towards the semiconductor substrate layer, the first doped layers are in contact with the well region and spaced from the gate structure, the doping type of the first doped layers is opposite to the doping type of the drift layer; wherein the spacing distance between the first doped layer and the semiconductor substrate layer is less than the spacing distance between the gate structure and the semiconductor substrate layer, and the width dimension of the one side surface of the first doped layer towards the semiconductor substrate layer along the first direction is greater than or equal to the width dimension of the one side surface of the first doped layer away from the semiconductor substrate layer along the first direction. The semiconductor power device improves the electric field concentration of the bottom region of the gate structure in the reverse blocking state.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor power device and its fabrication method. Background Technology

[0002] Power semiconductor devices are core components for power conversion and circuit control in power electronic devices. With the development of industries such as new energy vehicles, photovoltaics, rail transit, and smart grids in recent years, the market demand for power devices has rapidly increased. Third-generation semiconductor SiC materials have significant advantages in bandgap width, thermal conductivity, critical breakdown field strength, and electron saturation drift velocity, which aligns with the future development trend of power electronic systems towards miniaturization, lightweight design, high efficiency, integration, safety, and reliability.

[0003] As planar SiC MOSFET technology continues to iterate, its ability to reduce cell size is gradually approaching its limit. In contrast, trench SiC MOSFETs, with their inherent advantages such as smaller cell size and higher channel density, are destined to be the development trend of next-generation SiC power devices. For trench SiC MOSFETs, the electric field concentration at the bottom gate oxide in the reverse blocking state is a key issue restricting their performance and reliability. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to improve the electric field concentration in the bottom region of the gate structure of a semiconductor power device under reverse blocking state.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in a portion of the drift layer; well regions located in the drift layers on both sides of the gate structure along a first direction, wherein the conductivity type of the well regions is opposite to that of the drift layers; and a plurality of spaced first doped layers, wherein the first doped layers are located in the drift layers on both sides of the gate structure along the first direction and are located on the side of the well regions facing the semiconductor substrate layer, wherein the first doped layers are in contact with the well regions and spaced from the gate structure, and the doping type of the first doped layers is opposite to that of the drift layers; wherein the spacing distance between the first doped layers and the semiconductor substrate layer is less than the spacing distance between the gate structure and the semiconductor substrate layer, and the width dimension of the surface of the first doped layer facing the semiconductor substrate layer along the first direction is greater than or equal to the width dimension of the surface of the first doped layer facing away from the semiconductor substrate layer along the first direction.

[0006] Optionally, the width dimension of the first doped layer increases in the direction from the side of the first doped layer away from the semiconductor substrate to the side of the first doped layer facing the semiconductor substrate.

[0007] Optionally, the doping concentration of the first doped layer is less than the doping concentration of the well region.

[0008] Optionally, the doping concentration of the first doped layer is 1 / 10 to 1 / 2 of the doping concentration of the well region.

[0009] Optionally, the first doped layer extends to a portion of the gate structure facing the semiconductor substrate; or, the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate have no overlapping area, the second direction being perpendicular to the surface of the semiconductor substrate.

[0010] Optionally, the first doped layer extends to the side of the gate structure facing the semiconductor substrate, and the width of the overlapping region of the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate along the first direction is less than or equal to 0.5 micrometers.

[0011] Optionally, the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate have no overlapping area, and the distance between the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate along the first direction is less than or equal to 0.5 micrometers.

[0012] Optionally, the distance between the side surface of the first doped layer facing the semiconductor substrate and the side surface of the gate structure facing the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate is 0.3 micrometers to 3 micrometers.

[0013] Optionally, the doping concentration of the first doped layer is greater than the doping concentration of the drift layer.

[0014] Optionally, the doping concentration of the first doped layer is 2 to 10 times that of the doping concentration of the drift layer.

[0015] Optionally, it further includes: a second doped layer located on the side of the gate structure facing the semiconductor substrate and in contact with the gate structure, wherein the doping type of the second doped layer is the same as the doping type of the drift layer, and the doping concentration of the second doped layer is greater than the doping concentration of the drift layer; wherein the spacing between the first doped layer and the semiconductor substrate is less than the spacing between the second doped layer and the semiconductor substrate.

[0016] Optionally, the doping concentration of the second doped layer is 2 to 10 times that of the doping concentration of the drift layer.

[0017] Optionally, the thickness of the second doped layer is 0.1 micrometer to 1 micrometer.

[0018] The present invention also provides a method for fabricating a semiconductor power device, comprising: forming a drift layer, a plurality of first well regions spaced along a first direction, and a plurality of first doped layers spaced along the first direction on one side of a semiconductor substrate; the well regions are located in a portion of the drift layer, and the conductivity type of the well regions is opposite to that of the drift layer; the first doped layer is located in the drift layer on the side of the well regions facing the semiconductor substrate, the first doped layer is in contact with the well regions, and the doping type of the first doped layer is opposite to that of the drift layer; forming a gate structure, the gate structure being located in the drift layer between adjacent well regions and between adjacent first doped layers, the gate structure being spaced from the first doped layer; wherein the spacing distance between the first doped layer and the semiconductor substrate is less than the spacing distance between the gate structure and the semiconductor substrate, and the width dimension of the side surface of the first doped layer facing the semiconductor substrate along the first direction is greater than or equal to the width dimension of the side surface of the first doped layer away from the semiconductor substrate along the first direction.

[0019] Optionally, forming the plurality of first doped layers and the plurality of well regions includes: after forming the drift layer on one side of the semiconductor substrate, forming a first initial doped layer in the drift layer, the doping type of the first initial doped layer being opposite to the doping type of the drift layer, the first initial doped layer including a first region and a second region located on both sides of the first region along a first direction; performing ion implantation on the first region of the first initial doped layer such that the conductivity type of the first region is opposite to the conductivity type of the second region; after performing ion implantation on the first region of the first initial doped layer, forming the well regions in a portion of the second region and a portion of the first region, wherein the first doped layer is formed in the second region facing the semiconductor substrate.

[0020] Optionally, the process of forming the first initial doped layer in the drift layer includes an ion implantation process.

[0021] Optionally, forming the drift layer, the plurality of first doped layers, and the plurality of well regions includes: forming a first sub-drift layer on one side of the semiconductor substrate; epitaxially forming a second sub-drift layer on the side of the first sub-drift layer opposite to the semiconductor substrate, the second sub-drift layer having a doping type opposite to that of the first sub-drift layer, the second sub-drift layer including a third region and a fourth region located on both sides of the third region along a first direction; performing ion implantation on the third region of the second sub-drift layer such that the conductivity type of the third region is opposite to that of the fourth region and the same as that of the first sub-drift layer; after performing ion implantation on the third region of the second sub-drift layer, forming the well regions in a portion of the fourth region and a portion of the third region, wherein the first doped layer is formed in the fourth region facing the semiconductor substrate.

[0022] Optionally, forming the gate structure includes: forming a gate trench located in a drift layer between adjacent well regions and between adjacent first doped layers; and forming the gate structure in the gate trench.

[0023] Optionally, the method for fabricating the semiconductor power device further includes: forming a second doped layer in the drift layer at the bottom of the gate trench before forming the gate structure in the gate trench; wherein the second doped layer is in contact with the gate structure, the doping type of the second doped layer is the same as the doping type of the drift layer, and the doping concentration of the second doped layer is greater than the doping concentration of the drift layer; wherein the spacing distance between the first doped layer and the semiconductor substrate is less than the spacing distance between the second doped layer and the semiconductor substrate.

[0024] The technical solution of this invention has the following technical effects:

[0025] The semiconductor power device provided by this invention comprises multiple spaced first doped layers. Each first doped layer is located within a drift layer on the side of the well region facing the semiconductor substrate. The first doped layer is in contact with the well region, and the doping type of the first doped layer is opposite to that of the drift layer. The spacing between the first doped layer and the semiconductor substrate is less than the spacing between the gate structure and the semiconductor substrate. During reverse blocking (e.g., the gate structure is turned off and the drain voltage is greater than the source voltage), the PN junction formed by the first doped layer and the drift layer is depleted, and the electric field peak shifts to the boundary between the first doped layer and the drift layer. The width of the surface of the first doped layer facing the semiconductor substrate is greater than or equal to the width of the surface of the first doped layer facing away from the semiconductor substrate. During reverse blocking, the depletion layer at the corner between the bottom surface and the sidewall of one adjacent first doped layer and the depletion layer at the corner between the bottom surface and the sidewall of another first doped layer easily connect together, effectively pinching off the current. In summary, improving the electric field concentration in the bottom region of the gate structure of semiconductor power devices under reverse blocking conditions protects the gate dielectric layer in the gate structure. Due to the increased protection of the gate dielectric layer, the reverse breakdown voltage is improved.

[0026] Furthermore, the semiconductor power device also includes a second doped layer located on the side of the gate structure facing the semiconductor substrate and in contact with the gate structure. The doping type of the second doped layer is the same as that of the drift layer. When the semiconductor power device is forward-biased, charge carriers pass through the second doped layer. Because the doping concentration of the second doped layer is greater than that of the drift layer, the forward conduction resistance is reduced. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a semiconductor power device provided in an embodiment of the present invention;

[0029] Figures 2 to 4 This is a schematic diagram of the semiconductor power device fabrication process provided in an embodiment of the present invention. Detailed Implementation

[0030] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] One embodiment of the present invention provides a semiconductor power device, with reference to... Figure 1 ,include:

[0035] Semiconductor substrate layer 100;

[0036] A drift layer 110 located on one side of the semiconductor substrate layer 100;

[0037] Gate structure 130 is located in a portion of the drift layer 110;

[0038] Well regions 150 are located in the drift layers 110 on both sides of the gate structure 130 along the first direction X, and the conductivity type of the well regions 150 is opposite to that of the drift layers 110.

[0039] Multiple spaced first doped layers 120 are located in the drift layers 110 on both sides of the gate structure 130 along the first direction X and on the side of the well region 150 facing the semiconductor substrate layer 100. The first doped layers 120 are in contact with the well region 150 and spaced from the gate structure 130. The doping type of the first doped layers 120 is opposite to that of the drift layers 110.

[0040] Wherein, the spacing between the first doped layer 120 and the semiconductor substrate 100 is less than the spacing between the gate structure 130 and the semiconductor substrate 100, and the width dimension of the side surface of the first doped layer 120 facing the semiconductor substrate 100 along the first direction X is greater than or equal to the width dimension of the side surface of the first doped layer 120 away from the semiconductor substrate 100 along the first direction X.

[0041] Figure 1 As an example, the width dimension of the side surface of the first doped layer 120 facing the semiconductor substrate 100 along the first direction X is greater than the width dimension of the side surface of the first doped layer 120 away from the semiconductor substrate 100 along the first direction X.

[0042] In other embodiments, the width of the side surface of the first doped layer facing the semiconductor substrate along the first direction X is equal to the width of the side surface of the first doped layer away from the semiconductor substrate along the first direction.

[0043] The gate structure 130 includes a gate dielectric layer 131 and a gate electrode layer 132.

[0044] In this embodiment, the spacing between the first doped layer 120 and the semiconductor substrate 100 is smaller than the spacing between the gate structure 130 and the semiconductor substrate 100. During reverse blocking (e.g., the gate structure 130 is turned off and the drain voltage is greater than the source voltage), the PN junction formed by the first doped layer 120 and the drift layer 110 is depleted, and the electric field peak shifts to the boundary between the first doped layer 120 and the drift layer 110. The width of the side surface of the first doped layer 120 facing the semiconductor substrate 100 is greater than or equal to the width of the side surface of the first doped layer 120 away from the semiconductor substrate 100. During reverse blocking, the depletion layer at the corner between the bottom surface and the sidewall of one first doped layer 120 and the depletion layer at the corner between the bottom surface and the sidewall of another first doped layer 120 can easily connect together, thus pinching off the current. In summary, improving the electric field concentration in the bottom region of the gate structure of semiconductor power devices under reverse blocking conditions protects the gate dielectric layer in the gate structure. Due to the increased protection of the gate dielectric layer, the reverse breakdown voltage is improved.

[0045] Preferably, when the width of the side surface of the first doped layer 120 facing the semiconductor substrate 100 is greater than the width of the side surface of the first doped layer 120 away from the semiconductor substrate 100, during the reverse blocking process, the depletion layer at the corner between the bottom surface and the sidewall of one first doped layer 120 and the depletion layer at the corner between the bottom surface and the sidewall of the other first doped layer 120 are more likely to connect together.

[0046] In this embodiment, next-generation SiC-based semiconductor power devices, represented by SiC, exhibit higher reverse breakdown voltage, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate 100 are N-type ions. In other embodiments, the conductivity type of the semiconductor substrate 100 is not limited.

[0047] In one embodiment, the drift layer 110 has the same conductivity type as the semiconductor substrate 100, and the doping concentration of the drift layer 110 is lower than that of the semiconductor substrate 100. In one embodiment, the drift layer is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0048] The first direction X is parallel to the surface of the semiconductor substrate 100.

[0049] In this embodiment, the well region 150 is in contact with the sidewall of the gate structure 130.

[0050] In this embodiment, the semiconductor power device further includes: a first source region 160 located in the well region 150, the conductivity type of the first source region 160 being opposite to that of the well region 150, and the first source region 160 being in contact with the sidewall of the gate structure 130.

[0051] In this embodiment, when the drift layer 110 has an N-type conductivity, the well region 150 has a P-type conductivity. In this embodiment, when the well region 150 has a P-type conductivity, the first source region 160 has an N-type conductivity.

[0052] In this embodiment, the semiconductor power device further includes a second source region 170 located in the well region 150, the conductivity type of the second source region 170 being opposite to that of the first source region 160. The second source region 170 is located on the side of the first source region 160 opposite to the gate structure 130 along the first direction X.

[0053] In one embodiment, the orthographic projection of the gate structure 130 onto the surface of the semiconductor substrate is elongated. The width direction of the gate structure 130 is parallel to the first direction X.

[0054] The gate structure 130 is located between adjacent well regions 150 and adjacent first doped layer 120.

[0055] In this embodiment, a drain 101 is also included, located on the side surface of the semiconductor substrate 100 facing away from the drift layer 110. The material of the drain 101 includes metal.

[0056] In one embodiment, the dimension of the surface of the first doped layer 120 facing away from the semiconductor substrate 100 along the first direction X is smaller than the dimension of the surface of the well region 150 facing the semiconductor substrate 100 along the width direction of the gate structure 130.

[0057] The spacing between the first doped layer 120 and the semiconductor substrate 100 is less than the spacing between the gate structure 130 and the semiconductor substrate 100. The spacing between the first doped layer 120 and the semiconductor substrate 100 along the second direction Y is less than the spacing between the gate structure 130 and the semiconductor substrate 100 along the second direction Y. The spacing between the first doped layer 120 and the semiconductor substrate 100 refers to the spacing along the second direction Y between the surface of the first doped layer 120 facing the semiconductor substrate 100 and the surface of the semiconductor substrate 100 facing the drift layer 110. The spacing between the gate structure 130 and the semiconductor substrate 100 refers to the spacing along the second direction Y between the surface of the gate structure 130 facing the semiconductor substrate 100 and the surface of the semiconductor substrate 100 facing the drift layer 110.

[0058] In one embodiment, the second direction Y is perpendicular to the first direction X and to the surface of the semiconductor substrate 100.

[0059] The gate structure 130 includes a gate dielectric layer 131 and a gate electrode layer 132. The gate dielectric layer 131 surrounds the surface of the gate electrode layer 132 facing the semiconductor substrate layer 100 (that is, the bottom surface of the gate electrode layer 132) and the sidewalls of the gate electrode layer 132.

[0060] In one embodiment, the gate dielectric layer 131 is made of silicon oxide, and the gate electrode layer 132 is made of polycrystalline silicon.

[0061] In one embodiment, the doping concentration of the first doped layer 120 is less than the doping concentration of the well region 150. Further, the doping concentration of the first doped layer 120 is 1 / 10 to 1 / 2 of the doping concentration of the well region 150.

[0062] In one embodiment, the width of the first doped layer 120 increases in the first direction X along the direction from the side of the first doped layer 120 away from the semiconductor substrate 100 to the side of the first doped layer 120 facing the semiconductor substrate 100. This results in more holes in the first doped layer 120 and depletion of electrons in the drift layer 110 on the sides and bottom of the gate structure 130, further improving the electric field concentration in the bottom region of the gate structure 130 in the reverse blocking state of the semiconductor power device.

[0063] The direction along the side of the first doped layer 120 away from the semiconductor substrate 100 to the side of the first doped layer 120 facing the semiconductor substrate 100 is parallel to the second direction Y.

[0064] In one embodiment, the first doped layer 120 extends to a portion of the gate structure 130 facing the semiconductor substrate 100, and the orthographic projection of the first doped layer 120 along the second direction Y onto the surface of the semiconductor substrate 100 partially coincides with the orthographic projection of the gate structure 130 along the second direction Y onto the surface of the semiconductor substrate 100. This promotes the degree to which the depletion layers at the corner between the bottom surface and the sidewall of one first doped layer and the depletion layers at the corner between the bottom surface and the sidewall of another adjacent first doped layer are connected together.

[0065] Furthermore, the first doped layer 120 extends to the side of the gate structure 130 facing the semiconductor substrate 100. The width of the overlapping region of the orthographic projection of the bottom surface of the first doped layer 120 along the second direction Y onto the surface of the semiconductor substrate 100 and the orthographic projection of the bottom surface of the gate structure 130 along the second direction Y onto the surface of the semiconductor substrate 100 along the first direction X is less than or equal to 0.5 micrometers. For example, the width of the overlapping region along the first direction X is 0.5 micrometers, 0.4 micrometers, 0.3 micrometers, 0.2 micrometers, 0.1 micrometers, or 0.05 micrometers.

[0066] In another embodiment, the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate have no overlapping area. Further, the distance along the first direction between the orthographic projection of the bottom surface of the first doped layer along the second direction onto the surface of the semiconductor substrate and the orthographic projection of the bottom surface of the gate structure along the second direction onto the surface of the semiconductor substrate is less than or equal to 0.5 micrometers, for example, this distance is 0.5 micrometers, 0.4 micrometers, 0.3 micrometers, 0.2 micrometers, 0.1 micrometers, or 0.05 micrometers.

[0067] The first doped layer 120 is spaced apart from the gate structure 130, and the sidewalls of the first doped layer 120 and the gate structure 130 are spaced apart, so that when the semiconductor power device is forward-biased, the majority carriers in the first source region 160 can be transmitted through the space between the first doped layer 120 and the gate structure 130.

[0068] In one embodiment, the spacing between the side surface of the first doped layer 120 facing the semiconductor substrate 100 and the side surface of the gate structure 130 facing the semiconductor substrate 100 in a direction perpendicular to the surface of the semiconductor substrate (second direction Y) is 0.3 micrometers to 3 micrometers, for example, 0.3 micrometers, 0.5 micrometers, 1 micrometer, 2 micrometers or 3 micrometers.

[0069] It should be noted that, in other embodiments, the spacing between the side surface of the first doped layer 120 facing the semiconductor substrate 100 and the side surface of the gate structure 130 facing the semiconductor substrate 100 in a direction perpendicular to the surface of the semiconductor substrate (second direction Y) is not limited.

[0070] In one embodiment, the doping concentration of the first doped layer 120 is greater than the doping concentration of the drift layer.

[0071] In one embodiment, the doping concentration of the first doped layer 120 is 2 to 10 times that of the doping concentration of the drift layer 110.

[0072] In one embodiment, the semiconductor power device further includes: a second doped layer 140 located on the side of the gate structure 130 facing the semiconductor substrate layer 100 and in contact with the gate structure 130, wherein the doping type of the second doped layer 140 is the same as the doping type of the drift layer 110, and the doping concentration of the second doped layer 140 is greater than the doping concentration of the drift layer 110. The spacing between the first doped layer 120 and the semiconductor substrate layer 100 is less than the spacing between the second doped layer 140 and the semiconductor substrate layer 100.

[0073] The spacing between the second doped layer 140 and the semiconductor substrate 100 refers to the spacing along the second direction Y between the side surface of the second doped layer 140 facing the semiconductor substrate 100 and the side surface of the semiconductor substrate 100 facing the drift layer 110.

[0074] In one embodiment, the doping concentration of the second doped layer 140 is 2 to 10 times that of the doping concentration of the drift layer 110.

[0075] In one embodiment, the thickness of the second doped layer 140 is 0.1 micrometers to 1 micrometer, for example, 0.1 micrometers, 0.2 micrometers, 0.5 micrometers, 0.8 micrometers, or 1 micrometer. The thickness direction of the second doped layer 140 is the dimension of the second doped layer 140 along the second direction Y. The thickness direction of the second doped layer 140 is the direction from the surface of the second doped layer 140 facing the gate structure to the surface of the second doped layer 140 away from the gate structure.

[0076] Another embodiment of the present invention provides a method for fabricating a semiconductor power device, comprising: forming a drift layer, a plurality of first well regions spaced along a first direction, and a plurality of first doped layers spaced along the first direction on one side of a semiconductor substrate; the well regions are located in a portion of the drift layer, and the conductivity type of the well regions is opposite to that of the drift layer; the first doped layer is located in the drift layer on the side of the well regions facing the semiconductor substrate, the first doped layer is in contact with the well regions, and the doping type of the first doped layer is opposite to that of the drift layer; forming a gate structure, the gate structure being located in the drift layer between adjacent well regions and between adjacent first doped layers, the gate structure being spaced from the first doped layer; wherein the spacing distance between the first doped layer and the semiconductor substrate is less than the spacing distance between the gate structure and the semiconductor substrate, and the width dimension of the side surface of the first doped layer facing the semiconductor substrate along the first direction is greater than or equal to the width dimension of the side surface of the first doped layer away from the semiconductor substrate along the first direction.

[0077] In one embodiment, forming the plurality of first doped layers and the plurality of well regions includes: after forming the drift layer on one side of the semiconductor substrate, forming a first initial doped layer in the drift layer, the doping type of the first initial doped layer being opposite to the doping type of the drift layer, the first initial doped layer including a first region and a second region located on both sides of the first region along a first direction; performing ion implantation on the first region of the first initial doped layer such that the conductivity type of the first region is opposite to the conductivity type of the second region; after performing ion implantation on the first region of the first initial doped layer, forming the well regions in a portion of the second region and a portion of the first region, wherein the first doped layer is formed in the second region facing the semiconductor substrate.

[0078] The following is combined Figures 2 to 4 The method for fabricating the semiconductor power device in this embodiment is described in detail.

[0079] refer to Figure 2 A drift layer 110 is formed on one side of the semiconductor substrate layer 100; a first initial doped layer 1200 is formed in the drift layer, the doping type of the first initial doped layer 1200 is opposite to the doping type of the drift layer 110, and the first initial doped layer 1200 includes a first region 1200-1 and a second region 1200-2 located on both sides of the first region 1200-1 along a first direction X.

[0080] The first initial doped layer 1200 extends from the surface of the drift layer 110 away from the semiconductor substrate layer 100 to a portion of the thickness of the first initial doped layer 1200 in the drift layer 110.

[0081] The process for forming the first initial doped layer 1200 includes an ion implantation process.

[0082] The first initial doped layer 1200 is spaced apart from the semiconductor substrate layer 100.

[0083] refer to Figure 3 Ion implantation is performed on the first region 1200-1 of the first initial doped layer 1200 to make the conductivity type of the first region 1200-1 opposite to that of the second region 1200-2.

[0084] refer to Figure 4 After ion implantation into the first region 1200-1 of the first initial doped layer 1200, a well region 150 is formed in a portion of the second region 1200-2 and a portion of the first region 1200-1. The well region 150 forms the first doped layer 120 in the second region 1200-2 facing the semiconductor substrate layer 100.

[0085] The first doped layer 120 is located on the side of the well region 150 facing the semiconductor substrate layer 100 and is in contact with the well region 150.

[0086] The description of the first doped layer 120 is based on the content of the foregoing embodiments.

[0087] Continue to refer to Figure 4 A gate structure 130 is formed, which is located in a drift layer 110 between adjacent well regions 150 and adjacent first doped layer 120, and the gate structure 130 is spaced apart from the first doped layer 120.

[0088] Wherein, the spacing between the first doped layer 120 and the semiconductor substrate 100 is less than the spacing between the gate structure 130 and the semiconductor substrate 100, and the width dimension of the side surface of the first doped layer 120 facing the semiconductor substrate 100 along the first direction X is greater than the width dimension of the side surface of the first doped layer 120 away from the semiconductor substrate 100 along the first direction X.

[0089] Forming a gate structure 130 includes: forming a gate trench located in a drift layer 110 between adjacent well regions 150 and adjacent to the first doped layer 120; and forming the gate structure 130 in the gate trench.

[0090] In one embodiment, the method for fabricating a semiconductor power device further includes forming a second doped layer 140 in a drift layer 110 at the bottom of the gate trench before forming the gate structure 130 in the gate trench. The second doped layer 140 is in contact with the gate structure 130, the doping type of the second doped layer 140 is the same as the doping type of the drift layer 110, and the doping concentration of the second doped layer 140 is greater than the doping concentration of the drift layer 110. The spacing between the first doped layer 120 and the semiconductor substrate layer 100 is less than the spacing between the second doped layer 140 and the semiconductor substrate layer 100.

[0091] The method for fabricating a semiconductor power device further includes: forming a first source region 160 in a well region 150, wherein the conductivity type of the first source region 160 is opposite to that of the well region 150; and forming a second source region 170 in the well region 150, wherein the conductivity type of the second source region 170 is opposite to that of the first source region 160.

[0092] The first source region 160 is in contact with the sidewall of the gate structure 130, and the second source region 170 is located on the side of the first source region 160 away from the gate structure 130 along the first direction.

[0093] The method for fabricating a semiconductor power device further includes forming a drain 101 on the surface of the semiconductor substrate 100 facing away from the drift layer 110. The material of the drain 101 includes a metal.

[0094] Another embodiment of the present invention provides a method for fabricating a semiconductor power device, which differs from the previous embodiment in that: forming a drift layer, a plurality of first doped layers, and a plurality of well regions, comprising: forming a first sub-drift layer on one side of a semiconductor substrate; epitaxially forming a second sub-drift layer on the side of the first sub-drift layer away from the semiconductor substrate, wherein the doping type of the second sub-drift layer is opposite to that of the first sub-drift layer, and the second sub-drift layer includes a third region and a fourth region located on both sides of the third region along a first direction; performing ion implantation on the third region of the second sub-drift layer, such that the conductivity type of the third region is opposite to that of the fourth region and the same as that of the first sub-drift layer; after performing ion implantation on the third region of the second sub-drift layer, forming well regions in a portion of the fourth region and a portion of the third region, wherein a first doped layer is formed in the fourth region facing the semiconductor substrate.

[0095] In this embodiment, the description of forming the gate structure is the same as that in the previous embodiment and will not be described in detail again.

[0096] In this embodiment, the method further includes forming a second doped layer. The process of forming the second doped layer is described in the foregoing embodiment and will not be detailed hereafter.

[0097] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor power device, characterized by, Comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in part of the drift layer; a well region located in the drift layer on both sides of the gate structure along a first direction, respectively, the well region having a conductivity type opposite to that of the drift layer; a plurality of spaced first doped layers located in the drift layer on both sides of the gate structure along the first direction and on a side of the well region facing the semiconductor substrate layer, the first doped layers being in contact with the well region and spaced from the gate structure, the first doped layers having a doping type opposite to that of the drift layer; wherein a spacing distance between the first doped layers and the semiconductor substrate layer is less than a spacing distance between the gate structure and the semiconductor substrate layer, and a width dimension of a side surface of the first doped layers facing the semiconductor substrate layer along the first direction is greater than or equal to a width dimension of a side surface of the first doped layers away from the semiconductor substrate layer along the first direction.

2. The semiconductor power device of claim 1, wherein, The width dimension of the first doped layers in the first direction increases in a direction from the side of the first doped layers away from the semiconductor substrate layer to the side of the first doped layers facing the semiconductor substrate layer.

3. The semiconductor power device of claim 1, wherein, The doping concentration of the first doped layers is less than the doping concentration of the well region.

4. The semiconductor power device according to claim 3, wherein the doping concentration of the first doped layers is 1 / 10 to 1 / 2 of the doping concentration of the well region.

5. The semiconductor power device of claim 1, wherein, The first doped layers extend to a side of part of the gate structure facing the semiconductor substrate layer; or, a bottom surface of the first doped layers along a second direction has no overlapping area with a bottom surface of the gate structure along the second direction on a projection of a surface of the semiconductor substrate layer, the second direction being perpendicular to the surface of the semiconductor substrate layer.

6. The semiconductor power device according to claim 1, wherein the first doped layers extend to a side of part of the gate structure facing the semiconductor substrate layer, and a width dimension of an overlapping area of a bottom surface of the first doped layers along a second direction with a bottom surface of the gate structure along the second direction on a projection of a surface of the semiconductor substrate layer along the first direction is less than or equal to 0.5 microns.

7. The semiconductor power device according to claim 1, wherein a bottom surface of the first doped layers along a second direction has no overlapping area with a bottom surface of the gate structure along the second direction on a projection of a surface of the semiconductor substrate layer, and a spacing distance between a bottom surface of the first doped layers along the second direction on the projection of the surface of the semiconductor substrate layer and a bottom surface of the gate structure along the second direction on the projection of the surface of the semiconductor substrate layer along the first direction is less than or equal to 0.5 microns.

8. The semiconductor power device of claim 1, wherein, The interval distance between the first doped layer and the semiconductor substrate layer in a direction perpendicular to the surface of the semiconductor substrate layer is 0.3 microns to 3 microns.

9. The semiconductor power device of claim 1, wherein, The doping concentration of the first doped layer is greater than the doping concentration of the drift layer.

10. The semiconductor power device of claim 9, wherein The doping concentration of the first doped layer is 2 times to 10 times the doping concentration of the drift layer.

11. The semiconductor power device of claim 1, wherein, Further comprising: A second doped layer is located on the side of the gate structure facing the semiconductor substrate layer and in contact with the gate structure, the doping type of the second doped layer is the same as the doping type of the drift layer, and the doping concentration of the second doped layer is greater than the doping concentration of the drift layer. The interval distance between the first doped layer and the semiconductor substrate layer is less than the interval distance between the second doped layer and the semiconductor substrate layer.

12. The semiconductor power device of claim 11, wherein The doping concentration of the second doped layer is 2 times to 10 times the doping concentration of the drift layer.

13. The semiconductor power device of claim 11, wherein The thickness of the second doped layer is 0.1 microns to 1 microns.

14. A method of manufacturing a semiconductor power device, characterized by, Comprising: forming a drift layer, a plurality of first well regions spaced in a first direction, and a plurality of first doped layers on a side of a semiconductor substrate layer; the well regions are located in part of the drift layer, the conductivity type of the well regions is opposite to the conductivity type of the drift layer; the first doped layers are located in the drift layer on the side of the well regions facing the semiconductor substrate layer, the first doped layers are in contact with the well regions, the doping type of the first doped layers is opposite to the doping type of the drift layer; forming a gate structure in the drift layer between adjacent well regions and between adjacent first doped layers, the gate structure is spaced from the first doped layers; The interval distance between the first doped layer and the semiconductor substrate layer is less than the interval distance between the gate structure and the semiconductor substrate layer, and the width dimension of the side of the first doped layer facing the semiconductor substrate layer in the first direction is greater than or equal to the width dimension of the side of the first doped layer away from the semiconductor substrate layer in the first direction.

15. The method of manufacturing a semiconductor power device according to claim 14, wherein forming the plurality of first doped layers and the plurality of well regions, comprising: after forming the drift layer on the side of the semiconductor substrate layer, forming a first initial doped layer in the drift layer, the doping type of the first initial doped layer is opposite to the doping type of the drift layer, the first initial doped layer includes a first region and a second region located on both sides of the first region in a first direction; ion implantation is performed on the first region of the first initial doped layer, so that the conductivity type of the first region and the conductivity type of the second region are opposite; After the ion implantation on the third region of the second sub-drift layer, the well region is formed in part of the fourth region and in part of the third region, wherein the well region forms the first doped layer towards the fourth region on the side of the semiconductor substrate layer.

16. The method of claim 15, wherein, The process of forming the first initial doped layer in the drift layer comprises an ion implantation process.

17. The method of manufacturing a semiconductor power device according to claim 14, wherein The forming of the drift layer, the first doped layers and the well regions comprises: forming a first sub-drift layer on one side of the semiconductor substrate layer; and epitaxially forming a second sub-drift layer on the side of the first sub-drift layer away from the semiconductor substrate layer, the second sub-drift layer having a doping type opposite to that of the first sub-drift layer, the second sub-drift layer comprising a third region and fourth regions on both sides of the third region along a first direction; performing ion implantation on the third region of the second sub-drift layer so that the third region has a conduction type opposite to that of the fourth regions and same as that of the first sub-drift layer; After the ion implantation on the third region of the second sub-drift layer, the well region is formed in part of the fourth region and in part of the third region, wherein the well region forms the first doped layer towards the fourth region on the side of the semiconductor substrate layer.

18. The method of manufacturing a semiconductor power device according to claim 14, wherein The forming of the gate structure comprises forming a gate trench in the drift layer between adjacent well regions and between adjacent first doped layers; and forming the gate structure in the gate trench.

19. The method of manufacturing a semiconductor power device according to claim 18, wherein The method further comprises, before the forming of the gate structure in the gate trench, forming a second doped layer in the drift layer at the bottom of the gate trench; wherein the second doped layer is in contact with the gate structure, the second doped layer has a same doping type as the drift layer, and the second doped layer has a doping concentration greater than that of the drift layer. The interval distance between the first doped layer and the semiconductor substrate layer is less than the interval distance between the second doped layer and the semiconductor substrate layer.

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