FC device adaptive rate DMA communication method and communication system based on multi-partition

Abstract

The present invention provides a multi-partition FC device adaptive rate DMA communication method and communication system, the communication system includes FC equipment, FPGA and cache block dynamic adjustment module. During the transmission process, the performance of the partition may change due to various factors such as load changes and dynamic resource allocation. In order to ensure the stability and reliability of the system, a cache block dynamic adjustment module is set to dynamically adjust the size of the cache block according to the change of the partition performance, and perform DMA operations with the FPGA according to the dynamically adjusted cache block. The partition system increases / decreases the data transmission rate of the partition by changing the size of the DMA cache block corresponding to its own partition according to the real-time change of performance.

Description

Technical Field

[0001] The present invention relates to the technical field of FC fiber channel network communication, and in particular to a multi-partition-based FC device adaptive rate DMA communication method and communication system. Background Art

[0002] FC (Fiber Channel) network communication is a high-speed network communication technology based on fiber channel data transmission, providing high bandwidth, low latency and high reliability data transmission. The multi-partition DMA communication method of FC equipment based on the partition operating system allows the physical network to be divided into multiple logical channels through partition technology, so that multiple communication sessions can be carried out simultaneously on the same physical link to improve the performance and flexibility of the network, so that different communication traffic can be managed and optimized independently. At the same time, the use of partition technology allows a processor module to support one or more avionics application software, and ensures the time and space isolation between application software, so that each application software can run independently according to the time frame.

[0003] In the context of big data, the amount of data in the network is growing exponentially, and the requirements for network performance and reliability are getting higher and higher. In FC communication networks, the multi-partition DMA communication method can improve the efficiency of data processing. Combining data segmentation and queue optimization can further improve the efficiency of DMA buffer usage and solve multi-channel concurrency problems, reduce cache partition latency and network anomalies under large traffic loads. However, the traditional fixed-rate communication method cannot fully utilize network resources, resulting in resource waste or insufficient transmission performance. Therefore, in the dynamic rate communication method based on multi-partition receiving direction, a dynamic rate adjustment strategy based on multi-partition FC communication is proposed. The receiving partition splits the data according to the channel data and generates multiple cache blocks, that is, the size of the buffer is specifically divided and configured according to the data characteristics of the partition itself. For example, within the receiving partition, the receiving cache buffer is decomposed into multiple blocks, such as several buffers of 64k, 32k, 16k...1k in size. Each buffer corresponds to a physical base address (i.e., buffer number data, referred to as bd) used to initiate DMA operation. The partition pushes the cache block to the FPGA, and the FPGA sends data to the receiving partition according to the cache block. The efficiency of sending and receiving to the receiving partition is dynamically adjusted by calculating the margin of the partition receiving buffer, thereby realizing the control of the receiving traffic and avoiding the peak traffic at the receiving end, reducing the risk of receiving data overflow at the receiving end, thereby improving the stability and reliability of communication. In actual tests, it was found that the size of the cache block used in this method is still fixed, and the granularity of the cache block varies too much, which can only improve the cache usage efficiency to a certain extent; and the device will only make adjustments when the cache block is about to be exhausted and the system threshold is triggered. The size of the cache block cannot be dynamically adjusted according to the real-time rate on the link and the actual occupancy of system resources.

[0004] Prior art literature:

[0005] Patent document 1: CN116821042A FC device DMA communication method based on multi-partition

[0006] Patent document 2: CN115952117A DMA communication system and method based on FC device multi-partition receiving direction

[0007] Patent document 3: CN116489165A Dynamic rate communication method and system based on multi-partition receiving direction

[0008] Patent document 4: CN115118678A A multi-partition network communication system and communication method for FC equipment end Summary of the invention

[0009] The purpose of the present invention is to provide a multi-partition based FC device adaptive rate DMA communication method and system, which can dynamically and adaptively change the transmission rate according to network conditions and device capabilities, maximize the utilization of network resources and data transmission efficiency, optimize transmission performance, make the communication equipment have better versatility and applicability, and improve the efficiency and stability of FC communication.

[0010] According to a first aspect of an embodiment of the present invention, a multi-partition-based FC device adaptive rate DMA communication system is proposed, the system comprising an FC device, an FPGA, and a cache block dynamic adjustment module, wherein:

[0011] The FC device is configured with multiple partitions, each partition is independent of each other and can send and receive data. When the FC device sends data, the data is stored in the cache of at least one partition and is split into multiple cache blocks in the partition. Each cache block corresponds to a physical base address, which is sent to the FPGA to initiate a DMA operation.

[0012] The FPGA is configured with a DMA read / write control module, a logic processing module and an FC_MAC module. The DMA read / write control module is used to perform DMA read / write operations with the multiple partitions, including reading data from the cache of at least one partition and sending FC data frames to the cache of the destination partition; the logic processing module is configured to group FC data frames of data read from the FPGA and send them to the opposite device via the FC network through the FC_MAC module, and to parse and group PCIE data frames of data received from the opposite end via the FC_MAC module, and then send them to the partition cache of the destination partition via the DMA read / write control module;

[0013] The cache block dynamic adjustment module is configured to dynamically adjust the size of the cache block according to changes in partition performance, and perform DMA operations with the FPGA according to the dynamically adjusted cache block.

[0014] As an optional implementation, the cache block dynamic adjustment module is configured with a block prediction model dynamic training module and a cache block capacity prediction output module, wherein:

[0015] The block prediction model dynamic training module is configured to train a prediction model representing a mapping relationship between a partition performance indicator and a cache block based on the partition performance indicator obtained from the invalid data and normal data transmitted between the partition and the FPGA, and add each mapping relationship as an element into the monitoring window;

[0016] The cache block capacity prediction output module is used to predict the size of the cache block corresponding to the partition according to at least one element within the monitoring window range, and adjust the cache block corresponding to the partition accordingly, and push the physical base address of the adjusted cache block to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process.

[0017] Therefore, the size of the cache block is dynamically adjusted according to the change of the partition performance, and the DMA operation is performed with the FPGA according to the dynamically adjusted cache block, including:

[0018] According to the partition performance indicators obtained during the partition initialization phase (transmitted invalid data packets of different lengths) and / or the normal transmission of cache blocks between the partition and the FPGA, a prediction model representing the mapping relationship between the partition performance indicators and the cache blocks is trained, and each mapping relationship is added as an element into the monitoring window;

[0019] In the monitoring window size configured by the user, based on at least one element within the monitoring window range, the size of the partition cache block is predicted, and the cache block corresponding to the partition is adjusted accordingly. The physical base address of the adjusted cache block is pushed to the FPGA, and the FPGA performs DMA operations on the cache block after the partition is dynamically adjusted.

[0020] As an optional implementation, the partition performance index obtained by the invalid data transmitted between the partition and the FPGA includes:

[0021] The partition performance metrics obtained when the partition sends invalid cache blocks of different lengths and invalid contents to the FPGA for DMA operations; and

[0022] The partition performance index obtained when the FPGA sends data packets with different data lengths and invalid contents to the cache of the target partition.

[0023] The partition performance indicators include the data length corresponding to each transmission cache block, transmission delay, transmission bandwidth, partition resource occupancy indicator and cache block size indicator.

[0024] As an optional implementation, the block prediction model dynamic training module is configured to perform training based on a preset model using a partition performance indicator to obtain a training model representing a mapping relationship between the partition performance indicator and the cache block;

[0025] Furthermore, when the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance index of each cache block transmission is used for dynamic training, and the model updates the mapping relationship and adds the mapping relationship outputted by each update as a new element into the monitoring window;

[0026] When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

[0027] As an optional implementation, the monitoring window is configured with an initial length, and when one or more performance parameters determined by the mapping relationship between the partition performance index and the cache block fluctuate beyond a preset threshold range, the monitoring window length is dynamically adjusted to expand.

[0028] As an optional implementation, in response to one or more performance parameter fluctuations returning to within a preset threshold range, the monitoring window is gradually restored to its initial length.

[0029] As an optional implementation, when the monitoring window range contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

[0030] As an optional implementation, within the monitoring window range, if a new element enters the window, the element that first enters the window is discarded.

[0031] As an optional implementation, since each partition is independent, each partition can be trained independently without affecting each other. Therefore, the dynamic training module of the block prediction model corresponding to each partition is trained independently for dynamic adjustment of the cache blocks corresponding to each partition. In particular, when priority or channel is used to manage data within the partition, training can be performed separately for different priorities or different channels.

[0032] As an optional implementation, the aforementioned cache block dynamic adjustment module can be set in the FPGA, or in the partition. When set in the partition, the block prediction model dynamic training module and the cache block capacity prediction output module are configured in the partition, that is, the model training and cache block prediction output process are completed in the partition. When set in the FPGA, the partition sends its performance indicators to the FPGA, performs model training and cache block prediction output processes in the FPGA, and returns block size information to the partition, which dynamically adjusts the cache block and sends it to the FPGA for DMA operation.

[0033] According to a second aspect of the present invention, a multi-partition based adaptive rate DMA communication method is also proposed, comprising the following steps:

[0034] After the system is powered on, the PCIE interface is initialized. During the initialization phase, the partition sends invalid cache blocks of different lengths and invalid contents to the FPGA for DMA operations and obtains the corresponding partition performance indicators;

[0035] Based on the partition performance indicators obtained by transmitting invalid data packets in the initialization phase, a machine learning model is used for training to obtain a prediction model representing the mapping relationship between the partition performance indicators and the cache blocks, and each mapping relationship is added as an element to the monitoring window.

[0036] When the link between the partition and the FPGA has normal data transmission, the partition performance index corresponding to the cache block is obtained when the partition transmits the first cache block, and is input into the prediction model. The mapping relationship between the performance index of each partition and the cache block is given for the first time, and then the mapping relationship is sent into the monitoring window as an element. The subsequent cache blocks are processed according to the above steps and sent into the monitoring window;

[0037] According to at least one element within the monitoring window range, the size of the cache block corresponding to the partition is predicted, and the cache block corresponding to the partition is adjusted accordingly, and the physical base address of the adjusted cache block is pushed to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process;

[0038] When the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance index of each cache block transmission is used for dynamic training. The model updates the mapping relationship and adds the mapping relationship output each time as a new element to the monitoring window. When a new element enters the window, the element that enters the window first is discarded according to the window size.

[0039] When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

[0040] As an optional implementation, the monitoring window is configured with an initial length, and when one or more performance parameters determined by the mapping relationship between the partition performance index and the cache block fluctuate beyond a preset threshold range, the monitoring window length is dynamically adjusted to expand.

[0041] As an optional implementation, in response to one or more performance parameter fluctuations returning to within a preset threshold range, the monitoring window is gradually restored to its initial length.

[0042] As an optional implementation, when the monitoring window range contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

[0043] As an optional implementation, when the predicted size of the cache block is smaller than the length of the actually received data, the partition divides the actually received data into segments and performs DMA transmission in multiple times.

[0044] Through the implementation of the above technical solutions, in the adaptive rate DMA communication system and method of FC devices based on multiple partitions proposed by the present invention, the partition can dynamically and adaptively predict and adjust the size of the DMA cache block corresponding to the partition according to its own performance and network conditions, so as to increase / reduce the data transmission rate of the partition and maximize the utilization of network resources and transmission efficiency.

[0045] When the partition performance is not enough to receive a large amount of data, by reducing the size of the DMA cache block, the amount of data processed by the partition can be reduced, thereby reducing the partition load and improving the stability of the system. At the same time, small cache blocks can be processed by the target partition faster, reducing the occupation of system memory and other resources, and improving data processing efficiency. When the partition performance is high, by increasing the size of the DMA cache block, the interval time during the transmission process can be reduced, the delay of data transmission can be reduced, and the data throughput can be increased.

[0046] Therefore, during the transmission process, the partition performance will change due to various factors such as load changes and dynamic resource allocation. In order to ensure the reliability of the system, in the DMA communication method proposed in the present invention, the partition can adjust the size of the cache block according to the real-time changes in performance, thereby improving the efficiency and stability of system transmission and improving the overall performance.

[0047] It should be understood that all combinations of the aforementioned concepts and the additional concepts described in more detail below can be considered as part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of the claimed subject matter are considered as part of the inventive subject matter of the present disclosure.

[0048] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are not intended to be drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in each figure may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings.

[0050] Figure 1The figure is an overall block diagram of an adaptive rate DMA communication system for FC devices based on multiple partitions according to an embodiment of the present invention.

[0051] Figure 2 is a flow chart of establishing a dynamic monitoring window according to an embodiment of the present invention.

[0052] Figure 3 It is a schematic diagram of the module structure in a single partition according to an embodiment of the present invention.

[0053] Figure 4 2 is a schematic diagram of window movement according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0055] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0056] {FC device adaptive rate DMA communication system based on multi-partition}

[0057] Combination Figures 1 to 4 The embodiment shown is a multi-partition FC device adaptive rate DMA communication system, the system includes a FC device and an FPGA. An FC_MAC module is configured in the FPGA to access the FC optical fiber communication network and perform data communication with the opposite end device.

[0058] In an embodiment of the present invention, the FC device is configured with multiple partitions, each partition is independent of each other and can send and receive data. When the FC device sends data, the data is stored in the cache of at least one partition and is split into multiple cache blocks within the partition. Each cache block corresponds to a physical base address, which is sent to the FPGA to initiate a DMA operation.

[0059] It should be understood that DMA is the abbreviation of Direct Memory Access, which is a direct memory access technology that aims to copy data from one address space to another. The transfer action itself is implemented and completed by the DMA read / write controller, which realizes the DMA read / write operation between the target partition and the FPGA, and realizes data transfer and movement between each partition and the cache inside the FPGA without the participation of the CPU.

[0060] In the embodiment of the present invention, the FPGA is configured with a PCIE interface module 100 , a DMA read / write control module, a logic processing module 200 and a FC_MAC module 300 .

[0061] The DMA read / write control module is integrated in the PCIE interface module 100 and is used to perform DMA read / write operations with multiple partitions, including reading data from the cache of at least one partition and sending FC data frames to the cache of the destination partition.

[0062] The logic processing module 200 is configured to group FC data frames for FPGA read data and send them to the opposite device via the FC network through the FC_MAC module 300, and to parse and group the data received from the opposite end via the FC_MAC module 300 into PCIE data frames, and then send them to the partition cache of the destination partition through the DMA read-write control module.

[0063] The mapping relationship between the destination partition and the data is registered into the FPGA chip through the partition, that is, a piece of data enters the cache of one or more partitions through DMA according to the mapping relationship.

[0064] In an embodiment of the present invention, the cache block dynamic adjustment module 1000 is configured to dynamically adjust the size of the cache block according to changes in partition performance, and perform DMA operations with the FPGA according to the dynamically adjusted cache block.

[0065] As an optional implementation, the cache block dynamic adjustment module 1000 is configured with a block prediction model dynamic training module 1100 and a cache block capacity prediction output module 1200 .

[0066] The block prediction model dynamic training module 1100 is used to train a prediction model representing the mapping relationship between partition performance indicators and cache blocks based on the partition performance indicators obtained from invalid data and normal data transmitted between the partition and the FPGA, and add each mapping relationship as an element to the monitoring window.

[0067] The cache block capacity prediction output module 1200 is used to predict the size of the cache block corresponding to the partition based on at least one element within the monitoring window range, and adjust the cache block corresponding to the partition accordingly, and push the physical base address of the adjusted cache block to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process.

[0068] Combination Figure 2 , 4 As shown, the size of the cache block is dynamically adjusted according to the change of the partition performance, and the DMA operation is performed with the FPGA according to the dynamically adjusted cache block, including:

[0069] According to the partition performance index obtained during the partition initialization phase (transmitting invalid data) and / or the transmission of cache blocks between the partition and the FPGA, a prediction model representing the mapping relationship between the partition performance index and the cache block is trained, and each mapping relationship is added as an element into the monitoring window;

[0070] In the monitoring window size configured by the user, based on at least one element within the monitoring window range, the size of the partition cache block is predicted, and the cache block corresponding to the partition is adjusted accordingly. The physical base address of the adjusted cache block is pushed to the FPGA, and the FPGA performs DMA operations on the cache block after the partition is dynamically adjusted.

[0071] Among them, the partition performance indicators obtained by the invalid data transmitted between the partition and the FPGA include:

[0072] The partition performance metrics obtained when the partition sends invalid cache blocks of different lengths and invalid contents to the FPGA for DMA operations; and

[0073] The partition performance index obtained when the FPGA sends data packets with different data lengths and invalid contents to the cache of the target partition.

[0074] As an optional implementation, the partition performance index includes the data length corresponding to each transmission of the cache block, the transmission delay, the transmission bandwidth, the partition resource occupancy index and the cache block size index.

[0075] As an optional implementation, the aforementioned block prediction model dynamic training module 1100 is configured to perform training based on a preset model using a partition performance indicator to obtain a training model representing a mapping relationship between the partition performance indicator and the cache block;

[0076] Furthermore, when the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance index of each cache block transmission is used for dynamic training, and the model updates the mapping relationship and adds the mapping relationship outputted by each update as a new element into the monitoring window;

[0077] When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

[0078] In an embodiment of the present invention, the aforementioned machine learning model may adopt one of the models including but not limited to convolutional neural network CNN, recurrent neural network RNN, generative adversarial network GANs, deep reinforcement learning RL, logistic regression model, etc.

[0079] Combination Figure 4 As shown, the monitoring window is configured with an initial length, and when one or more performance parameters determined by the mapping relationship between the partition performance index and the cache block fluctuate beyond a preset threshold range, the length of the monitoring window is dynamically adjusted to expand. In an embodiment of the present invention, the initial length of the window is 4, that is, the monitoring window includes 4 elements.

[0080] In the specific implementation process, when the content of the newly entered element in the window differs too much from the existing element content, if the partition selects the dynamic adjustment method, the size of the window will be expanded to ensure the accuracy of the predicted data as much as possible. If the fluctuation of one or more performance parameters is restored to within the preset threshold range, the partition gradually restores the monitoring window to the initial length.

[0081] In particular, when the monitoring window range contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

[0082] As an optional implementation, within the monitoring window range, if a new element enters the window, the element that first enters the window is discarded.

[0083] As an optional implementation, since each partition is independent, each partition can be trained independently without affecting each other. Therefore, the dynamic training module of the block prediction model corresponding to each partition is trained independently for dynamic adjustment of the cache blocks corresponding to each partition. In particular, when priority or channel is used to manage data within the partition, training can be performed separately for different priorities or different channels.

[0084] As an optional implementation, the aforementioned cache block dynamic adjustment module can be set in the FPGA, or in the partition. When set in the partition, the block prediction model dynamic training module and the cache block capacity prediction output module are configured in the partition, that is, the model training and cache block prediction output process are completed in the partition. When set in the FPGA, the partition sends its performance indicators to the FPGA, performs model training and cache block prediction output processes in the FPGA, and returns block size information to the partition, which dynamically adjusts the cache block and sends it to the FPGA for DMA operation.

[0085] exist Figure 3 In the example, model training and prediction output cache block size are used as examples in partitions.

[0086] {Adaptive rate DMA communication method based on multiple partitions}

[0087] Combined with the implementation of the DMA communication system in the above embodiment, the model training is carried out in the partition as an example. Figure 2 , 3 As shown in , 4, the adaptive rate DMA communication method based on multiple partitions according to the embodiment disclosed in the present invention includes the following steps:

[0088] After the system is powered on, the PCIE interface is initialized. During the initialization phase, the partition sends invalid cache blocks of different lengths and invalid contents to the FPGA for DMA operations and obtains the corresponding partition performance indicators;

[0089] Based on the partition performance indicators obtained by transmitting invalid data packets in the initialization phase, a machine learning model is used for training to obtain a prediction model representing the mapping relationship between the partition performance indicators and the cache blocks, and each mapping relationship is added as an element to the monitoring window.

[0090] When the link between the partition and the FPGA has normal data transmission, the partition performance index corresponding to the cache block is obtained when the partition transmits the first cache block, and is input into the prediction model. The mapping relationship between the performance index of each partition and the cache block is given for the first time, and then the mapping relationship is sent into the monitoring window as an element. The subsequent cache blocks are processed according to the above steps and sent into the monitoring window;

[0091] According to at least one element within the monitoring window range, the size of the cache block corresponding to the partition is predicted, and the cache block corresponding to the partition is adjusted accordingly, and the physical base address of the adjusted cache block is pushed to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process;

[0092] Among them, when the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance indicators of each cache block transmission are used for dynamic training. The model updates the mapping relationship and adds the mapping relationship output each time as a new element to the monitoring window. For new elements entering the window, the elements that first enter the window are discarded according to the window size.

[0093] When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

[0094] Combination Figure 4 As shown, the monitoring window is configured with an initial length, and when one or more performance parameters determined by the mapping relationship between the partition performance index and the cache block fluctuate beyond a preset threshold range, the monitoring window length is dynamically adjusted to be expanded.

[0095] As an optional implementation, in response to one or more performance parameter fluctuations returning to within a preset threshold range, the monitoring window is gradually restored to its initial length.

[0096] As an optional implementation, when the monitoring window range contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

[0097] As an optional implementation, when the predicted size of the cache block is smaller than the length of the actually received data, the partition divides the actually received data into segments and performs DMA transmission in multiple times.

[0098] Therefore, in the multi-partition FC device adaptive rate DMA communication system and method proposed by the present invention, the partition can dynamically and adaptively predict and adjust the size of the DMA cache block corresponding to the partition according to its own performance and network conditions, so as to increase / reduce the data transmission rate of the partition and maximize the utilization of network resources and transmission efficiency.

[0099] When the partition performance is not enough to receive a large amount of data, by reducing the size of the DMA cache block, the amount of data processed by the partition can be reduced, thereby reducing the partition load and improving the stability of the system. At the same time, small cache blocks can be processed by the target partition faster, reducing the occupation of system memory and other resources, and improving data processing efficiency. When the partition performance is high, by increasing the size of the DMA cache block, the interval time during the transmission process can be reduced, the delay of data transmission can be reduced, and the data throughput can be increased.

[0100] Therefore, during the transmission process, the partition performance will change due to various factors such as load changes and dynamic resource allocation. In order to ensure the reliability of the system, in the DMA communication method proposed in the present invention, the partition can adjust the size of the cache block according to the real-time changes in performance, thereby improving the efficiency and stability of system transmission and improving the overall performance.

[0101] {Example 1}

[0102] Combination Figure 1 The overall system design shown includes FPGA and multiple partitions (oa1, os2, os3, ..., osn). The multiple partitions are independent of each other, and each independent partition can receive data and send data. The number of partitions can be any number.

[0103] When the host computer needs to send data, the data is placed in the partition cache through the partition.

[0104] The FPGA uses the PCIE interface module to perform DMA to read the data in the cache. The tx_top module divides the parsed data into data packets that comply with the fc protocol and sends them out through the FC_MAC module.

[0105] When the FC_MAC module receives the data, it is parsed in the rx_top module to form a data packet that complies with the PCIE protocol and is sent to the cache of the destination partition through the DMA of the PCIE module.

[0106] The mapping relationship between the destination partition and the data is registered into the FPGA through the partition, that is, a piece of data enters the cache of one or more partitions through DMA according to the mapping relationship.

[0107] During the transmission process, the performance of the partition may change due to various factors such as changes in load and allocation of dynamic resources. In order to ensure the stability and reliability of the system, in an embodiment of the present invention, the partition system increases / decreases the data transmission rate of the partition by changing the size of the DMA cache block corresponding to the partition according to the real-time changes in performance.

[0108] When the partition performance is not sufficient to receive a large amount of data, the size of the DMA cache block can be reduced to reduce the amount of data processed by the partition, thereby reducing the partition load and improving system stability. Small cache blocks can be processed by the target partition faster, reducing the use of system memory and other resources and improving data processing efficiency.

[0109] When the partition performance is high, by increasing the size of the DMA block, the interval time during the transmission process can be reduced, the delay of data transmission can be reduced, and the data throughput can be increased, thereby improving the overall performance of the system.

[0110] {Example 2}

[0111] Combination Figure 2 As shown, a schematic diagram of establishing a dynamic monitoring window is exemplarily shown, taking the receiving direction as an example, that is, the FPGA sends data to the partition.

[0112] First, in the partition initialization phase, multiple invalid data packets of different lengths and invalid contents are sent to the partition through the FPGA, and these data are used to train the prediction model so that the size of the cache block can be predicted more accurately in the future.

[0113] Next, the partition extracts the partition index parameters of the data length, transmission delay, transmission bandwidth, and partition resource occupancy of each received data packet, and uses the prediction model to establish / update the mapping relationship between the partition performance index and the cache block.

[0114] After the mapping relationship is determined, it is added to the monitoring window, where the size of the monitoring window is configured by the user, or the size of the window is adjusted dynamically.

[0115] Among them, the monitoring window is configured with an initial length. In this example, the window length is 4, that is, 4 elements (mapping relationships), and when one or more performance parameters determined by the mapping relationship between the partition performance indicator and the cache block fluctuate beyond the preset threshold range, it is dynamically adjusted to expand the length of the monitoring window.

[0116] In the specific implementation process, when the content of the newly entered element in the window differs too much from the existing element content, if the partition selects the dynamic adjustment method, the size of the window will be expanded to ensure the accuracy of the predicted data as much as possible. If the fluctuation of one or more performance parameters is restored to within the preset threshold range, the partition gradually restores the monitoring window to the initial length.

[0117] In particular, when the monitoring window range contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

[0118] As an optional implementation, the aforementioned window strategy processing includes one of taking the mean, median, maximum or minimum value, trend analysis value, and statistical feature extraction. In this example, taking the mean is taken as an example.

[0119] When the performance parameters output by the model fluctuate too much or are lower than the set threshold, the window is enlarged to obtain more accurate results. When the fluctuation is stable, it is gradually restored to the initial window size.

[0120] When the link receives data normally, the relevant parameters of this data block are updated into the model, and the model updates the mapping relationship (such as a mapping table), which is finally output to the monitoring window of the partition through the mapping relationship. If the link is in an idle state, the training and model update of invalid data packets are performed again to always keep the parameters in the window in the latest state.

[0121] {Example 3}

[0122] Combination Figure 2 , 3 , 4, the description is made taking the receiving direction as an example (the sending direction is the same).

[0123] When the system is powered on, the PCIE interface module is initialized and the partition starts to push buffers of different sizes to the FPGA. Due to the limited initialization time, a limited number of blocks of different sizes are pushed here (the size k here can be a larger buffer block to ensure normal data transmission. The more subsequent training times, the more accurate the results). The FPGA starts to perform DMA write operations, and the content is all invalid (such as all 0s).

[0124] In other examples, as mentioned above, the FPGA may also send multiple invalid data packets of different lengths and invalid contents to the partition, and use these data to train the prediction model so as to more accurately predict the size of the cache block in the future.

[0125] Since each partition is independent, each partition can be trained independently without affecting each other. When priority or channels are used to manage data within the partition, training can be performed separately for different priorities or channels.

[0126] like Figure 3 As shown, when a partition receives the first block, it will obtain the corresponding parameter information such as the transmission delay, effective data length, bandwidth, and resources occupied by the partition. Then, these parameter information will be given to the trained prediction model. The model output will give the mapping relationship between each parameter and the cache block for the first time. Finally, the mapping relationship will be sent to the monitoring window as an element. Subsequent blocks will be sent to the monitoring window according to the above steps. Figure 4 ,Within the range of the monitoring window, if a new element enters the window, the element that first enters the window will be discarded to ensure the real-time nature of the data when executing the window strategy.

[0127] like Figure 4As shown, taking 4 elements as an example (the initial length of the window is configured to be 4), the size of the first window is a set of 4 elements (the window size can be set with a threshold or dynamically adjusted), and the four elements are processed with a window strategy (such as mean, median, maximum or minimum value, trend analysis value, statistical feature extraction), and a final numerical result can be obtained. According to this result and the mapping relationship, a predicted cache block size is given and pushed to DPGA for subsequent use, completing the entire data transmission process.

[0128] When the link is idle, training of invalid packets of different lengths will continue to increase the accuracy of the prediction.

[0129] Moreover, when the content of the newly entered element in the window differs too much from that of the existing element, if the partition OS chooses the dynamic adjustment method, the size of the window will be expanded to ensure the accuracy of the predicted data as much as possible.

[0130] In some embodiments, when the predicted cache block size is smaller than the actual length of the received data packet, the partition will divide the actually received data packet into segments and perform DMA transmission in multiple times to prevent data loss or jamming. When the predicted cache block size is larger than the actual length of the received data packet, the utilization of the cache block will decrease, the transmission time will be extended, and the partition will give the next prediction result based on the processing method and push it to the FPGA for subsequent use.

[0131] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A multi-partition based FC device adaptive rate DMA communication system, characterized in that: The system includes an FC device, an FPGA, and a cache block dynamic adjustment module, wherein: The FC device is configured with multiple partitions, each partition is independent of each other and can send and receive data. When the FC device sends data, the data is stored in the cache of at least one partition and is split into multiple cache blocks in the partition. Each cache block corresponds to a physical base address, which is sent to the FPGA to initiate a DMA operation. The FPGA is configured with a DMA read / write control module, a logic processing module and an FC_MAC module. The DMA read / write control module is used to perform DMA read / write operations with the multiple partitions, including reading data from the cache of at least one partition and sending FC data frames to the cache of the destination partition; the logic processing module is configured to group FC data frames of data read from the FPGA and send them to the opposite device via the FC network through the FC_MAC module, and to parse and group PCIE data frames of data received from the opposite end via the FC_MAC module, and then send them to the partition cache of the destination partition via the DMA read / write control module; The cache block dynamic adjustment module is configured to dynamically adjust the size of the cache block according to the change of the partition performance, and perform DMA operations with the FPGA according to the dynamically adjusted cache block; The cache block dynamic adjustment module is configured with a block prediction model dynamic training module and a cache block capacity prediction output module, wherein: The block prediction model dynamic training module is configured to train a prediction model representing a mapping relationship between a partition performance indicator and a cache block based on the partition performance indicator obtained from the invalid data and normal data transmitted between the partition and the FPGA, and add each mapping relationship as an element into the monitoring window; The cache block capacity prediction output module is used to predict the size of the cache block corresponding to the partition according to at least one element within the monitoring window range, and adjust the cache block corresponding to the partition accordingly, and push the physical base address of the adjusted cache block to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process.

2. The multi-partition-based FC device adaptive rate DMA communication system according to claim 1, characterized in that: The partition performance index includes the data length corresponding to the cache block transmitted each time, the transmission delay, the transmission bandwidth, the partition resource occupancy index and the cache block size index.

3. The multi-partition-based FC device adaptive rate DMA communication system according to claim 1, characterized in that: The block prediction model dynamic training module is configured to perform training based on a preset model using a partition performance indicator to obtain a training model representing a mapping relationship between the partition performance indicator and the cache block; Furthermore, when the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance index of each cache block transmission is used for dynamic training, and the model updates the mapping relationship and adds the mapping relationship outputted by each update as a new element into the monitoring window; When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

4. The multi-partition FC device adaptive rate DMA communication system according to any one of claims 1 to 3, characterized in that: The monitoring window is configured with an initial length, and when a fluctuation of one or more performance parameters determined by a mapping relationship between partition performance indicators and cache blocks exceeds a preset threshold range, the monitoring window is dynamically adjusted to expand the length.

5. The multi-partition-based FC device adaptive rate DMA communication system according to claim 4, characterized in that: In response to one or more performance parameter fluctuations returning to within a preset threshold range, the monitoring window is gradually restored to an initial length.

6. The multi-partition-based FC device adaptive rate DMA communication system according to claim 4, characterized in that: When the monitoring window contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

7. The multi-partition-based FC device adaptive rate DMA communication system according to claim 4, characterized in that: Within the monitoring window, if a new element enters the window, the element that first enters the window is discarded.

8. The multi-partition-based FC device adaptive rate DMA communication system according to claim 1, characterized in that: The block prediction model dynamic training modules corresponding to each partition are trained independently for dynamic adjustment of the cache blocks corresponding to each partition.

9. An adaptive rate DMA communication method based on multiple partitions of the adaptive rate DMA communication system for FC devices based on multiple partitions according to any one of claims 1 to 8, characterized in that: The following steps are involved: After the system is powered on, the PCIE interface is initialized. During the initialization phase, the partition sends invalid cache blocks of different lengths and invalid contents to the FPGA for DMA operations and obtains the corresponding partition performance indicators; Based on the partition performance indicators obtained by transmitting invalid data packets in the initialization phase, a machine learning model is used for training to obtain a prediction model representing the mapping relationship between the partition performance indicators and the cache blocks, and each mapping relationship is added as an element to the monitoring window. When the link between the partition and the FPGA has normal data transmission, the partition performance index corresponding to the cache block is obtained when the partition transmits the first cache block, and is input into the prediction model. The mapping relationship between the performance index of each partition and the cache block is given for the first time, and then the mapping relationship is sent into the monitoring window as an element. The subsequent cache blocks are processed according to the above steps and sent into the monitoring window; According to at least one element within the monitoring window range, the size of the cache block corresponding to the partition is predicted, and the cache block corresponding to the partition is adjusted accordingly, and the physical base address of the adjusted cache block is pushed to the FPGA. The FPGA performs DMA operation on the cache block after the partition is dynamically adjusted to complete the entire data transmission process; When the link between the partition and the FPGA is in the normal data cache block transmission, the partition performance index of each cache block transmission is used for dynamic training. The model updates the mapping relationship and adds the mapping relationship output each time as a new element to the monitoring window. When a new element enters the window, the element that enters the window first is discarded according to the window size. When the link between the partition and the FPGA is idle, invalid data packets of different lengths and invalid contents are continuously transmitted between the partition and the FPGA, and continuous training and model updating are performed based on the partition performance indicators at this time.

10. The multi-partition-based FC device adaptive rate DMA communication method according to claim 9, characterized in that: The monitoring window is configured with an initial length, and when a fluctuation of one or more performance parameters determined by a mapping relationship between partition performance indicators and cache blocks exceeds a preset threshold range, the monitoring window is dynamically adjusted to expand the length.

11. The multi-partition-based FC device adaptive rate DMA communication method according to claim 10, characterized in that: In response to one or more performance parameter fluctuations returning to within a preset threshold range, the monitoring window is gradually restored to an initial length.

12. The multi-partition-based FC device adaptive rate DMA communication method according to claim 9, characterized in that: When the monitoring window contains multiple elements, the partition executes window strategy processing on the parameters corresponding to the multiple elements, calculates a final numerical result, and gives a predicted cache block size based on the numerical result and the mapping relationship.

13. The multi-partition-based FC device adaptive rate DMA communication method according to claim 9, characterized in that: When the predicted size of the cache block is smaller than the length of the actually received data, the partition divides the actually received data into segments and performs DMA transmission in multiple times.

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