An efficient integrated circuit design method based on shared devices

Abstract

The present invention provides an efficient integrated circuit design method based on shared devices, which relates to the technical field of integrated circuit design, including obtaining key data information of all standard cells, and performing commonality analysis to obtain a target commonality identification part; using the target commonality identification part to design an initial editing unit template; performing simulation tests on the initial editing unit template, and optimizing and adjusting the initial editing unit template according to the test results to obtain an editable unit template; according to the design requirements of the integrated circuit, calling a matching editable unit template for editing and modification. By extracting the commonality part of the standard cell design and establishing an editable template in an array form, which is used for editing and applying the template during integrated circuit design, it can effectively reduce the original investment cost, improve the efficiency and quality of integrated circuit design, and ensure the high efficiency of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an efficient integrated circuit design method based on shared devices. Background Art

[0002] In recent years, with the continuous development of science and technology, the functions of electronic products have become more and more powerful, the performance has become more and more superior, and the demand for integrated circuits has also increased. In order to meet market demand, integrated circuit design has been continuously developing towards higher performance, lower power consumption, and smaller size, and standard cell design has emerged. However, standard cell design has defects such as high human and material investment costs and long time consumption. Therefore, how to overcome the defects of standard cell design and improve the efficiency of integrated circuit design has become the focus of current research.

[0003] Therefore, the present invention provides an efficient integrated circuit design method based on shared devices. Summary of the invention

[0004] The present invention provides an efficient integrated circuit design method based on shared devices, which is used to establish an editable template in an array form by extracting the common parts of the standard unit design, and is used for editing and applying the template during integrated circuit design. It can effectively reduce the original investment cost, improve the efficiency and quality of integrated circuit design, and ensure the high performance of the circuit.

[0005] The present invention provides an efficient integrated circuit design method based on shared devices, comprising:

[0006] Step 1: Obtain key data information of all standard cells, and perform commonality analysis to obtain the target commonality identification part;

[0007] Step 2: Designing an initial editing unit template using the target commonality recognition part;

[0008] Step 3: Performing simulation test on the initial editing unit template, and optimizing and adjusting the initial editing unit template according to the test result to obtain an editable unit template;

[0009] Step 4: According to the design requirements of the integrated circuit, call up the matching editable unit template for editing and modification.

[0010] Preferably, key data information of relevant standard units is obtained, and commonality analysis is performed to obtain a target commonality identification part, including:

[0011] Obtain data information of all standard units and extract key data information;

[0012] Performing commonality analysis on the remaining key data in the key data information except the unit type to obtain all commonality parts of the units;

[0013] Dividing all standard cells by using the cell types in the key data information to obtain a first standard cell set, and marking corresponding cell types;

[0014] Performing commonality analysis on key data information of all standard cells in the first standard cell set to obtain a specific commonality part;

[0015] The specific commonality part and all commonality parts of the units are aggregated to obtain a target commonality part, which is regarded as a target commonality identification part corresponding to the first standard unit set.

[0016] Preferably, the key data information includes unit type, pin configuration and layout.

[0017] Preferably, designing an initial editing unit template using the target commonality recognition part includes:

[0018] Generate a target commonality module by extracting a target commonality identification portion from standard cells in the first standard cell set;

[0019] Use CAD tools to create an initial array frame, place the target common module into the initial array frame, and then add connection lines and pins;

[0020] Add and utilize parametric design capabilities to complete the design of the initial editing unit template.

[0021] Preferably, a simulation test is performed on the initial editing unit template, and the initial editing unit template is optimized and adjusted according to the test result to obtain an editable unit template, including:

[0022] Step 11: Set the simulation input data and expected output results;

[0023] Step 12: Import the initial edit unit template into the set simulation tool, then input the set simulation input data to run the simulation, and obtain the running output result;

[0024] Step 13: If there is an error exception report in the running output result, it is determined that the initial editing unit template in the current simulation process is running abnormally;

[0025] According to the error type, location and cause in the error exception report, the initial editing unit template is adjusted and the simulation is run again to obtain the running output result;

[0026] If there is no error exception report in the current running output result, the initial editing unit template is optimized by using the performance evaluation result obtained by analyzing the running output result and the expected output result to obtain an editable unit template;

[0027] Step 14: If there is no error or exception report in the running output result, it is determined that the initial editing unit template runs normally during the current simulation process;

[0028] By using the performance evaluation result obtained by analyzing the running output result and the expected output result, the current initial editing unit template is optimized to obtain an editable unit template;

[0029] Step 15: Repeat steps 11 to 14 to perform a preset number of template operation simulations and performance tests under different application scenarios, and iteratively optimize the initial editing unit template to obtain an editable unit template;

[0030] Step 16: Summarize the editable unit templates of all unit types in different application scenarios, create corresponding standard unit editing template files, and save them to the preset editable unit template library.

[0031] Preferably, the current initial editing unit template is optimized by using the performance evaluation result obtained by analyzing the running output result and the expected output result to obtain an editable unit template, including:

[0032] Compare the running output results with the expected output results to obtain performance comparison results;

[0033] Comparing the first performance parameter difference in the performance comparison result with a parameter data threshold corresponding to the first performance parameter extracted from a preset performance-threshold mapping table;

[0034] If the first performance parameter difference is less than the corresponding parameter data threshold, the current first performance parameter is marked as a normal performance parameter;

[0035] Otherwise, marking the current first performance parameter as a possible normal performance parameter;

[0036] At this time, if there are zero possible normal performance parameters, it is determined that the initial editing unit template does not need to be optimized and adjusted, and the current initial editing unit template is output as an editable unit template;

[0037] If there is only a single possible normal performance parameter, the optimization direction that matches the current possible normal performance parameter is used as the target optimization direction;

[0038] Acquire a template optimization strategy that matches the target optimization direction;

[0039] If there are multiple possible normal performance parameters, calculating the performance evaluation index of each possible normal performance parameter based on the first performance parameter difference and the parameter data threshold;

[0040] Outputting the performance evaluation index and the optimization priority set of the corresponding possible normal performance parameters determined according to the performance evaluation index as the performance evaluation result;

[0041] A machine learning algorithm is introduced to train a model using a preset amount of unit historical optimization data extracted from a standard unit optimization database as training data to obtain an optimization generation model;

[0042] Extracting key feature data of the current initial editing unit template and inputting them into the optimization generation model together with the performance evaluation result to obtain a model optimization strategy;

[0043] The template optimization strategy is used in combination with the shared device to optimize and adjust the current initial editing unit template to obtain an editable unit template.

[0044] Preferably, the calculation formula of the performance evaluation index is as follows:

[0045] ;in, It is expressed as the performance evaluation index of the i-th possible normal performance parameter; The first performance parameter difference represented as the i-th possible normal performance parameter; denoted as the parameter data threshold of the i-th possible normal performance parameter; It is represented as the parameter importance weight of the i-th possible normal performance parameter in the current application scenario; It is expressed as the comprehensive influence coefficient of the common influencing factors of performance parameters on the performance evaluation of possible normal performance parameters; It is expressed as the value of the jth main influencing indicator of the i-th possible normal performance parameter; It is expressed as the influence coefficient of the jth main influencing indicator of the ith possible normal performance parameter on the performance evaluation of the current possible normal performance parameter.

[0046] Preferably, according to the design requirements of the integrated circuit, a matching editable unit template is retrieved for editing and modification, including:

[0047] Based on the design requirements of integrated circuits, obtain the current standard cell type requirements and cell size requirements;

[0048] Retrieving an editable unit template file matching the standard unit type requirement unit type from a preset editable unit template library, and establishing a unit template to be edited;

[0049] According to the unit size requirement, the unit template to be edited is edited and then used for integrated circuit design.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] By extracting the common parts of standard unit designs and establishing editable templates in array form, the templates can be edited and applied during integrated circuit design, which can effectively reduce the original investment cost, improve the efficiency and quality of integrated circuit design, and ensure the high performance of the circuit.

[0052] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0053] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0055] Figure 1 The present invention is a flowchart of an efficient integrated circuit design method based on shared devices in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0057] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, such as Figure 1 As shown, including:

[0058] Step 1: Obtain key data information of all standard cells, and perform commonality analysis to obtain the target commonality identification part;

[0059] Step 2: Designing an initial editing unit template using the target commonality recognition part;

[0060] Step 3: Performing simulation test on the initial editing unit template, and optimizing and adjusting the initial editing unit template according to the test result to obtain an editable unit template;

[0061] Step 4: According to the design requirements of the integrated circuit, call up the matching editable unit template for editing and modification.

[0062] In this embodiment, standard cells refer to a basic building block in integrated circuit design, especially in digital circuit design. They are pre-designed circuit modules with specific functions manufactured by semiconductor technology, such as logic gates (AND, OR, NOT, NAND, NOR, etc.), flip-flops (Flip-Flop), multiplexers (Mux), decoders (Decoders), etc.; key data information includes the unit type, pin configuration and layout of the standard unit, where the unit type includes logic gate units, drive units, timing units, operation units, mixed logic units, I / O units and special function units.

[0063] In this embodiment, the target commonality identification part is used to express the common characteristics of all standard cells in the corresponding first standard cell set of different cell types, namely the pin configuration standards and the layout rules of the board; the initial editing cell template is a template built based on the CAD tool that allows users to configure standard cells of different numbers and configurations through editing.

[0064] In this embodiment, the editable cell template is a cell template obtained by iterative optimization of the initial edit template; the design requirements include functional requirements, performance requirements, circuit design requirements, and cost requirements, etc., wherein the circuit design requirements include standard cell type requirements, cell size requirements, etc.; the cell size requirements refer to the requirements for the number of standard cells, the width and height requirements, and the pin position requirements, etc.

[0065] The beneficial effect of the above technical solution is: by extracting the common parts of the standard unit design, an editable template is established in an array form, which is used for editing and applying the template during integrated circuit design, which can effectively reduce the original investment cost, improve the efficiency and quality of integrated circuit design, and ensure high circuit performance.

[0066] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, which obtains key data information of all standard cells and performs commonality analysis to obtain a target commonality identification part, including:

[0067] Obtain data information of all standard units and extract key data information;

[0068] Performing commonality analysis on the remaining key data in the key data information except the unit type to obtain all commonality parts of the units;

[0069] Dividing all standard cells by using the cell types in the key data information to obtain a first standard cell set, and marking corresponding cell types;

[0070] Performing commonality analysis on key data information of all standard cells in the first standard cell set to obtain a specific commonality part;

[0071] The specific commonality part and all commonality parts of the units are aggregated to obtain a target commonality part, which is regarded as a target commonality identification part corresponding to the first standard unit set.

[0072] In this embodiment, standard cells refer to a basic building block in integrated circuit design, especially in digital circuit design. They are pre-designed circuit modules with specific functions manufactured by semiconductor technology, such as logic gates (AND, OR, NOT, NAND, NOR, etc.), flip-flops (Flip-Flop), multiplexers (Mux), decoders (Decoders), etc.; data materials include data manuals, design documents, schematics, and layout information of standard cells, etc.

[0073] In this embodiment, the key data information includes the unit type, pin configuration and layout of the standard unit, wherein the unit type includes logic gate unit, drive unit, timing unit, operation unit, hybrid logic unit, I / O unit and special function unit.

[0074] In this embodiment, all common parts of the units refer to the parts common to all standard units obtained based on the commonality analysis of the pin configuration and the layout in the key data information; the first standard unit set is composed of a set of related standard units with the same unit type.

[0075] In this embodiment, the specific common part refers to the part common to standard cells of the same cell type obtained based on the commonality analysis of the pin configuration and layout in the key data information; the target common part is obtained by summarizing the specific common part and all the common parts of the cells; the target commonality identification part is used to express the common characteristics of all standard cells in the corresponding first standard cell set of different cell types, namely the pin configuration standard and layout rules, wherein the pin configuration standard includes the number, type and function of pins, and the layout rules refer to the arrangement and connection of components such as transistors, resistors and capacitors.

[0076] The beneficial effect of the above technical solution is: by extracting the common parts of all standard cells and the common parts of corresponding standard cells of different cell types and summarizing them to obtain the target common identification part, data support is laid for establishing editable modules, and it is beneficial to improve design efficiency and quality. The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, using the target common identification part to design an initial edit unit template, including:

[0077] Generate a target commonality module by extracting a target commonality identification portion from standard cells in the first standard cell set;

[0078] Use CAD tools to create an initial array frame, place the target common module into the initial array frame, and then add connection lines and pins;

[0079] Add and utilize parametric design capabilities to complete the design of the initial editing unit template.

[0080] In this embodiment, the first standard cell set is composed of a set of related standard cells of the same cell type; standard cells refer to a basic building block in integrated circuit design, especially in digital circuit design. They are pre-designed circuit modules with specific functions manufactured by semiconductor technology, such as logic gates (AND, OR, NOT, NAND, NOR, etc.), flip-flops (Flip-Flop), multiplexers (Mux), decoders (Decoders), etc.

[0081] In this embodiment, the target commonality identification part is used to express the common characteristics of all standard cells in the corresponding first standard cell set of different cell types, that is, the pin configuration standards and the layout rules of the board; the target commonality module is constructed based on extracting the target commonality identification part from the standard cells in the first standard cell set, and is composed of circuit structure, pin arrangement, power and ground connection points, etc.

[0082] In this embodiment, the CAD tool can be used for circuit design and simulation; the initial array framework is a framework constructed by editing the initial array parameters using the CAD tool, and is used to place target common modules, wherein the initial array parameters include the number of rows, the number of columns, the spacing, etc.

[0083] In this embodiment, the connecting lines include power lines, ground lines, signal lines, etc.; the addition of parametric design functions is to make the template more flexible and reusable, including functions such as adjusting array initial parameters, module spacing, connecting line width, and number of units; the initial editing unit template is a template built based on CAD tools that allows users to configure standard units of different numbers and configurations through editing.

[0084] The beneficial effect of the above technical solution is: by adopting CAD tools and utilizing the identified target commonality to identify the partial design to obtain the initial editing unit template, it is possible to reduce the original investment cost, reduce the layout time, improve the efficiency and reliability of integrated circuit design, and promote the standardization and reuse of the design.

[0085] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, which performs simulation test on an initial edit unit template, and optimizes and adjusts the initial edit unit template according to the test result to obtain an editable unit template, including:

[0086] Step 11: Set the simulation input data and expected output results;

[0087] Step 12: Import the initial edit unit template into the set simulation tool, then input the set simulation input data to run the simulation, and obtain the running output result;

[0088] Step 13: If there is an error exception report in the running output result, it is determined that the initial editing unit template in the current simulation process is running abnormally;

[0089] According to the error type, location and cause in the error exception report, the initial editing unit template is adjusted and the simulation is run again to obtain the running output result;

[0090] If there is no error exception report in the current running output result, the initial editing unit template is optimized by using the performance evaluation result obtained by analyzing the running output result and the expected output result to obtain an editable unit template;

[0091] Step 14: If there is no error or exception report in the running output result, it is determined that the initial editing unit template runs normally during the current simulation process;

[0092] By using the performance evaluation result obtained by analyzing the running output result and the expected output result, the current initial editing unit template is optimized to obtain an editable unit template;

[0093] Step 15: Repeat steps 11 to 14 to perform a preset number of template operation simulations and performance tests under different application scenarios, and iteratively optimize the initial editing unit template to obtain an editable unit template;

[0094] Step 16: Summarize the editable unit templates of all unit types in different application scenarios, create corresponding standard unit editing template files, and save them to the preset editable unit template library.

[0095] In this embodiment, the simulation input data is set to include analog signals, such as voltage and current, digital signals, such as switch status, code values, and file data, such as configuration files, data files, etc.; the expected output results include estimated analog signal waveforms, estimated digital signal statuses, and estimated performance parameter values; the simulation tool is set to be a simulation tool selected in advance, such as CloudSim; the running output results include analog signal waveforms, digital signal statuses, and performance parameter data, etc.; the error exception report consists of the exception type, the location where the exception occurs, and the cause of the exception.

[0096] In this embodiment, the performance evaluation result is composed of a performance evaluation index of a possible normal performance parameter and a corresponding optimization priority, wherein the possible normal performance parameter refers to a performance parameter whose first performance parameter difference is not less than a corresponding parameter data threshold; the first performance parameter difference is obtained by comparing the performance parameter data in the running output result with the expected output result; the performance parameters include power consumption, delay and area; and the parameter data threshold is set in advance.

[0097] In this embodiment, the editable unit template is a unit template obtained by iteratively optimizing the initial edit template; application scenarios include high-performance processors, low-power Internet of Things devices, embedded systems, etc.

[0098] In this embodiment, the preset number of times is set in advance; the standard cell editing template file includes an editable cell template file designed using a CAD tool, a template usage document, and a user guide; the preset editable cell template library is composed of standard cell editing template files of all standard cell types, which can be reused for subsequent designs.

[0099] The beneficial effect of the above technical solution is: by using simulation tools to perform simulation tests on the initial editing unit template under different application scenarios and different input conditions, and optimizing and adjusting the initial editing unit template according to the test results, iterative optimization of the initial editing unit template is achieved, thereby obtaining an editable unit template, and effectively ensuring the reliability of the editable unit template.

[0100] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, which optimizes the current initial editing unit template by analyzing the performance evaluation result obtained by combining the running output result with the expected output result to obtain an editable unit template, including:

[0101] Compare the running output results with the expected output results to obtain performance comparison results;

[0102] Comparing the first performance parameter difference in the performance comparison result with a parameter data threshold corresponding to the first performance parameter extracted from a preset performance-threshold mapping table;

[0103] If the first performance parameter difference is less than the corresponding parameter data threshold, the current first performance parameter is marked as a normal performance parameter;

[0104] Otherwise, marking the current first performance parameter as a possible normal performance parameter;

[0105] At this time, if there are zero possible normal performance parameters, it is determined that the initial editing unit template does not need to be optimized and adjusted, and the current initial editing unit template is output as an editable unit template;

[0106] If there is only a single possible normal performance parameter, the optimization direction that matches the current possible normal performance parameter is used as the target optimization direction;

[0107] Acquire a template optimization strategy that matches the target optimization direction;

[0108] If there are multiple possible normal performance parameters, calculating the performance evaluation index of each possible normal performance parameter based on the first performance parameter difference and the parameter data threshold;

[0109] Outputting the performance evaluation index and the optimization priority set of the corresponding possible normal performance parameters determined according to the performance evaluation index as the performance evaluation result;

[0110] A machine learning algorithm is introduced to train a model using a preset amount of unit historical optimization data extracted from a standard unit optimization database as training data to obtain an optimization generation model;

[0111] Extracting key feature data of the current initial editing unit template and inputting them into the optimization generation model together with the performance evaluation result to obtain a model optimization strategy;

[0112] The template optimization strategy is used in combination with the shared device to optimize and adjust the current initial editing unit template to obtain an editable unit template.

[0113] In this embodiment, the operation output result includes an analog signal waveform, a digital signal state, and performance parameter data, etc.; the expected output result includes an estimated analog signal waveform, an estimated digital signal state, and an estimated performance parameter value; the performance comparison result is obtained by comparing the operation output result with the expected output result; the first performance parameter difference refers to the difference between the performance parameter data in the operation output result and the estimated performance parameter value in the expected output result; the preset performance-threshold mapping table is set in advance.

[0114] In this embodiment, for example, the first performance parameter differences corresponding to the performance parameters a1 and a2 in the performance comparison result 1 are b1 and b2 respectively, where b1 is less than the parameter data threshold of the performance parameter a1, and b2 is equal to the parameter data threshold of the performance parameter a2. At this time, the performance parameter a1 is marked as a normal performance parameter, and the performance parameter a2 is marked as a possible normal performance parameter.

[0115] In this embodiment, the optimization direction includes size optimization, layout optimization, power consumption optimization and delay optimization; the template optimization strategy refers to the corresponding optimization method of the optimization direction, for example, the optimization strategy of the power consumption optimization direction refers to reducing the size of the transistor, reducing the power supply voltage or using low-power design technology, such as multi-threshold voltage technology, gated clock, etc. to reduce power consumption; the performance evaluation index is used to characterize the performance of the current possible normal performance parameters; the performance evaluation result is composed of the performance evaluation index of the possible normal performance parameter and the corresponding optimization priority, wherein the possible normal performance parameter refers to the performance parameter whose first performance parameter difference is not less than the corresponding parameter data threshold; the performance parameters include power consumption, delay and area; the parameter data threshold is extracted from a preset performance-threshold mapping table.

[0116] In this embodiment, the machine learning algorithm refers to an important component of the field of artificial intelligence, and its core is to acquire new knowledge or skills by simulating or realizing human behavior, reorganizing the existing knowledge structure, and continuously improving its own intelligence; the standard cell optimization database is used to store the unit historical optimization data of various standard cells, wherein the unit historical optimization data includes standard cell basic information, unit layout design data, performance parameter data, and historical optimization method record data, etc., wherein the standard cell basic information includes standard cell name, cell type, application scenario, etc.

[0117] In this embodiment, the preset quantity is set in advance; the optimization generation model is used to generate the optimization strategy of the standard unit template; the key feature data refers to the standard unit template layout feature data and application scenario data; the shared device refers to the standardized, modular components, modules or technologies that can be reused in multiple circuit designs; the editable unit template is a template obtained by optimizing and adjusting the initial edit unit template.

[0118] The beneficial effects of the above technical solution are: the performance evaluation results are obtained by comparing and analyzing the running output results of the simulated initial editing template with the expected output results; the template optimization strategy generated by the optimization generation model based on the input performance evaluation results is used to optimize and adjust the current initial editing template, which can effectively ensure the reliability and reusability of the unit template.

[0119] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, and the calculation formula of the performance evaluation index is as follows:

[0120] ;in, It is expressed as the performance evaluation index of the i-th possible normal performance parameter; The first performance parameter difference represented as the i-th possible normal performance parameter; denoted as the parameter data threshold of the i-th possible normal performance parameter; It is represented as the parameter importance weight of the i-th possible normal performance parameter in the current application scenario; It is expressed as the comprehensive influence coefficient of the common influencing factors of performance parameters on the performance evaluation of possible normal performance parameters; It is expressed as the value of the jth main influencing indicator of the i-th possible normal performance parameter; It is expressed as the influence coefficient of the jth main influencing indicator of the ith possible normal performance parameter on the performance evaluation of the current possible normal performance parameter.

[0121] In this embodiment, the common influencing factors include material factors, environmental factors and power supply voltage factors; the main influencing indicators refer to the main influencing factors of the performance parameters of standard cells of different cell types, where the performance parameters refer to power consumption, area and delay.

[0122] In this embodiment, the main influencing indicators of power consumption include circuit operating frequency, short-circuit power consumption, transistor leakage current, etc.; the main influencing indicators of area include circuit design complexity, number of transistors, and packaging and interconnection requirements; the main influencing indicators of delay include input and output loads, device threshold voltage, clock frequency, and load capacitance.

[0123] The beneficial effect of the above technical solution is: by calculating and analyzing the combined effects of the first performance parameter difference and the influencing factors of different performance parameters, a performance evaluation index is obtained to characterize the running performance of the current initial editing template and lay the foundation for generating a template optimization strategy for the current initial editing template.

[0124] The embodiment of the present invention provides an efficient integrated circuit design method based on shared devices, which calls a matching editable unit template for editing and modification according to the design requirements of the integrated circuit, including:

[0125] Based on the design requirements of integrated circuits, obtain the current standard cell type requirements and cell size requirements;

[0126] Retrieving an editable unit template file matching the standard unit type requirement unit type from a preset editable unit template library, and establishing a unit template to be edited;

[0127] According to the unit size requirement, the unit template to be edited is edited and then used for integrated circuit design.

[0128] In this embodiment, the integrated circuit is composed of transistors, transformers, capacitors, resistors and other elements to realize circuit functions such as acquisition, processing, transmission and amplification of control signals; the design requirements of the integrated circuit include functional requirements, performance requirements, circuit design requirements and cost requirements, etc., among which the circuit design requirements include standard unit type requirements, unit size requirements, etc.

[0129] In this embodiment, the standard cell type requirement refers to the standard cell type required for the current integrated circuit design, wherein the standard cell types include logic gate units, drive units, timing units, operation units, mixed logic units, I / O units and special function units; the unit size requirement refers to the quantity requirement, width and height requirement and pin position requirement for the standard cells, etc.

[0130] In this embodiment, the preset editable cell template library is composed of standard cell editing template files of all standard cell types and can be reused for subsequent designs; the cell template to be edited is a template established using an editable cell template file that matches the required cell type of the standard cell type.

[0131] The beneficial effect of the above technical solution is: by retrieving the corresponding editable unit template file from the preset editable unit template library based on the design requirements of the integrated circuit, establishing the unit template to be edited and editing and modifying it for integrated circuit design, it is possible to reduce the original investment cost and layout time while effectively improving the efficiency and quality of integrated circuit design and ensuring high circuit performance.

[0132] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An efficient integrated circuit design method based on shared devices, characterized in that: include: Step 1: Obtain key data information of all standard cells, and perform commonality analysis to obtain the target commonality identification part; Step 2: Designing an initial editing unit template using the target commonality recognition part; Step 3: Performing simulation test on the initial editing unit template, and optimizing and adjusting the initial editing unit template according to the test result to obtain an editable unit template; Step 4: According to the design requirements of the integrated circuit, call up the matching editable unit template for editing and modification; Among them, the key data information of all standard units is obtained, and commonality analysis is performed to obtain the target commonality identification part, including: Obtain data information of all standard units and extract key data information; Performing commonality analysis on the remaining key data in the key data information except the unit type to obtain all commonality parts of the units; Dividing all standard cells by using the cell types in the key data information to obtain a first standard cell set, and marking corresponding cell types; Performing commonality analysis on key data information of all standard cells in the first standard cell set to obtain a specific commonality part; Aggregating the specific commonality part with all commonality parts of the units to obtain a target commonality part, and treating it as a target commonality identification part corresponding to the first standard unit set; The method of designing an initial editing unit template using the target commonality recognition part includes: Generate a target commonality module by extracting a target commonality identification portion from standard cells in the first standard cell set; Use CAD tools to create an initial array frame, place the target common module into the initial array frame, and then add connection lines and pins; Add and utilize parametric design capabilities to complete the design of the initial editing unit template; The initial editing unit template is simulated and tested, and the initial editing unit template is optimized and adjusted according to the test result to obtain an editable unit template, including: Step 11: Set the simulation input data and expected output results; Step 12: Import the initial edit unit template into the set simulation tool, then input the set simulation input data to run the simulation, and obtain the running output result; Step 13: If there is an error exception report in the running output result, it is determined that the initial editing unit template in the current simulation process is running abnormally; According to the error type, location and cause in the error exception report, the initial editing unit template is adjusted and the simulation is run again to obtain the running output result; If there is no error exception report in the current running output result, the initial editing unit template is optimized by using the performance evaluation result obtained by analyzing the running output result and the expected output result to obtain an editable unit template; Step 14: If there is no error or exception report in the running output result, it is determined that the initial editing unit template runs normally during the current simulation process; By using the performance evaluation result obtained by analyzing the running output result and the expected output result, the current initial editing unit template is optimized to obtain an editable unit template; Step 15: Repeat steps 11 to 14 to perform a preset number of template operation simulations and performance tests under different application scenarios, and iteratively optimize the initial editing unit template to obtain an editable unit template; Step 16: Summarize the editable unit templates of all unit types in different application scenarios, create corresponding standard unit editing template files, and save them to the preset editable unit template library.

2. The method for efficient design of integrated circuits based on shared devices according to claim 1, characterized in that: The key data information includes unit type, pin configuration and layout.

3. The method for efficient design of integrated circuits based on shared devices according to claim 1, characterized in that: By using the performance evaluation results obtained by analyzing the running output results and the expected output results, the current initial editing unit template is optimized to obtain an editable unit template, including: Compare the running output results with the expected output results to obtain performance comparison results; Comparing the first performance parameter difference in the performance comparison result with a parameter data threshold corresponding to the first performance parameter extracted from a preset performance-threshold mapping table; If the first performance parameter difference is less than the corresponding parameter data threshold, the current first performance parameter is marked as a normal performance parameter; Otherwise, marking the current first performance parameter as a possible normal performance parameter; At this time, if there are zero possible normal performance parameters, it is determined that the initial editing unit template does not need to be optimized and adjusted, and the current initial editing unit template is output as an editable unit template; If there is only a single possible normal performance parameter, the optimization direction that matches the current possible normal performance parameter is used as the target optimization direction; Acquire a template optimization strategy that matches the target optimization direction; If there are multiple possible normal performance parameters, calculating the performance evaluation index of each possible normal performance parameter based on the first performance parameter difference and the parameter data threshold; Outputting the performance evaluation index and the optimization priority set of the corresponding possible normal performance parameters determined according to the performance evaluation index as the performance evaluation result; A machine learning algorithm is introduced to train a model using a preset amount of unit historical optimization data extracted from a standard unit optimization database as training data to obtain an optimization generation model; Extracting key feature data of the current initial editing unit template and inputting them into the optimization generation model together with the performance evaluation result to obtain a model optimization strategy; The template optimization strategy is used in combination with the shared device to optimize and adjust the current initial editing unit template to obtain an editable unit template.

4. The method for efficient design of integrated circuits based on shared devices according to claim 3, characterized in that: The calculation formula of the performance evaluation index is as follows: ;in, It is expressed as the performance evaluation index of the i-th possible normal performance parameter; The first performance parameter difference represented as the i-th possible normal performance parameter; denoted as the parameter data threshold of the i-th possible normal performance parameter; It is represented as the parameter importance weight of the i-th possible normal performance parameter in the current application scenario; It is expressed as the comprehensive influence coefficient of the common influencing factors of performance parameters on the performance evaluation of possible normal performance parameters; It is expressed as the value of the jth main influencing indicator of the i-th possible normal performance parameter; It is expressed as the influence coefficient of the jth main influencing indicator of the ith possible normal performance parameter on the performance evaluation of the current possible normal performance parameter.

5. The method for efficient design of integrated circuits based on shared devices according to claim 1, characterized in that: According to the design requirements of the integrated circuit, the matching editable unit template is retrieved for editing and modification, including: Based on the design requirements of integrated circuits, obtain the current standard cell type requirements and cell size requirements; Retrieving an editable unit template file matching the standard unit type requirement unit type from a preset editable unit template library, and establishing a unit template to be edited; According to the unit size requirement, the unit template to be edited is edited and then used for integrated circuit design.

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