Wafer face-to-face fusion bonding deep silicon via formation method

Abstract

The present invention belongs to the field of semiconductor device manufacturing, and in particular, relates to a method for forming deep silicon vias by face-to-face melt bonding of wafers. The method comprises: applying a photomask from the top of the face-to-face melt bonding wafer, that is, one side of the second wafer, and forming a plurality of deep silicon vias as the first deep silicon via TSV1 and the second deep silicon via TSV2 from the outside to the inside by etching; removing etching byproducts by semiconductor ashing and semiconductor cleaning, thereby removing the excess part of the first deep silicon via TSV1, thereby completing the complete etching formation of the large-size TSV1 and the small-size TSV2 in one step. Through the method of the present invention, the melt bonding is adopted, the process is simple and efficient, and the face-to-face bonding process does not require the aid of a carrier wafer, which greatly reduces the process flow and cost; and only one deep silicon via + one thin film process is required, and compared with the traditional method, the mask production and process costs are halved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for forming a wafer face-to-face fusion-bonded deep silicon through-hole. Background Art

[0002] In the field of semiconductor device manufacturing, the advantage of face-to-face wafer stacking over back-to-face bonding is that wafer stacking can be completed without the aid of a carrier wafer. However, when using back-to-back stacking, both melt bonding and hybrid bonding only require one deep silicon via (TSV) + one thin film (TM) production process, which can avoid the dilemma of two deep silicon vias + two thin film productions brought about by face-to-face melt bonding. However, the face-to-face stacking melt bonding method requires two deep silicon via processes to complete the electrical connection and lead-out of the stacked wafers. There is currently no better solution to this problem. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention provides a method for forming a wafer-to-wafer melt-bonded deep silicon via, wherein the wafer-to-wafer melt-bonded deep silicon via at least includes a first deep silicon via TSV1 connected to a metal layer of a first wafer to connect an electrical signal of the first wafer to an external part, and a second deep silicon via TSV2 connected to a metal layer of a second wafer to connect an electrical signal of the second wafer to an external part, wherein the first wafer serves as a bottom wafer and the second wafer serves as a top wafer, and the wafer-to-wafer melt-bonded deep silicon via forming method comprises the following steps: Step S1, applying a photomask from the top of the wafers to be melt-bonded face to face, i.e., one side of the second wafer, and forming a first deep silicon via TSV from the outside to the inside by etching 1 and a plurality of deep silicon through vias TSV2, wherein the mask is designed to design the critical dimension of the edge portion of TSV1 to be the same as the critical dimension of TSV2, and the critical dimension of the middle portion of TSV1 is slightly larger, so that the inner region with a larger size is etched to the bottom first, and a notching (also known as a "notch") morphology appears at the bottom and is laterally connected, waiting for the hole with a small edge size to be etched to the bottom and connected with the laterally etched portion in the middle, so as to finally realize the etching formation of the large-sized TSV1 hole, and the Si etching of the edge portion of TSV1 and TSV2 can reach the bottom at the same time; step S2, removing the etching byproducts through semiconductor ashing (Asher) and semiconductor cleaning (Wet Clean), so as to remove the redundant portion in the first deep silicon through via TSV1, so as to complete the complete etching formation of the large-sized TSV1 and the small-sized TSV2 in one step.

[0004] In addition, preferably, the present invention provides a method for forming deep silicon through-holes by face-to-face fusion bonding of wafers. In step S1, the design specifications of the mask used to form TSV1 and TSV2 are as follows: the diameter of the middle hole is X, and the bottom side-digging distance produced by etching is D, then the final opening diameter that can be obtained is X+2D, wherein the distance from the edge hole to the edge of the middle hole is controlled to be equal to the side-digging distance, and the design size of the mask is obtained according to the longitudinal etching rate corresponding to different hole diameters, the lateral etching rate reaching the bottom, and the depth of silicon to be etched.

[0005] In addition, preferably, the present invention provides a method for forming deep silicon through-holes by face-to-face melt bonding of wafers, in which the side-excavation distance D is designed to make the time for the middle hole and the small hole at the edge to reach the bottom consistent, and at the same time, the critical size of the outermost circle mask of TSV1 is required to be consistent with the critical size of the TSV2 mask, and the etching completion time of the middle hole and the small hole is consistent, so as to ensure that the large hole can be accurately formed in the end.

[0006] In addition, preferably, the present invention provides a wafer face-to-face melt-bonded deep silicon via formation method. In step S1, the design of the mask used to form TSV1 and TSV2 needs to take into account that after Si etching is completed, the time for the large hole to reach the deepest metal is consistent with the time for the small hole to reach the shallowest metal.

[0007] In addition, preferably, the present invention provides a method for forming deep silicon vias by face-to-face melt bonding of wafers. In step S1, the design of the mask used to form TSV1 and TSV2 needs to adjust the etching recipe according to the difference in film thickness of the two wafers to ensure that the time spent on etching TSV1 and TSV2 to their respective metal layers is equal.

[0008] In addition, preferably, the present invention provides a wafer face-to-face melt-bonded deep silicon via formation method, wherein the structural difference between the first deep silicon via TSV1 and the second deep silicon via TSV2 is only in the thickness of the bottom dielectric film layer, while the top dielectric film layer thickness and silicon thickness are the same.

[0009] In addition, preferably, the present invention provides a method for forming a wafer face-to-face melt-bonded deep silicon through-hole, after the etching of the first deep silicon through-hole TSV1 and the second deep silicon through-hole TSV2 is completed, conventional barrier layer and seed layer deposition, copper electroplating, surface copper surface chemical mechanical polishing, annealing, and surface copper surface chemical mechanical polishing are performed in sequence to complete the production of a TSV closed loop (Loop).

[0010] The method of the present invention adopts melt bonding, which is simple and efficient. In addition, the face-to-face bonding process does not require the aid of a carrier wafer, which greatly reduces the process flow and cost. Only one TSV + one TM process flow is required, and compared with the traditional method, the mask production and process costs are halved.

[0011] In other words, the present invention is a process integration solution developed for face-to-face melt-bonded wafer-level stacking. The specially designed TSV closed-loop mask is used in combination with the conventional TSV closed-loop manufacturing process to achieve one TSV + one TM process flow, achieving the effect ultimately achieved by the conventional process of two TSV + two TM process flows. Finally, the connection and lead-out of the electrical signals of the stacked wafers are completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram showing a hybrid key and flow in the prior art.

[0013] Figure 2 A schematic diagram showing a hybrid bond and a process in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0014] Figure 3 A schematic diagram showing the process of etching film layers required for forming TSV in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0015] Figure 4 A schematic diagram showing a TSV closed-loop process flow in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0016] Figure 5 A schematic diagram showing a TM process flow in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0017] Figure 6 A schematic diagram showing electrical connections in two TM processes in a method for forming deep through silicon vias by wafer face-to-face fusion bonding according to an embodiment of the present invention.

[0018] Figure 7 A schematic diagram showing lateral etching at the interface between Si and ONO in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0019] Figure 8 A schematic diagram showing a two-in-one etching process and a mask manufacturing process in a wafer face-to-face fusion bonding deep silicon via formation method according to an embodiment of the present invention.

[0020] Fig. 9A schematic diagram showing the characteristic morphology of TSV edge ripples in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention.

[0021] Fig. 10A A schematic diagram showing the side view angle relationship of the mask design dimensions used in the TSV formation method of wafer face-to-face fusion bonding deep silicon via according to one embodiment of the present invention.

[0022] Fig. 10B A schematic diagram showing the top view angle relationship of the mask design dimensions used in the TSV formation method of wafer face-to-face fusion bonding deep silicon via according to one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Other embodiments or variations obtained based on the embodiments in the present application by ordinary technicians in this field without creative work are all within the scope of protection of this application.

[0024] The present invention develops a process integration solution for face-to-face fusion-bonded wafer-level stacking. The specially designed TSV closed-loop mask is used in combination with the conventional TSV closed-loop manufacturing process to achieve one TSV + one TM process flow, achieving the effect ultimately achieved by the conventional process of two TSV + two TM process flows. Finally, the electrical signal connection and lead-out of the stacked wafers are completed.

[0025] At present, the permanent bonding process of advanced packaging is divided into fusion bonding and hybrid bonding. Hybrid bonding can realize the connection between wafer structures and electrical connection at the same time. After the wafer thinning process, deep silicon vias (TSV) are made to lead out the electrical signals of the upper wafer. Since hybrid bonding has realized the electrical connection between the upper and lower wafers, only hybrid bonding between wafers + deep silicon via process are needed to realize the lead-out of stacked wafer electrical signals. The process flow is as follows: Figure 1 shown.

[0026] When the wafers are previously melt-bonded, two deep through-silicon vias (TSVs) need to be made to connect the metal layers of wafer 1 and wafer 2 respectively, so as to achieve the effect of electrically connecting the two melt-bonded wafers. Figure 2 shown.

[0027] If hybrid bonding is used, a complete Damascus process is required to make hybrid bonding vias / pads. At this time, a series of related machines such as chemical vapor deposition (CVD), photolithography (Litho), etching (Etch), wet process (WET), physical vapor deposition (PVD), electropolishing (ECP), chemical mechanical polishing (CMP) are required. Compared with the subsequent TSV Damascus process, the critical dimensions of the Damascus process here are more refined, so the technical difficulty is higher; at the same time, compared with melt bonding, hybrid bonding needs to achieve both inter-wafer structure and electrical connectivity, and has higher requirements for parameters such as the amount of Cu dish-shaped defects (Dishing amount) at the bonding interface, dielectric layer morphology (Profile) control, and interface cleanliness. Therefore, the overall process flow is more complicated than melt bonding; but the subsequent deep silicon through-hole only needs to connect the upper wafer metal layer, and the process here is simpler than the melt bonding stacking method.

[0028] If melt bonding is used, since the bonding interface is a single dielectric layer, the morphology requirements of the bonding interface are relatively low. At the same time, since bonding only needs to achieve structural connection, the requirements for particles are also lower. Compared with hybrid bonding, melt bonding has a lower process difficulty in bonding; but the subsequent process of electrically connecting the stacked wafers is more complicated. It is necessary to complete the production of silicon through vias twice. The structure of silicon through vias is relatively complex. The original structure has Si and the middle ONO dielectric layer (Oxide-Nitride-Oxide, also known as "oxide-nitride-oxide"). Considering the type and thickness of the film layer that needs to be passed through, a certain thickness of ONO dielectric layer needs to be deposited on the top as a hard mask layer.

[0029] Therefore, the film layers that TSV needs to etch through are ONO dielectric layer, Si, and ONO dielectric layer. Figure 3 shown.

[0030] The more complete process flow of TSV is:

[0031] 1. Top dielectric mask layer deposition;

[0032] 2. Photolithography;

[0033] 3. Dielectric mask layer etching;

[0034] 4. Silicon etching;

[0035] 5. Bottom dielectric layer etching;

[0036] 6. Insulating oxide layer deposition;

[0037] 7. Bottom thermal oxide layer etching;

[0038] 8. Barrier layer and seed layer deposition;

[0039] 9. Copper electroplating;

[0040] 10. Chemical mechanical polishing of copper surface;

[0041] 11. Annealing;

[0042] 12. Chemical mechanical polishing of copper surface.

[0043] TSV closed-loop process flow Figure 4 shown.

[0044] In summary, a TSV process includes many process steps. Since the depth of the ONO dielectric film layer at the bottom of wafer 2 and wafer 1 is different, usually the thickness difference is a few microns, so the conventional solution requires two steps of through silicon via etching to complete, which is equivalent to repeating the above process flow, and the overall number of process flows has increased significantly. At the same time, because the dielectric hard mask layers deposited by the TSV process are relatively thick, after the second TSV process is completed in the conventional process, the remaining hard mask layer on the top of the second TSV is relatively thick (usually several microns thick). The subsequent use of the Damascus process to make the metal layer to electrically connect the two TSVs is likely to cause machine arcing (Arcing) or wafer plasma induced damage (Wafer PID), thereby damaging the devices on the wafer. The schematic diagram is as follows Figure 5 If you want to eliminate this effect, you need to produce two masks and perform the Damascus process step by step. In summary, four Damascus processes (two TSV and two TM) are required to complete all processes. Figure 6 shown.

[0045] The stacking method involved in the above bonding method is face-to-face wafer stacking. Compared with the back-to-back bonding method, the advantage of this solution is that the wafer stacking can be completed without the help of a carrier wafer, so we adopt a face-to-face stacking method. When the back-to-back stacking method is adopted, both melt bonding and hybrid bonding only require one TSV + one TM production process, which can avoid the dilemma of two TSV + two TM productions brought about by face-to-face melt bonding. However, if the face-to-face stacking melt bonding method is adopted, two TSV processes are required to complete the electrical connection and lead-out of the stacked wafers. There is currently no better solution to this problem.

[0046] The present invention develops a process integration solution for face-to-face fusion-bonded wafer-level stacking. The specially designed TSV closed-loop mask is used in combination with the conventional TSV closed-loop manufacturing process to achieve one TSV + one TM process flow, achieving the effect ultimately achieved by the conventional process of two TSV + two TM process flows. Finally, the electrical signal connection and lead-out of the stacked wafers are completed.

[0047] The advantages of using this process are:

[0048] 1. Compared with hybrid bonding, it has the advantages of simple and efficient melt bonding process;

[0049] 2. The face-to-face bonding process does not require the use of a carrier wafer, which greatly reduces the process flow and cost;

[0050] 3. Only one TSV + one TM process is required, and the mask production and process costs are halved compared to the original two TSV + two TM process.

[0051] Plasma dry etching is used in the entire TSV process, and the etched morphology is a hole. Therefore, the larger the CD (critical dimension) of the hole, the faster the internal ion concentration and exchange rate, and the faster the final etching rate. The TSV of the bottom wafer 1 has a longer etching distance than the TSV of the top wafer 2, so we designed the CD of the TSV of wafer 1 to be larger. Since the TSV etching rate of wafer 1 is faster, the TSV of wafer 1 can etch a longer distance in the same etching time, and finally reach the etching position at the same time as the TSV of wafer 2, and stop on their respective metal layers, completing the etching of the two TSVs, and continuing the subsequent TSV closed-loop process to complete the entire TSV production.

[0052] A careful comparison of the structural differences between TSV1 and TSV2 shows that the thickness of the top dielectric film layer (Top ONO) and the thickness of silicon (Si) are the same for both, and only the thickness of the bottom dielectric layer (Bottom ONO) is different. At the same time, due to the switching of the three interfaces in the middle, the mask size of TSV1 cannot be simply designed to be larger. Because in the process of silicon etching, TSV1 etches faster and the etching of TSV1 Si is completed first. At this time, TSV2 Si has not been etched yet, which will cause the appearance of side-excavation morphology at the bottom of TSV1 Si; this will cause problems such as abnormalities in the subsequent Bottom ONO ET etching and the inability to deposit the barrier seed layer (Barrier Seed) normally.

[0053] Therefore, we cannot simply enlarge the CD of TSV1 to achieve our goal. We take advantage of the phenomenon that side digging occurs when the Si etching reaches the Bottom ONO interface. Figure 7 When several holes are connected with each other due to side digging at the bottom, a larger hole will be formed.

[0054] In the process of mask design, there are two important parameters, namely the CD of TSV and the size between TSVs with different CDs. In order to ensure that the bottom edge of the large-sized Si of the final etched TSV1 does not have a side-excavation morphology, we designed the edge CD of TSV1 to be the same as the CD of TSV2. The CD of the middle part of TSV1 is slightly larger, so that the larger inner area is etched to the bottom first, and the side-excavation morphology appears when it is etched to the bottom, and the side is connected. The holes with smaller edge sizes have not been etched to the bottom at this time. When the smaller edge size is etched to the bottom, it is connected with the side-etched part in the middle, so that the etching of the large-sized TSV1 hole is finally completed. Since the edge CD of TSV1 is consistent with the CD of TSV2, the edge of TSV1 and the Si etching of TSV2 reach the bottom at the same time. Then, in the process of ashing and cleaning to remove etching byproducts, the excess part of TSV1 is removed, thereby completing the etching of large-sized TSV1 and small-sized TSV2.

[0055] After silicon etching is completed, large-sized TSV1 and small-sized TSV2 holes are formed. Since large-sized holes are etched faster, we designed the mask size and adjusted the formula in advance according to the difference in film thickness between the two wafers, ultimately ensuring that TSV1 and TSV2 are etched to their respective metal layers at the same time. The etching process and mask production diagram are shown in the figure below. Figure 8 shown.

[0056] After TSV etching is completed, conventional barrier layer, seed layer deposition, copper electroplating, surface copper surface chemical mechanical polishing, annealing, and surface copper surface chemical mechanical polishing are performed in sequence; the TSV closed loop can be completed. Since the two TSVs are at the same height, there is no arcing (Arcing) or wafer plasma induced damage (Wafer PID) caused by the height difference in the later stage. In the future, only a conventional TM layer is needed to connect the two TSVs, which saves a TM layer compared to the original.

[0057] The present invention is mainly aimed at face-to-face fusion-bonded wafer-level stacking, and the developed one TSV closed-loop process + one TM process process realizes the connection and lead-out of stacked wafer electrical signals.

[0058] In addition, as a preferred embodiment of the present invention, the edge hole CD of the large-sized TSV is consistent with that of the small-sized TSV, so as to ensure that the two can be etched to the bottom of Si at the same time, so as to ensure that the outermost sides of the large and small TSVs do not have side digging, so as to ensure the etching morphology of TSV Si.

[0059] In addition, as a preferred embodiment of the present invention, in the large-sized TSV holes, the middle size should be larger than the edge size to ensure that the middle large size is etched to the bottom first, and then side etching occurs. After the edge small-sized TSV is etched to the bottom, a connection is formed and the excess part can be removed.

[0060] In addition, as a preferred embodiment of the present invention, the hole CD, spacing and arrangement inside the large-size TSV need to be determined according to its own formula and film layer structure, and preliminary experiments are required to collect experimental data.

[0061] In addition, as a preferred embodiment of the present invention, this process integration scheme is applicable to the Bottom ONO etching of different depths of stacked wafers, and is not limited to fusion-bonded stacked wafers. Other stacking methods can also adopt this scheme.

[0062] In addition, as a preferred embodiment of the present invention, after the TSV process is completed, the electrical properties of the stacked wafers can be led out by using Cu, Al pads, bumps, etc.

[0063] In addition, as a preferred embodiment of the present invention, the TSV etched hole morphology finally formed by this solution, according to the process characteristics, the TSV edge has a wavy characteristic morphology, such as Fig. 9 shown.

[0064] In addition, if Fig. 10A and Fig. 10B As shown, Fig. 10A and Fig. 10B Schematic diagrams showing the relationship between the design dimensions of a mask used for TSV in a wafer face-to-face fusion bonding deep through silicon via formation method according to an embodiment of the present invention at a side view angle and a top view angle, respectively.

[0065] In addition, as a preferred embodiment of the present invention, it is necessary to ensure that the CD of the hole at the outermost edge of the large hole TSV1 is consistent with that of the small hole TSV2, so as to ensure that the small hole at the edge of the large hole TSV1 and the small hole TSV2 reach the bottom of Si at the same time and complete the etching to ensure that there is no side-excavation morphology at the edge of the hole finally formed.

[0066] In addition, as a preferred embodiment of the present invention, the hole CD in the middle of the large hole TSV1 should be large to ensure that it can reach the bottom first and dig sideways, so that when the small hole TSV1 at the edge reaches the bottom, it can encounter the side digging of the large hole in the middle of TSV1, thus forming a large TSV1 hole.

[0067] For example, if the diameter of the middle hole is X and the side cut distance is D, the overall diameter can be X + 2D. Therefore, the distance between the edge holes and the edge of the middle hole must be equal to the side cut distance.

[0068] In addition, as a preferred embodiment of the present invention, the longitudinal etching rate corresponding to different hole diameters and the lateral etching rate to the bottom are calculated, and the depth of silicon to be etched is matched to design the size of the mask according to the above calculation method.

[0069] In addition, it should be noted that CD is the abbreviation of critical dimension, which refers to the critical dimension in Fab. Specifically for TSV holes, CD refers to the diameter. The specific range is not limited, but Fig. 10A and 10B As shown, the relationship between the designed spacing D, the large hole diameter X1, and the small hole diameter X2 is that the side-digging distance D is consistent with the time when the small hole etching is completed to ensure that the large hole can be perfectly formed. If the side-digging distance is less than D, the small hole has been etched to the bottom, and the edge of the large hole formed as a whole will be side-digging. If the side-digging distance is greater than D, the small hole has not reached the bottom, and the large hole formed as a whole will still have side-digging at the edge. Therefore, it is only necessary to limit the designed distance D. In the actual etching process, a certain side-digging distance D is consistent with the time when the edge small hole X2 reaches the bottom. In addition, the CD of the outermost mask of TSV1 can be required to be consistent with the CD of the TSV2 mask.

[0070] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0071] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0072] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0073] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A wafer face-to-face fusion bonding deep silicon via formation method, characterized in that: The wafer face-to-face fusion-bonded deep silicon via at least includes a first deep silicon via connected to a metal layer of a first wafer to connect an electrical signal of the first wafer to an external part and a second deep silicon via connected to a metal layer of a second wafer to connect an electrical signal of the second wafer to an external part, the first wafer is used as a bottom wafer, and the second wafer is used as a top wafer. The wafer face-to-face fusion-bonded deep silicon via forming method includes the following steps: Step S1, applying a photomask from the top of the face-to-face melt-bonded wafer, that is, one side of the second wafer, and forming a plurality of deep silicon through holes as the first deep silicon through hole and the second deep silicon through hole from the outside to the inside by etching, wherein the photomask is designed so that the critical size of the first deep silicon through hole at the edge portion is the same as the critical size of the second deep silicon through hole, and the critical size of the first deep silicon through hole in the middle portion is larger, so that the first deep silicon through hole in the middle portion is etched to the bottom first, and a side-excavated morphology appears at the bottom and is laterally connected, waiting for the hole with a small edge size to be etched to the bottom and connected with the laterally etched portion in the middle, thereby finally realizing the hole etching formation of the large-sized first deep silicon through hole, and the etching of the first deep silicon through hole at the edge portion and the second deep silicon through hole can reach the bottom at the same time; Step S2, removing etching byproducts by semiconductor ashing and semiconductor cleaning, thereby removing the redundant portion of the first deep silicon via, thereby completing the complete etching of the large-sized first deep silicon via and the small-sized second deep silicon via in one step.

2. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 1, characterized in that: In step S1, the design specifications of the photomask used to form the first deep silicon via and the second deep silicon via are as follows: the diameter of the middle hole is X, the bottom side recess distance produced by etching is D, and the final opening diameter that can be obtained is X+2D, Among them, the distance from the edge hole to the edge of the middle hole is controlled to be equal to the side-excavation distance, and the design size of the mask is obtained according to the longitudinal etching rate corresponding to different hole diameters, the lateral etching rate reaching the bottom, and the depth of silicon to be etched.

3. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 2, characterized in that: The side-excavation distance is designed so that the time it takes for the middle hole and the small hole on the edge to reach the bottom is consistent. At the same time, the critical size of the first deep silicon via and the second deep silicon via of the outermost mask are required to be consistent, and the etching completion time of the middle hole and the small hole is consistent to ensure that the large hole can be accurately formed in the end.

4. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 1, characterized in that: In step S1 , the design of the photomask for forming the first deep silicon via and the second deep silicon via needs to take into account that after etching is completed, the time at which the large holes reach the deepest metal is consistent with the time at which the small holes reach the shallowest metal.

5. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 1, characterized in that: In step S1, the design of the mask for forming the first deep silicon via and the second deep silicon via needs to adjust the etching recipe according to the difference in film thickness of the two wafers to ensure that the time spent on etching the first deep silicon via and the second deep silicon via to their respective metal layers is equal.

6. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 1, characterized in that: The structural difference between the first deep silicon via and the second deep silicon via is only that the thickness of the bottom dielectric film layer is different, while the thickness of the top dielectric film layer and the silicon thickness are the same.

7. The wafer face-to-face fusion bonding deep silicon via formation method according to claim 1, characterized in that: After the etching of the first deep silicon via and the second deep silicon via is completed, conventional barrier layer and seed layer deposition, copper electroplating, surface copper surface chemical mechanical polishing, annealing, and surface copper surface chemical mechanical polishing are performed in sequence to complete the production of the deep silicon via closed loop.

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