A High-Voltage MOSFET Device with a Double-Groove Structure and Its Manufacturing Method

Abstract

The present invention discloses a high-voltage MOSFET device with a double-groove structure and a manufacturing method thereof. The high-voltage MOSFET device includes an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a P+ masking layer, a first Trench groove, a source electrode, an N+ layer, an insulating layer, and a metal layer that are stacked in sequence. Pwell regions are respectively arranged on both sides of the first Trench groove, and second Trench grooves are respectively arranged on both sides of the two Pwell regions. One end of the Pwell region is connected to the second N-epitaxial layer and the P+ masking layer, and the other end is connected to the N+ layer and the metal layer. Gates are also arranged on both sides of the two second Trench grooves away from the Pwell region. The components of the gates and the source electrodes both include polysilicon. By setting the double grooves and adopting the methods of P+ masking and introducing polysilicon, a breakdown voltage rating of over 300V is achieved. While reducing the design size and production cost, the main parameter performance is comparable to the original design; the polysilicon in the source electrode plays a role in improving the electric field structure, generating a transverse electric field component from the original longitudinal electric field, thereby enhancing the breakdown voltage capability of the product.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a high-voltage MOSFET device with a double-groove structure and a manufacturing method thereof. Background Art

[0002] Currently, in the existing technical field, breakdown voltage is the main parameter for measuring the performance of MOSFET devices and is one of the important indicators for engineers to select products. Generally, for MOSFET devices, the higher the breakdown voltage, the higher the on-resistance, and the larger the design size of the unit cell, which is mainly restricted by the raw material specifications and product design principles.

[0003] Generally, in high-voltage MOSFET devices (usually referring to products with a rated voltage ≥ 300V), most adopt a planar structure design method, resulting in a relatively large overall design size of the chip, and the structural integration of high-voltage MOSFET devices with a large size is not ideal, resulting in fewer effective patterns on the chip.

[0004] In view of this, it is necessary to further improve the structure of the current high-voltage MOSFET device with a double-groove structure. Summary of the Invention

[0005] Therefore, the purpose of the present invention is to at least partly solve the deficiencies in the prior art, and thus propose a high-voltage MOSFET device with a double-groove structure and a manufacturing method thereof.

[0006] To achieve the above purpose, a technical solution adopted by the present invention is as follows:

[0007] The present invention provides a high-voltage MOSFET device with a double-groove structure, including an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a P+ masking layer, a first Trench groove, a source electrode, an N+ layer, an insulating layer, and a metal layer, which are sequentially stacked. Pwell regions are respectively arranged on both sides of the first Trench groove, and second Trench grooves are respectively arranged on both sides of the two Pwell regions far from the first Trench groove. One end of the Pwell region is connected to the second N-epitaxial layer and the P+ masking layer, and the other end is connected to the N+ layer and the metal layer. Gates are arranged on both sides of the two second Trench grooves far from the Pwell region, and the gates are also connected to the insulating layer. The components of the gates and the source electrodes both include polysilicon.

[0008] Further, the width of the high-voltage MOSFET device is 6.5 - 8.5μm.

[0009] Further, the width of the first Trench groove is 1 - 2μm, and the depth is 4 - 5μm.

[0010] Further, the width of the second Trench groove is 0.5 - 1.5 μm, and the depth is 1.5 - 2.5 μm.

[0011] Further, a JFET region is provided at the bottom of the second Trench groove.

[0012] Further, the first N - epitaxial layer and the second N - epitaxial layer are stacked on the front surface of the N+ substrate, and the material of the front surface of the N+ substrate is aluminum. The back surface of the N+ substrate includes a stacked Ti - Ni - Ag structure.

[0013] Further, the present invention also provides a manufacturing method of a high - voltage MOSFET device with a double - trench structure as described in any one of the above, including the following steps:

[0014] S1. Sequentially prepare the first N - epitaxial layer and the second N - epitaxial layer on the N+ substrate by epitaxial growth;

[0015] S2. Form a first Trench groove in the second N - epitaxial layer by means of SiO2 hard mask, photolithography and etching;

[0016] S3. Form a P+ masking layer and an oxide layer in the first Trench groove by ion implantation and thermal oxidation and diffusion;

[0017] S4. Use the oxide layer as a hard mask and form a second Trench groove by photolithography and etching;

[0018] S5. Fill the first Trench groove and the second Trench groove with polysilicon by chemical vapor deposition, and adopt an in - situ doping process to simultaneously realize the doping of polysilicon, form a source electrode and a gate electrode mainly composed of polysilicon, then remove the surface polysilicon by CMP, perform large - area ion implantation and thermal oxidation and diffusion to form a Pwell region;

[0019] S6. Perform large - area ion implantation on the second N - epitaxial layer to form an N+ layer, and adopt an annealing method to activate impurities;

[0020] S7. Grow an insulating layer on the second N - epitaxial layer by chemical vapor deposition;

[0021] S8. Deposit a metal layer on the surface of the insulating layer.

[0022] Further, in step S4, perform large - area ion implantation of phosphorus element and thermal oxidation and diffusion at the bottom of the second Trench groove to form a JFET region, and grow a gate oxide layer.

[0023] Further, in step S8, a source window is formed by photolithography, the corresponding thicknesses of the insulating layer and the oxide layer are removed by wet etching, and then polysilicon is simultaneously removed by dry etching to form a contact hole shallow trench structure, and the contact hole is connected to the metal layer;

[0024] In step S8, a back thinning process is used to deposit a Ti-Ni-Ag structure layer on the back surface of the N+ substrate.

[0025] Further, in step S1, the doping concentration of the first N-epitaxial layer raw material is 1.9e14, and the thickness of the raw material is 65 - 70 μm; the doping concentration of the second N-epitaxial layer raw material is 3.0e15, and the thickness of the raw material is 3 - 8 μm; the doping element is phosphorus;

[0026] In step S3, the ion implantation dose is 1e13, the implantation energy is 80 kev, the implantation element is boron, and the thermal oxidation temperature is 1150 °C;

[0027] In step S4, the ion dose implanted into the second Trench is 2.5e12, the implantation energy is 100 kev, and the thickness of the gate oxide layer is 1100 Å;

[0028] In step S5, the polysilicon thickness is The doping element is phosphorus, and the doping concentration is 2.9e14. The ion implantation element is boron, the implantation dose is 1.5e13, the implantation energy is 60 kev, and the thermal oxidation push-annealing temperature is 1150 °C;

[0029] In step S6, the ion implantation element is arsenic, the implantation dose is 1.0e16, the implantation energy is 100 kev, and the annealing temperature is 950 °C;

[0030] In step S8, the thickness of the insulating layer is 10000 Å, the designed width of the contact hole is 2 - 5 μm, and the designed depth of the contact hole shallow trench is 0.2 - 0.8 μm.

[0031] The present invention provides a high-voltage MOSFET device with a double-groove structure and a manufacturing method thereof. The high-voltage MOSFET device with a double-groove structure includes an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a P+ masking layer, a first Trench groove, a source electrode, an N+ layer, an insulating layer, and a metal layer which are stacked in sequence. Pwell regions are respectively arranged on both sides of the first Trench groove, and second Trench grooves are respectively arranged on both sides of the two Pwell regions away from the first Trench groove. One end of the Pwell region is connected to the second N-epitaxial layer and the P+ masking layer, and the other end is connected to the N+ layer and the metal layer. Gates are arranged on both sides of the two second Trench grooves away from the Pwell region, and the gates are also connected to the insulating layer. The components of the gates and the source electrodes both include polysilicon. By providing the high-voltage MOSFET device of the present invention with a double-groove structure and adopting the methods of P+ masking and introducing polysilicon, a breakdown voltage rating of more than 300V is achieved. While reducing the design size and production cost, this structure enables the main parameter performance to be comparable to the original design. Among them, the polysilicon in the source electrode plays a role in improving the electric field structure, generating a transverse electric field component from the original longitudinal electric field, thereby enhancing the breakdown voltage capability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0033] Figure 1 It is a schematic diagram of the overall structure of the high-voltage MOSFET device with a double-groove structure of the present invention;

[0034] Figure 2 It is a schematic diagram of the design structure of a conventional planar MOSFET device;

[0035] Figure 3 It is a schematic diagram of the electric field distribution of a conventional MOSFET device;

[0036] Figure 4 It is a schematic diagram of the electric field distribution of the high-voltage MOSFET device with a double-groove structure of the present invention;

[0037] Figure 5 It is a schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after epitaxy;

[0038] Figure 6Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a first Trench groove is provided;

[0039] Figure 7 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a P+ masking layer is provided;

[0040] Figure 8 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a second Trench groove is provided;

[0041] Figure 9 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a gate oxide layer (Gate Oxide) and a JFET region are provided;

[0042] Figure 10 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a Pwell region is provided;

[0043] Figure 11 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after an N+ layer is provided;

[0044] Figure 12 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after an insulating layer is provided;

[0045] Figure 13 Schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure of the present invention after a metal layer and a metal layer on the back of the N+ substrate are provided.

[0046] In the figure, the reference numerals are represented as: 1. N+ substrate; 2. First N-epitaxial layer; 3. Second N-epitaxial layer; 4. P+ masking layer; 5. First Trench groove; 6. Source electrode; 7. Second Trench groove; 71. JFET region; 8. Pwell region; 9. N+ layer; 10. Gate electrode; 11. Insulating layer; 12. Metal layer. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] It should be noted that the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] Please refer to Figures 1 to 4 , the present invention provides a high-voltage MOSFET device with a double-groove structure, including an N+ substrate 1, a first N-epitaxial layer 2, a second N-epitaxial layer 3, a P+ masking layer 4, a first Trench groove 5, a source electrode 6, an N+ layer 9, an insulating layer 11, and a metal layer 12, which are sequentially stacked. Pwell regions 8 are respectively arranged on both sides of the first Trench groove 5, and second Trench grooves 7 are respectively arranged on both sides of the two Pwell regions 8 away from the first Trench groove 5. One end of the Pwell region 8 is connected to the second N-epitaxial layer 3 and the P+ masking layer 4, and the other end is connected to the N+ layer 9 and the metal layer 12. Gates 10 are arranged on both sides of the two second Trench grooves 7 away from the Pwell region 8, and the gates 10 are also connected to the insulating layer 11. The components of the gates 10 and the source electrode 6 both include polysilicon.

[0050] In this embodiment, the high-voltage MOSFET device with a double-groove structure includes an N+ substrate 1, a first N-epitaxial layer 2, a second N-epitaxial layer 3, a P+ masking layer 4, a first Trench groove 5, a source electrode 6, an N+ layer 9, an insulating layer 11, and a metal layer 12, which are sequentially stacked from bottom to top. The source electrode 6 is arranged in the first Trench groove 5, and Pwell regions 8 are respectively arranged on both sides of the outer sidewall. One second Trench groove 7 is respectively arranged on one side of the two Pwell regions 8 away from the first Trench groove 5, that is, two second Trench grooves 7 are arranged, and a Pwell region 8 is arranged between each second Trench groove 7 and the first Trench groove 5. The first Trench groove 5 and the second Trench groove 7 are respectively on the left and right sides of the Pwell region 8, and the lower end is connected to the second N-epitaxial layer 3 and the P+ masking layer 4, and the upper end is connected to the metal layer 12 and the N+ layer 9. Gates 10 are arranged on the side of the second Trench groove away from the Pwell region 8, and the upper end of the gates 10 is connected to the insulating layer. Among them, the main components of the gates 10 and the source electrode 6 include polysilicon.

[0051] Specifically, the N+ substrate 1 is an important part of the conductive path of the high-voltage MOSFET device; the first N-epitaxial layer 2 is the inner epitaxy of the double-epitaxy structure in the embodiment of the present application, and the second N-epitaxial layer 3 is the surface epitaxy of the double-epitaxy structure in the embodiment of the present application. The specifications of the two epitaxial layers are different, but they bear the voltage at the same time. Optimizing the original single-epitaxial layer into a double-epitaxial structure can adjust the on-resistance to eliminate the influence. The P+ masking layer 4 is for improving the breakdown voltage; the first Trench groove 5 is an important part of the source electrode 6, and the second Trench groove 7 is an important part of the gate in the embodiment of the present application. The embodiment of the present application optimizes the original planar high-voltage structure product into a double-groove structure high-voltage MOSFET device, reducing the size of the MOSFET device, that is, achieving a reduction in the overall size of the MOSFET device under the same performance specifications. The source electrode 6 is used to adjust the electric field distribution of the MOSFET device; the Pwell region 8 is used to bear the voltage; the N+ layer 9 is an important part of the conductive path; the insulating layer 11 is used to isolate the gate from the gate to prevent short-circuit contact between the two; the metal layer 12 is used for conduction and contact connection with the source electrode 6. Among them, the first N-epitaxial layer 2 and the second N-epitaxial layer 3 are stacked on the front surface of the N+ substrate 1, and the material of the front surface of the N+ substrate 1 is aluminum. The back surface of the N+ substrate 1 includes a stacked Ti-Ni-Ag structure.

[0052] Specifically, in actual product design, the Trench groove structure is usually applied to the design of low-voltage MOSFET products (usually referring to products with a breakdown voltage < 300V), mainly limited by the fact that as the voltage level increases, breakdown is likely to occur at the trench. In the embodiment of the present application, by using the P+ masking layer 4 and the method of setting polysilicon both inside the source electrode 6 and inside the gate 10, a breakdown voltage of more than 300V is achieved.

[0053] Please refer to Figure 2 , Figure 2 is a structural diagram of a conventional planar MOSFET design. Taking a 900V high-voltage MOSFET product as an example, its unit cell design size is 15um. Figure 3 is a schematic diagram of the electric field distribution of a conventional planar MOSFET. When a positive voltage is applied between the D (device drain) and S (device source), the device operates in reverse. At this time, the breakdown voltage structure of the device is mainly borne by the diode formed by the raw material and the Pwell and N-epitaxial layers. The reverse-formed depletion region is shown by the dotted line, the electric field is shown by the arrow, and the direction of the electric field is the longitudinal Y direction.

[0054] Please refer to Figure 1 and Figure 4 , Figure 1This is the design structure diagram of the double-groove MOSFET in the embodiment of the present application. Taking the 900V high-voltage MOSFET product as an example, the parameters of the high-voltage MOSFET device in the embodiment of the present application are based on the 900V high voltage of the high-voltage MOSFET product, which will not be elaborated below. Figure 4 This is the schematic diagram of the electric field distribution of the double-groove MOSFET in the embodiment of the present application. When a positive voltage is applied between D (device drain) and S (device source), the device operates in reverse. At this time, the voltage withstand structure of the device is mainly borne by the diode formed by the raw material, the Pwell region 8, the P+ mask layer 4 and the two N-epitaxial layers. And due to the presence of polysilicon in the source 6, it plays a role in improving the electric field structure, generating a transverse electric field component from the original longitudinal electric field, thereby improving the voltage withstand ability of the product. The reverse-formed depletion region is shown by the dotted line, and the electric field is shown by the arrow.

[0055] Furthermore, the size of the high-voltage MOSFET device is 6.5 - 8.5 μm.

[0056] The original designed width dimension of the single cell of the high-voltage MOSFET device is 15 μm (which can be regarded as the width of the device). Using the structure in the embodiment of the present application for design, without changing the length and height dimensions of the single cell of the high-voltage MOSFET device, the designed width dimension of the single cell of the high-voltage MOSFET device can be optimized to 7.5 μm. Therefore, without changing the chip design size, the chip can accommodate the changed single cells as a whole, and the resistance parameters of the device are further optimized; and without changing the resistance parameters of the device, the chip design area can be reduced by about 2 times. That is, 50% of the design size can be saved. Under the same voltage level, the high-voltage Trench structure in the embodiment of the present application is only 50% of the size of the high-voltage planar structure, which means the chip size / area can be reduced by 50%. On the same wafer size, more effective die can be obtained, and the production cost is reduced by 50%.

[0057] Furthermore, the width of the first Trench groove 5 is 1 - 2 μm, and the depth is 4 - 5 μm; the width of the second Trench groove 7 is 0.5 - 1.5 μm, and the depth is 1.5 - 2.5 μm.

[0058] In this embodiment, the width of the first Trench groove 5 is preferably 1.2 μm, and the depth is preferably 4.5 μm; the width of the second Trench groove 7 is preferably 1.0 μm, and the depth is preferably 1.8 μm.

[0059] Furthermore, a JFET region 71 is provided at the bottom of the second Trench groove 7.

[0060] In this embodiment, a JFET region 71 is further provided at the bottom of the trench of the second Trench groove 7. In theory, the on-resistance of a Trench trench structure product is usually lower than that of a planar structure product, but this is only limited to the design of low-voltage MOSFET products. Because in a high-voltage Trench structure, the resistance of the JFET region accounts for a large proportion of the on-resistance. If it cannot be eliminated, the product advantages will disappear. In the embodiment of the present application, the on-resistance is adjusted by designing a double epitaxial structure, and at the same time, the JFET injection method can better reduce the influence of the JFET region 71 on the on-resistance.

[0061] Further, please refer to Figures 5 - 13 , the manufacturing method of a double-groove high-voltage MOSFET device includes:

[0062] S1. Form a first N-epitaxial layer 2 and a second N-epitaxial layer 3 required for the high-voltage MOSFET device. Preferably, the doping concentration of the raw material of the first N-epitaxial layer 2 is 1.9e14, and the raw material thickness is 67um; the doping concentration of the raw material of the second N-epitaxial layer 3 is 3.0e15, and the raw material thickness is 5um; the doping element is phosphorus. Specifically, please refer to Figure 5 , Figure 5 is the schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure after epitaxy in the embodiment of the present application.

[0063] S2. Adopt the SiO2 hard mask and photolithography etching method to form the first Trench groove 5 structure required for the source electrode 6 of the high-voltage MOSFET device. Taking a 900V product as an example, preferably, the width of the first Trench groove 5 is 1.2um, and the depth of the first Trench groove 5 is 4.5um; specifically, please refer to Figure 6 , Figure 6 is the schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure in the embodiment of the present application after the first Trench groove is provided.

[0064] S3. Adopt the ion implantation and thermal oxidation pushing junction method to form the P+ mask layer 4 structure and the oxide layer structure required for the source electrode 6 of the high-voltage MOSFET device. Taking a 900V product as an example, preferably, the ion implantation dose is 1e13, the implantation energy is 80kev, and the implantation element is boron; the thermal oxidation temperature is 1150°C; specifically, please refer to Figure 7 , Figure 7 is the schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure in the embodiment of the present application after the P+ mask layer is provided. The Field Oxide in the figure is the oxide layer.

[0065] S4. Use the oxide layer formed by thermal oxidation as a hard mask, form the window of the second Trench groove 7 by lithography, and form the second Trench groove 7 required for the gate of the high-voltage MOSFET device by etching. Taking a 900V product as an example, preferably, the width of the second Trench groove 7 is 1.0um, and the depth of the second Trench groove 7 is 1.8um; for details, please refer to Figure 8 , Figure 8 FIG. is a schematic structural diagram of the high-voltage MOSFET device with a double-groove structure in the embodiment of the present application after the second Trench groove is provided.

[0066] S5. First, perform a large-area phosphorus element implantation on the bottom of the second Trench groove 7 and the Si mesa by ion implantation, and perform diffusion pushing by thermal oxidation to form the JFET region 71 and adjust the resistance. At the same time, affected by the mutual compensation of boron and phosphorus elements, the initial P+ masking structure formed on the mesa disappears. Subsequently, the gate oxide layer is grown. Taking a 900V product as an example, preferably, the ion implantation dose is 2.5e12, the implantation energy is 100kev, the implanted element is phosphorus, and the gate oxide thickness is 1100A. For details, please refer to Figure 9 , Figure 9 FIG. is a schematic structural diagram of the high-voltage MOSFET device with a double-groove structure in the embodiment of the present application after the gate oxide layer (Gate Oxide) and the JFET region are provided.

[0067] S6. First, fill the first Trench groove 5 and the second Trench groove 7 with polysilicon by chemical vapor deposition, and use in-situ doping technology to synchronously dope the polysilicon to form the source and gate mainly composed of polysilicon. Subsequently, use CMP to remove the polysilicon on the surface. Finally, perform a large-area implantation by ion implantation, and form the Pwell region 8 by thermal oxidation diffusion pushing. Taking a 900V product as an example, preferably, the polysilicon thickness is the doping element is phosphorus, and the doping concentration is 2.9e14. The ion implantation element is boron, the implantation dose is 1.5e13, and the implantation energy is 60kev. The thermal oxidation diffusion pushing temperature is 1150°C. For details, please refer to Figure 10 , Figure 10 FIG. is a schematic structural diagram of the high-voltage MOSFET device with a double-groove structure in the embodiment of the present application after the Pwell region is provided.

[0068] S7. Perform a large-area implantation by ion implantation to form the N+ layer 9, and use annealing to activate the impurities. Taking a 900V product as an example, preferably, the ion implantation element is arsenic, the implantation dose is 1.0e16, the implantation energy is 100kev, and the annealing temperature is 950°C. For details, please refer to Figure 11 , Figure 11This is a schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure after the N+ layer is provided in the embodiment of the present application.

[0069] S8. First, the insulating layer 11 (dielectric layer ILD) is grown by chemical vapor deposition. Subsequently, according to the designed size of the holes, the source electrode window is realized by photolithography. Then, the corresponding thicknesses of the insulating layer 11 and the Field Oxide are removed by wet etching. Finally, the polysilicon and silicon materials are synchronously removed by dry etching to realize the contact hole shallow trench structure. Taking a 900V product as an example, preferably, the thickness of the insulating layer 11 is 10,000 Å, the designed width of the contact hole is 3 μm, and the designed depth of the contact hole shallow trench is 0.5 μm. For details, please refer to Figure 12 , Figure 12 This is a schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure after the insulating layer is provided in the embodiment of the present application.

[0070] S9. The high-voltage MOSFET device is thinned. The metal material on the front side of the N+ substrate 1 is designed as aluminum, and the back side adopts a three-layer metal structure. Taking a 900V product as an example, preferably, the overall thickness of the chip after thinning is designed to be 175 μm, the thickness of the front-side metal is 5 μm, and the back-side metal adopts a Ti-Ni-Ag structure. For details, please refer to Figure 13 , Figure 13 This is a schematic diagram of the structure of the high-voltage MOSFET device with a double-groove structure after the metal layer and the metal layer on the back side of the N+ substrate are provided in the embodiment of the present application.

[0071] The technical effects achieved by manufacturing the high-voltage MOSFET device with a double-groove structure through the above manufacturing method include the following:

[0072] 1. In actual product design, the Trench trench structure is usually applied to the design of low-voltage MOSFET products (usually referring to products with a breakdown voltage < 300V), mainly limited by the fact that as the voltage level increases, breakdown is likely to occur at the trench. In this paper, the method of P+ masking and introducing polysilicon is adopted to achieve a breakdown voltage above 300V.

[0073] 2. Theoretically, the on-resistance of the Trench trench structure product is usually lower than that of the planar structure product, but this is only limited to the design of low-voltage MOSFET products. Because in the high-voltage Trench structure, the resistance of the JFET region accounts for a large proportion of the on-resistance. If it cannot be eliminated, the product advantage will disappear. In this paper, by designing a double-layer epitaxial structure and adopting the JFET injection method, the influence of the JFET region on the on-resistance is reduced.

[0074] 3. At the same voltage level, the high-voltage Trench structure in this article is only 50% of the size of the high-voltage planar structure, which means that the chip size / area can be reduced by 50%. On the same wafer size, more effective die can be obtained, and the production cost is reduced by 50%.

[0075] The present invention provides a high-voltage MOSFET device with a double-groove structure and a manufacturing method. The high-voltage MOSFET device with a double-groove structure includes an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a P+ masking layer, a first Trench groove, a source electrode, an N+ layer, an insulating layer, and a metal layer stacked in sequence. Pwell regions are respectively arranged on both sides of the first Trench groove, and second Trench grooves are respectively arranged on both sides of the two Pwell regions far from the first Trench groove. One end of the Pwell region is connected to the second N-epitaxial layer and the P+ masking layer, and the other end is connected to the N+ layer and the metal layer. Gates are arranged on both sides of the two second Trench grooves far from the Pwell region, and the gates are also connected to the insulating layer. The components of the gates and the source electrodes both include polysilicon. By providing the high-voltage MOSFET device with a double-groove structure and adopting the methods of P+ masking and introducing polysilicon, a breakdown voltage level above 300V is achieved. While reducing the design size and production cost, the main parameter performance of this structure is equivalent to the original design. Among them, the polysilicon in the source electrode plays a role in improving the electric field structure, generating a transverse electric field component from the original longitudinal electric field, thereby enhancing the breakdown voltage ability of the product.

[0076] It should be noted that the various embodiments in the content of the present invention are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same and similar parts among the various embodiments, reference can be made to each other.

[0077] It also should be noted that in the content of the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0078] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high voltage MOSFET device with a double trench structure, characterized in that: The invention comprises an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a P+ shielding layer, a first Trench groove, a source electrode, an N+ layer, an insulating layer, and a metal layer which are stacked in sequence, wherein Pwell regions are respectively arranged on both sides of the first Trench groove, and second Trench grooves are respectively arranged on both sides of the two Pwell regions away from the first Trench groove, one end of the Pwell region is connected to the second N-epitaxial layer and the P+ shielding layer, and the other end is connected to the N+ layer and the metal layer, gates are also arranged on both sides of the two second Trench grooves away from the Pwell region, the gates are also connected to the insulating layer, and the components of the gates and the source electrode include polysilicon; A high voltage MOSFET device with a double trench structure is manufactured by the following steps: S1, sequentially preparing a first N-epitaxial layer and a second N-epitaxial layer by epitaxial growth on an N+ substrate; S2, forming a first trench in the second N-epitaxial layer by means of SiO2 hard mask and photolithography and etching; S3, forming a P+ shielding layer and an oxide layer in the first trench by ion implantation and thermal oxidation; S4, using the oxide layer as a hard mask, and forming a second trench by photolithography and etching; S5, using chemical vapor deposition to fill the first trench and the second trench with polysilicon, and using an in-situ doping process to simultaneously achieve polysilicon doping to form a source and a gate whose main components are polysilicon, and then using CMP to remove the surface polysilicon, and performing large-area ion implantation and thermal oxidation junction pushing to form a Pwell region; S6, performing large-area ion implantation on the second N-epitaxial layer to form an N+ layer, and activating impurities by annealing; S7, growing an insulating layer on the second N-epitaxial layer by chemical vapor deposition; S8. A metal layer is deposited on the surface of the insulating layer, wherein a source window is realized by photolithography, a corresponding thickness of the insulating layer and the oxide layer is removed by wet etching, and then polysilicon is simultaneously removed by dry etching to realize a shallow groove structure of a contact hole, wherein the contact hole connects the metal layer; a back side thinning process is used to evaporate a Ti-Ni-Ag structural layer on the back side of the N+ substrate.

2. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: The width of the high-voltage MOSFET device is 6.5-8.5 μm.

3. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: The first trench has a width of 1-2 μm and a depth of 4-5 μm.

4. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: The second trench has a width of 0.5-1.5 μm and a depth of 1.5-2.5 μm.

5. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: A JFET region is disposed at the bottom of the second trench.

6. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: The first N-epitaxial layer and the second N-epitaxial layer are stacked on the front side of the N+ substrate, and the material of the front side of the N+ substrate is aluminum. The back side of the N+ substrate includes a stacked Ti-Ni-Ag structure.

7. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: In step S4, a large area of ​​phosphorus ion implantation and thermal oxidation junction push-up are performed at the bottom of the second trench to form a JFET region, and a gate oxide layer is grown.

8. The high voltage MOSFET device with a double trench structure according to claim 1, characterized in that: In step S1, the doping concentration of the first N-epitaxial layer raw material is 1.9e14 atoms / cm³, and the thickness of the first N-epitaxial layer raw material is 65-70 μm; the doping concentration of the second N-epitaxial layer raw material is 3.0e15 atoms / cm³, and the thickness of the second N-epitaxial layer raw material is 3-8 μm; the doping element is phosphorus; In step S3, the ion implantation dose is 1e13 ions / cm², the implantation energy is 80kev, the implantation element is boron, and the thermal oxidation temperature is 1150°C; In step S4, the ion dose injected into the second trench is 2.5e12 ions / cm², the injection energy is 100kev, and the thickness of the gate oxide layer is 1100Å; In step S5, the thickness of polysilicon is 12000Å, the doping element is phosphorus, the doping concentration is 2.9e14 atoms / cm³, or the ion implantation element is boron, the implantation dose is 1.5e13 ions / cm², the implantation energy is 60kev, and the thermal oxidation junction temperature is 1150°C; In step S6, the ion implantation element is arsenic, the implantation dose is 1.0e16 ions / cm², the implantation energy is 100kev, and the annealing temperature is 950°C; In step S8, the thickness of the insulating layer is 10000Å, the design width of the contact hole is 2-5um, and the design depth of the shallow trench of the contact hole is 0.2-0.8um.

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