A method and device for implementing Retimer mode switching

Abstract

The present invention discloses a method and device for implementing Retimer mode switching, the method includes ordered set interval maintenance logic, PIPE transmission timing alignment logic, mode switching synchronization logic and execution mode exit timeout logic, wherein: the ordered set interval maintenance logic is used to ensure the correctness of the ordered set interval when forwarding is cut into execution; the PIPE transmission timing alignment logic is used to ensure that the PIPE transmission timing is aligned when executing cut-in forwarding; the mode switching synchronization logic is used to ensure the synchronization of various dependent conditions of mode switching; the execution mode exit timeout logic is used to force exit from the execution mode if the EQ state machine does not exit from the execution mode within a specified time after exiting. The present invention can enhance the robustness of the PCIE link.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and more specifically, relates to a method and device for implementing Retimer mode switching. Background Art

[0002] As the transmission rate of Peripheral Component Interconnect Express (PCIE) continues to increase, the signal attenuation problem becomes particularly serious, and the unit signal time (UnitInterval, abbreviated as: UI) becomes smaller and smaller, resulting in worsening eye diagram quality at the receiving end, which directly causes the bit error rate to deteriorate. In order to solve the above problems, it is necessary to place a relay chip in the middle of the signal transmission path or at the interface card slot to restore the signal quality. Common relay chips include Redriver and Retimer. Redriver is a non-protocol-aware device that simply amplifies the signal and does not have the ability to perform individual equalization and testing on each sub-link; Retimer is improved on the basis of Redriver and has protocol-aware capabilities, can perceive the link training process, and can adjust the equalization of each sub-link individually, but the transmission delay is greater.

[0003] Retimer has forwarding mode and execution mode. The forwarding mode is responsible for forwarding the Ordered Sets (training sequence), Compliance Pattern (consistency test pattern), Loopback Data (loopback data), TLP (transaction layer packet), DLLP (data link layer packet), etc. received by the pseudo port on one side to the pseudo port on the other side. The execution mode is responsible for generating Ordered Sets, Compliance Pattern, etc. by itself, which are used to perform balancing of each sub-link and test the electrical characteristics of the sending and receiving ends of each sub-link. Since the mode switching related to electrical testing is relatively simple and does not require improvement, only the equalization mode switching is discussed here; when entering EQphase2 (the second stage of equalization; in this stage, the upstream pseudo-port of the Retimer feeds back the Tx preset value corresponding to the RC according to the size of the eye diagram of the receiving end, so that the signal sent by the RC Tx has the largest eye diagram), the Retimer needs to switch from forwarding mode to execution mode, and then each pseudo-port of the Retimer acts as a sending module, actively sending and receiving equalization sequences to adjust the equalization coefficient of each sub-link; when the equalization is completed, it is necessary to switch from execution mode to forwarding mode and continue link training to L0. The schematic diagram of mode switching is referenced Figure 1As shown, when the mode indication signal is high, the forwarding mode sequence is selected for output, otherwise the execution mode sequence is selected for output. In order not to destroy the sequence, it is necessary to ensure that the switching is performed at the TS1 sequence boundary.

[0004] At present, the mode switching method of Retimer only considers the simple scenarios of switching from forwarding mode to execution mode and from execution mode to forwarding mode, which only meets the basic requirements of PCIE protocol, but does not consider the following situations: 1. The equal interval of the ordered set (Electrical Idle Exit Ordered Set, abbreviated as: EIEOS) and SKIP (clock tolerance adjustment sequence) at the switching boundary between forwarding mode and execution mode; 2. The correctness of subsequent execution switching and forwarding cannot be affected after the interruption of receiving data in execution mode; 3. The synchronization of mode switching between lanes; 4. The robustness of being able to exit execution mode and restore link establishment when the transmission and reception in execution mode are abnormal. If the above four points are not implemented or implemented unreasonably, certain errors will occur at the mode switching moment or after exiting mode switching, and even cause link retraining.

[0005] In view of this, how to overcome the technical problems existing in the above-mentioned prior art is a difficult problem to be solved urgently in this technical field. Summary of the invention

[0006] One of the purposes of the present invention is to overcome the technical problems existing in the above-mentioned prior art and to propose a method and device for implementing Retimer mode switching, aiming to solve at least one of the above-mentioned problems so as to enhance the robustness of the PCIE link.

[0007] To achieve the above-mentioned purpose, according to a first aspect of the present invention, a Retimer mode switching implementation method is provided, comprising an ordered set interval maintaining logic, a PIPE sending timing alignment logic, a mode switching synchronization logic and an execution mode exit timeout logic, wherein: the ordered set interval maintaining logic is used to ensure the correctness of the ordered set interval when forwarding is switched in and executed; the PIPE sending timing alignment logic is used to ensure the PIPE sending timing alignment when executing switching in and forwarding; the mode switching synchronization logic is used to ensure the synchronization of various dependent conditions of the mode switching; the execution mode exit timeout logic is used to force exit from the execution mode if the EQ state machine does not exit from the execution mode within a specified time after exiting.

[0008] Further, the ordered set interval maintenance logic includes:

[0009] Set an incrementing or decrementing counter a working in forwarding mode and an incrementing or decrementing counter b working in execution mode;

[0010] The enable signal of the counter a is the currently forwarded txstartblock pulse signal or the TS1 pulse signal, and the reset signal of the counter a is that the working rate is a preset value and the current mode is the execution mode;

[0011] The enable signal of the counter b is the currently sent txstartblock pulse signal or TS1 pulse signal, and the reset signal of the counter b is that the working rate is a preset value and the current mode is a forwarding mode;

[0012] When forwarding cut-in is executed, the counter b obtains the current value of the counter a+1 as its own initial value; when the counter reaches a preset value, an insertion enable signal is generated.

[0013] Further, the ordered set interval maintenance logic includes a SKIP interval maintenance logic, and the SKIP interval maintenance logic specifically includes:

[0014] The forwarded txstartblock pulse signal is counted at a preset rate through the SKIP interval counter. When the SKIP is forwarded, the counter is cleared, otherwise it is incremented. When the forwarding mode is switched to the execution mode, the value of the current SKIP interval counter is added by 1 and assigned to the SKIP sending counter. At this time, the SKIP sending counter increments the actively sent txstartblock pulse signal. When the count reaches the preset value, the counter is cleared and a SKIP insertion enable signal is generated.

[0015] Further, the ordered set interval maintenance logic includes an EIEOS interval maintenance logic, and the EIEOS interval maintenance logic specifically includes:

[0016] The EIEOS interval counter counts the forwarded TS1 pulse signal at a preset rate. When forwarding EIEOS, the counter is cleared, otherwise it is incremented. When switching from forwarding mode to execution mode, the value of the current EIEOS interval counter is added by 1 and assigned to the EIEOS sending counter. At this time, the EIEOS sending counter starts to count up. When the count reaches the preset value, the counter is cleared and an EIEOS insertion enable signal is generated.

[0017] Further, the PIPE sending timing alignment logic includes:

[0018] A phase difference detection circuit working in execution mode and a SKIP sending logic working in execution mode are set, the input signal of the phase difference detection circuit includes a txstartblock pulse signal of a sending end in forwarding mode and a txstartblock pulse signal of a sending end in execution mode; the output signal of the phase difference detection circuit includes an output phase difference; the input signal of the SKIP sending logic includes a current working rate and an output phase difference; the output signal of the SKIP sending logic includes three types of signals, namely, SKIP OS of normal length, SKIP OS after symbols are deleted, and SKIPOS after symbols are added, and the SKIP sending logic determines and outputs one type of signal according to the output phase difference of the phase difference detection circuit.

[0019] Further, the SKIP sending logic determines to output one type of signal according to the output phase difference of the phase difference detection circuit, specifically including:

[0020] Calculate the cycle number difference between the txstartblock pulse signal of the sending end in forwarding mode and the txstartblock pulse signal of the sending end in execution mode. When the cycle number difference is not zero, compare the cycle number with half of the interval of the txstartblock pulse signal of the sending end in execution mode. If the cycle number is smaller, output and send the SKIP OS indication signal of deletion symbol. If the cycle number is larger or equal, output and send the SKIP OS indication signal of addition symbol. When the cycle number difference is zero, output and send the SKIP OS indication signal of normal length.

[0021] Furthermore, the mode switching synchronization logic includes:

[0022] The switching conditions that must be met simultaneously for forwarding cut-in execution are: the main state machine of each lane channel is strictly synchronized and enters the EQ phase2 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels is aligned;

[0023] The switching conditions that must be met simultaneously for executing cut-in forwarding are: the main state machine of each lane channel is strictly synchronized and exits the EQ phase3 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels is aligned; the forwarding mode PIPE sending timing is aligned with the execution mode PIPE sending timing.

[0024] Further, the execution mode exit timeout logic includes:

[0025] Set a timeout counter. When each lane exits EQ phase 3, start counting up. If the execution mode is exited within the specified time, the counter is cleared. Otherwise, the execution mode is forced to exit after the counter times out.

[0026] Furthermore, the timeout counter includes a counter c operating in an execution mode, the counter c increases or decreases under the action of a clock edge, the initial value or threshold of the counter c is controlled by an n-bit register, and one of 2^n values ​​is selected; when the counter c times out, an enable signal is generated, and the enable signal forces the Retimer to switch from the execution mode to the forwarding mode.

[0027] In a second aspect, the present invention provides a Retimer mode switching implementation device, which applies the Retimer mode switching implementation method described in the first aspect, and the device includes at least one processor and a memory, the at least one processor and the memory are connected via a data bus, the memory stores instructions that can be executed by the at least one processor, and the instructions are used to complete the Retimer mode switching implementation method of the first aspect after being executed by the processor.

[0028] In general, the above technical scheme conceived by the present invention has the following beneficial effects compared with the prior art: the present invention proposes a Retimer mode switching implementation method and device, provides an ordered set interval maintenance logic, ensures the correctness of the SKIP / EIEOS interval when the forwarding is cut in, and if there is no interruption in the received data in the execution mode, it can also ensure the correctness of the SKIP / EIEOS interval when the forwarding is cut out, thereby avoiding probabilistic data errors at the time of mode switching.

[0029] Provide PIPE send timing alignment logic to ensure that the PIPE send timing is aligned when performing cut-in forwarding, avoiding data errors when switching modes.

[0030] Providing mode switching synchronization logic ensures that all dependent conditions of mode switching are synchronized, so that the mode switching is also completely synchronized, ensuring the correctness of the data link during switching.

[0031] Provides execution mode exit timeout logic. When the EQ state machine exits, if it does not exit from the execution mode within the specified time, this module will force exit from the execution mode to ensure that subsequent link training can proceed normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of mode switching provided by an embodiment of the present invention;

[0033] Figure 2A schematic diagram of a flow chart of a method for implementing a Retimer mode switching provided by an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of implementing the SKIP interval maintenance logic provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the implementation of the EIEOS interval maintenance logic provided by an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of the implementation of the PIPE transmission timing alignment logic provided in an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of phase difference provided by an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of the conditions for forwarding cut-in execution in the implementation of the mode switching synchronization logic provided in an embodiment of the present invention;

[0039] Figure 8 A schematic diagram of conditions for executing cut-in forwarding in the implementation of the mode switching synchronization logic provided in an embodiment of the present invention;

[0040] Fig. 9 A schematic diagram of an implementation of the execution mode exit timeout logic provided in an embodiment of the present invention;

[0041] Fig.10 A schematic diagram of the structure of a Retimer mode switching implementation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] The present invention is an architecture of a specific functional device, so the specific embodiments mainly illustrate the functional logical relationship between the various structural modules, and do not limit the specific software and hardware implementation methods.

[0044] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other, and the order of each step can be changed if it is logical and does not conflict. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0045] refer to Figure 2As shown, in some embodiments, the present invention provides a method for implementing Retimer mode switching, including setting ordered set interval maintenance logic, PIPE transmission timing alignment logic, mode switching synchronization logic, and execution mode exit timeout logic. Specifically, it can be divided into the following steps. Among them, PIPE: PHY Interface for the PCIExpress, Chinese interpretation: PCIe PHY interface. It is usually directly called: PIPE interface in the field.

[0046] Step 100: Set the ordered set interval maintenance logic, which is used to ensure the correctness of the ordered set interval when forwarding is switched into execution. It should be noted that the current PCIE Retimer has the following problems: when switching from forwarding mode to execution mode, the SKIP or EIEOS interval in the TS1 sequence changes; for example, in Common Clock forwarding mode, the SKIP interval is 370 blocks. When switching into execution mode, since the first SKIP sending timing is related to the specific implementation, the interval between the SKIP at the end of the forwarding mode and the first SKIP in the execution mode may not be 370 blocks, which may affect the clock tolerance adjustment and cause data errors in this vicinity; in response to this problem, a SKIP / EIEOS interval maintenance logic is proposed to ensure the correctness of the SKIP / EIEOS interval when forwarding is switched into execution, and if the received data is not interrupted in the execution mode, the correctness of the SKIP / EIEOS interval can also be ensured when switching out of forwarding, avoiding probabilistic data errors at the time of mode switching.

[0047] Step 200: Set the PIPE transmission timing alignment logic, which is used to ensure that the PIPE transmission timing is aligned when the forwarding is executed. It should be noted that the current PCIE Retimer has the following problems: when the received data is interrupted in the execution mode, the forwarding mode PIPE interface transmission timing and the execution mode PIPE interface transmission timing will be misaligned. When the execution mode is subsequently switched to the forwarding mode, the output PIPE interface transmission timing will be disordered, resulting in large-scale data errors; in response to this problem, a forwarding execution PIPE transmission timing alignment logic is proposed to ensure that the PIPE transmission timing is aligned when the forwarding is executed, avoiding data errors at the time of mode switching.

[0048] Step 300: Set the mode switching synchronization logic, which is used to ensure the synchronization of various dependent conditions of the mode switching. It should be noted that the current PCIE Retimer has the following problems: when a single lane controller solution is adopted, that is, the xN Retimer controller is spliced ​​with N x1 Retimer controllers, when the mode is switched, the mode switching indication signal of each lane controller may be misaligned at the moment of mode switching, thereby causing errors in the link training; in response to this problem, a mode switching synchronization logic is proposed, that is, to ensure that various dependent conditions of the mode switching are synchronized, then the mode switching is also completely synchronized, ensuring the correctness of the data link during switching.

[0049] Step 400: Set the execution mode exit timeout logic, which is used to force the exit of the execution mode if the EQ (Equalization) state machine does not exit the execution mode within a specified time after exiting. It should be noted that the current PCIE Retimer has the following problems: in the execution mode, if a serious error occurs in the received data, or the RC (Root Complex) and EP (Endpoint) behaviors are abnormal, the Retimer will not be able to exit the execution mode normally, and subsequent link training cannot be performed, and can only be restored by link reset; in response to this problem, an execution mode exit timeout logic is proposed. When the EQ state machine exits, if the execution mode is not exited within a specified time, this module will force the exit of the execution mode to ensure that subsequent link training can proceed normally.

[0050] In some embodiments, the ordered set interval maintenance logic includes: setting an increasing or decreasing counter a working in forwarding mode and an increasing or decreasing counter b working in execution mode; the enable signal of the counter a is the currently forwarded txstartblock pulse signal or TS1 pulse signal, and the clear signal of the counter a is that the working rate is a preset value and the current mode is an execution mode; the enable signal of the counter b is the currently sent txstartblock pulse signal or TS1 pulse signal, and the clear signal of the counter b is that the working rate is a preset value and the current mode is a forwarding mode; when the forwarding is cut in and executed, the counter b obtains the current value of the counter a + 1 as its own initial value; when the counter counts to the preset value, an insertion enable signal is generated.

[0051] refer to Figure 3As shown, in some embodiments, the ordered set interval holding logic includes a SKIP interval holding logic, and the SKIP interval holding logic specifically includes: counting the forwarded txstartblock pulse signal at a preset rate through a SKIP interval counter, and when forwarding a SKIP, clearing the counter, otherwise incrementing the count; when switching from the forwarding mode to the execution mode, the value of the current SKIP interval counter is increased by 1 and assigned to the SKIP sending counter, at which time the SKIP sending counter increments the actively sent txstartblock pulse signal, and when the count reaches the preset value, the counter is cleared and a SKIP insertion enable signal is generated. Specifically, the SKIP interval counter counts the forwarded txstartblock pulses at a rate of 8.0GT / s and above. When a SKIP is forwarded, the counter is cleared, otherwise it is incremented. When the forwarding mode is switched to the execution mode, the value of the current SKIP interval counter is added by 1 and assigned to the SKIP sending counter. At this time, the SKIP sending counter increments the actively sent txstartblock. When the count reaches 370 (common clock mode) or 38 (sris clock mode), the counter is cleared and a SKIP insertion enable signal is generated.

[0052] refer to Figure 4 As shown, in some embodiments, the ordered set interval holding logic includes an EIEOS interval holding logic, and the EIEOS interval holding logic specifically includes: the EIEOS interval counter counts the forwarded TS1 pulse signal at a preset rate, and when forwarding EIEOS, the counter is cleared, otherwise it counts up; when switching from forwarding mode to execution mode, the value of the current EIEOS interval counter is added by 1 and assigned to the EIEOS sending counter, at which time the EIEOS sending counter starts to count up, and when the count reaches the preset value, the counter is cleared, and an EIEOS insertion enable signal is generated. Specifically, the EIEOS interval counter counts the forwarded TS1 pulse at the Gen3 / 4 / 5 rate, and when forwarding EIEOS, the counter is cleared, otherwise it counts up; when switching from forwarding mode to execution mode, the value of the current EIEOS interval counter is added by 1 and assigned to the EIEOS sending counter, at which time the EIEOS sending counter starts to count up, and when the count reaches 31, the counter is cleared, and an EIEOS insertion enable signal is generated.

[0053] refer to Figure 5 , Figure 6As shown, in some embodiments, the PIPE sending timing alignment logic includes: setting a phase difference detection circuit working in execution mode and a SKIP sending logic working in execution mode, the input signal of the phase difference detection circuit includes a txstartblock pulse signal of the sending end in forwarding mode and a txstartblock pulse signal of the sending end in execution mode; the output signal of the phase difference detection circuit includes an output phase difference; the input signal of the SKIP sending logic includes the current working rate (the reason for using this signal is: this module must work at 8.0GT / and above, if the working rate is lower than this value, this module does not work) and the output phase difference of the phase difference detection circuit; the output signal of the SKIP sending logic includes three types of signals: SKIP OS of normal length, SKIP OS after deleting symbols, and SKIP OS after adding symbols, and the SKIP sending logic determines and outputs one of the types of signals according to the output phase difference of the phase difference detection circuit. Among them, the SKIP sending logic determines to output one type of signal according to the output phase difference of the phase difference detection circuit, specifically including: calculating the number of cycles that differ between the txstartblock pulse signal of the forwarding mode sending end and the txstartblock pulse signal of the execution mode sending end (the phase difference is the number of cycles that differ between the two signals); when the number of cycles is not zero, comparing the number of cycles with half of the interval of the txstartblock pulse signal of the execution mode sending end; if the number of cycles is smaller, outputting a SKIP OS indication signal for sending a deletion symbol; if the number of cycles is larger or equal, outputting a SKIP OS indication signal for sending an addition symbol; when the number of cycles is zero, outputting an indication signal for sending a SKIP OS of normal length.

[0054] Specifically, when the EQ phase3 exit flag is valid, on the one hand, SKIP continues to be inserted according to the specified interval, and on the other hand, the phase difference between the forwarding mode PIPE interface txstartblock and the execution mode PIPE interface txstartblock is calculated in real time. The principle is to start counting when the forwarding mode txstartblock is detected, and stop counting when the execution mode txstartblock is detected; then the count value is sent to the SKIP sending mode module to select the type of SKIP to be sent; if the count value is less than half of the two txstartblock intervals, the SKP symbol is deleted when the sending sequence is SKIP, and if the phase difference is greater than or equal to half of the two txstartblock intervals, the SKP symbol is added when the sending sequence is SKIP. When there is no phase difference between the two, it means that they are aligned at this time, and one of the conditions for mode switching is met at this time; in this way, the purpose of timing alignment can be achieved quickly when the received data flow is interrupted in the execution mode.

[0055] In some implementations, the mode switching synchronization logic includes a condition for executing the forwarding cut-in and a condition for executing the cut-in forwarding.

[0056] refer to Figure 7 As shown in the figure, the switching conditions that need to be met simultaneously for forwarding cut-in execution are: the main state machine of each lane channel is strictly synchronized and enters the EQ phase2 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels is aligned. Since the main state machine of each lane channel is strictly synchronized, condition a is met, and since the switch occurs when the channel is already aligned, conditions b and c are met; this saves additional synchronization logic, simplifies the design, and enhances robustness.

[0057] refer to Figure 8 As shown in the figure, the switching conditions that must be met simultaneously for the execution of the cut-in forwarding are: the main state machine of each lane channel is strictly synchronized and exits the EQ phase 3 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels is aligned; the forwarding mode PIPE sending timing is aligned with the execution mode PIPE sending timing. Since the main state machine of each lane channel is strictly synchronized, condition a is satisfied. Since the switching occurs when the channel is already aligned, conditions b and c are satisfied. Since the SKIP insertion point of each lane channel in the execution mode is also aligned, each lane channel is also synchronized when adjusting the timing alignment, so condition d is satisfied. This saves the extra synchronization logic, simplifies the design, and enhances robustness.

[0058] refer to Fig. 9As shown, in some embodiments, the execution mode exit timeout logic includes: setting a timeout counter, when each lane channel exits the EQ phase3 stage, starting to count up, if the execution mode is exited within a specified time, the counter is cleared, otherwise when the counter times out, the execution mode is forced to exit. Specifically, the timeout counter includes a counter c working in the execution mode, the counter c increases or decreases under the action of the clock edge, the initial value or threshold of the counter c is controlled by an n-bit register, and one of 2^n values ​​is selected; when the counter c times out, an enable signal is generated, and the enable signal forces the Retimer to switch from the execution mode to the forwarding mode. The logic principle is as follows: when data flow is interrupted or signal quality deteriorates, it is difficult for the forwarded data to be aligned in all channels, and the conditions for executing forwarding are not met; if it is stuck in the execution mode, the link cannot be retrained, the system is stuck, and it can only be released by resetting; by setting a timeout counter, when each lane channel exits the EQ phase3 stage, the increment count is started, if the execution mode is exited within the specified time, the counter is cleared, otherwise when the counter times out, the execution mode is forced to exit for subsequent link training, thus increasing the robustness of the mode switching. It should be noted that EQ Phase3: the third stage of equalization; in this stage, the downstream pseudo port of the Retimer feeds back the Tx preset value corresponding to the EP according to the size of the receiving end eye diagram, so that the signal sent by the EP Tx has the largest eye diagram.

[0059] In summary, the present invention proposes a method for implementing Retimer mode switching, which has the following characteristics:

[0060] (1) The structure and working principle of the SKIP / EIEOS interval holding logic, that is, it is a circuit with the following characteristics: it includes an increasing or decreasing counter a working in the forwarding mode, the enable signal of the counter is the currently forwarded txstartblock signal or TS1 pulse signal, and the clear signal of the counter is the working rate of 2.5GT / s and 5.0GT / s and the current mode is the execution mode; it includes an increasing or decreasing counter b working in the execution mode, the enable signal of the counter is the currently sent txstartblock signal or TS1 pulse signal, and the clear signal of the counter is the working rate of 2.5GT / s and 5.0GT / s and the current mode is the forwarding mode; when the forwarding is executed, the counter b obtains the current value of the counter a + 1 as its initial value; when the counter counts to 370 or 38, it generates a SKIP insertion indication signal; when the counter counts to 31, it generates an EIEOS insertion indication signal.

[0061] (2) The structure and working principle of the forwarding execution transmission timing alignment logic, that is, it is a circuit with the following characteristics: it contains a phase difference detection circuit, which works in the execution mode. Its input signals include the forwarding mode sending end txstartblock, the execution mode sending end txstartblock, and the current working rate. It calculates the number of cycles of the phase difference between the two startblock pulses. When the phase difference cycle number is not zero, it compares this value with half of the txstartblock pulse interval of the execution mode sending end. If it is less than this value, it outputs a SKIP OS indication signal for sending the deletion symbol. If it is greater than or equal to this value, it outputs a SKIP OS indication signal for sending the addition symbol. When the phase difference cycle number is zero, it outputs an indication signal for sending the normal length SKIP OS. It contains a SKIP sending logic working in the execution mode. It has the ability to send the normal length SKIP OS, the SKIP OS after the deletion symbol, and the SKIP OS after the addition symbol. The SKIP sending type is given by the phase difference detection circuit.

[0062] (3) The structure and working principle of the mode switching synchronization logic, that is, it is a circuit with the following characteristics: The forwarding and execution logic must meet the following switching conditions: a. The main state machine of each lane channel is strictly synchronized and enters the EQphase2 stage; b. The current forwarding sequence is not SKIP and EIEOS; c. The current forwarding data of all lane channels are aligned; The execution and forwarding logic must meet the following switching conditions: a. The main state machine of each lane channel is strictly synchronized and exits the EQphase3 stage; b. The current forwarding sequence is not SKIP and EIEOS; c. The current forwarding data of all lane channels are aligned; d. The forwarding mode PIPE sending timing is aligned with the execution mode PIPE sending timing.

[0063] (4) The structure and working principle of the execution mode exit timeout logic, that is, it is a circuit with the following characteristics: it contains a counter c that works in the execution mode. The counter increases or decreases under the action of the clock edge. The initial value or threshold of the counter is controlled by an n-bit register, and one of 2^n values ​​is selected. When the counter times out, an enable signal is generated, which forces the Retimer to switch from the execution mode to the forwarding mode.

[0064] The above features have the following advantages: It provides ordered set interval maintenance logic to ensure the correctness of the SKIP / EIEOS interval when forwarding is executed, and if the received data is not interrupted in the execution mode, it can also ensure the correctness of the SKIP / EIEOS interval when executing the cut-out forwarding, avoiding the probabilistic data error at the time of mode switching. It provides PIPE transmission timing alignment logic to ensure that the PIPE transmission timing is aligned when executing the cut-in forwarding, avoiding the data error at the time of mode switching. It provides mode switching synchronization logic, that is, to ensure that the various dependent conditions of the mode switching are synchronized, so that the mode switching is also completely synchronized, ensuring the correctness of the data link during the switch. It provides execution mode exit timeout logic. When the EQ state machine exits, if it does not exit from the execution mode within the specified time, this module will force exit the execution mode to ensure that subsequent link training can proceed normally.

[0065] Based on the Retimer mode switching implementation method provided in the above embodiment, the present invention also provides a Retimer mode switching implementation device that can be used to implement the above method, such as Fig.10 , which is a schematic diagram of the device architecture of an embodiment of the present invention. The Retimer mode switching implementation device of this embodiment includes one or more processors 21 and a memory 22. Fig.10 A processor 21 is taken as an example.

[0066] The processor 21 and the memory 22 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0067] The memory 22 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the Retimer mode switching implementation method in the above-mentioned embodiment. The processor 21 executes various functional applications and data processing of the Retimer mode switching implementation device by running the non-volatile software programs, instructions and modules stored in the memory 22, that is, the Retimer mode switching implementation method of the embodiment of the present invention is implemented.

[0068] The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 may optionally include a memory remotely arranged relative to the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0069] The program instructions / modules are stored in the memory 22 , and when executed by one or more processors 21 , the Retimer mode switching implementation method in the above embodiment is executed, for example, the control method of each logic described above is executed.

[0070] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for implementing Retimer mode switching, characterized in that: It includes ordered set interval keeping logic, PIPE sending timing alignment logic, mode switching synchronization logic and execution mode exit timeout logic, wherein: the ordered set interval keeping logic is used to ensure the correctness of the ordered set interval when forwarding is switched into execution; the ordered set interval keeping logic includes SKIP interval keeping logic and / or EIEOS interval keeping logic, and the SKIP interval keeping logic includes: counting the forwarded txstartblock pulse signal at a preset rate through a SKIP interval counter, when forwarding SKIP, clearing the counter, otherwise incrementing the count; when switching from forwarding mode to execution mode, adding 1 to the current SKIP interval counter value and assigning it to the SKIP sending count The SKIP sending counter counts the actively sent txstartblock pulse signal incrementally at this time. When the count reaches a preset value, the counter is cleared and a SKIP insertion enable signal is generated. The EIEOS interval holding logic includes: the EIEOS interval counter counts the forwarded TS1 pulse signal at a preset rate. When the EIEOS is forwarded, the counter is cleared, otherwise the count is incremented. When the forwarding mode is switched to the execution mode, the value of the current EIEOS interval counter is added by 1 and assigned to the EIEOS sending counter. At this time, the EIEOS sending counter starts to count incrementally. When the count reaches a preset value, the counter is cleared and an EIEOS insertion enable signal is generated. The PIPE transmission timing alignment logic is used to ensure that the PIPE transmission timing is aligned when the cut-in forwarding is executed; specifically, the phase difference between the forwarding mode PIPE interface txstartblock and the execution mode PIPE interface txstartblock is calculated, and the counting is started when the forwarding mode txstartblock is detected, and the counting is stopped when the execution mode txstartblock is detected; then the count value is sent to the SKIP transmission mode module to select the SKIP type to be sent; if the count value is less than half of the two txstartblock intervals, when the transmission sequence is SKIP, the SKP symbol is deleted, and if the phase difference is greater than or equal to half of the two txstartblock intervals, when the transmission sequence is SKIP, the SKP symbol is added, and when there is no phase difference between the two, it means that they are aligned at this time; The mode switching synchronization logic is used to ensure the synchronization of various dependent conditions of mode switching; the mode switching synchronization logic includes: the switching conditions that need to be met simultaneously for forwarding cut-in execution: the main state machine of each lane channel is strictly synchronized and enters the EQ phase2 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels are aligned; the switching conditions that need to be met simultaneously for execution cut-in forwarding: the main state machine of each lane channel is strictly synchronized and exits the EQ phase3 stage; the current forwarding sequence is not SKIP and EIEOS; the current forwarding data of all lane channels are aligned; the forwarding mode PIPE sending timing is aligned with the execution mode PIPE sending timing; The execution mode exit timeout logic is used to force exit from the execution mode if the EQ state machine does not exit from the execution mode within a specified time after exiting.

2. The method for implementing Retimer mode switching according to claim 1, characterized in that: The ordered set interval maintenance logic includes: Set an incrementing or decrementing counter a working in forwarding mode and an incrementing or decrementing counter b working in execution mode; The enable signal of the counter a is the currently forwarded txstartblock pulse signal or the TS1 pulse signal, and the reset signal of the counter a is that the working rate is a preset value and the current mode is the execution mode; The enable signal of the counter b is the currently sent txstartblock pulse signal or TS1 pulse signal, and the reset signal of the counter b is that the working rate is a preset value and the current mode is a forwarding mode; When forwarding cut-in is executed, the counter b obtains the current value of the counter a+1 as its own initial value; when the counter reaches a preset value, an insertion enable signal is generated.

3. The method for implementing Retimer mode switching according to claim 1, characterized in that: The PIPE transmission timing alignment logic includes: A phase difference detection circuit working in execution mode and a SKIP sending logic working in execution mode are set, the input signal of the phase difference detection circuit includes a txstartblock pulse signal of a sending end in forwarding mode and a txstartblock pulse signal of a sending end in execution mode; the output signal of the phase difference detection circuit includes an output phase difference; the input signal of the SKIP sending logic includes a current working rate and an output phase difference; the output signal of the SKIP sending logic includes three types of signals, namely, a SKIP OS of normal length, a SKIP OS after symbols are deleted, and a SKIP OS after symbols are added, and the SKIP sending logic determines and outputs one type of signal according to the output phase difference of the phase difference detection circuit.

4. The method for implementing Retimer mode switching according to claim 3, characterized in that: The SKIP sending logic determines and outputs one of the types of signals according to the output phase difference of the phase difference detection circuit: Calculate the cycle number difference between the txstartblock pulse signal of the sending end in forwarding mode and the txstartblock pulse signal of the sending end in execution mode. When the cycle number difference is not zero, compare the cycle number with half of the interval of the txstartblock pulse signal of the sending end in execution mode. If the cycle number is smaller, output and send the SKIP OS indication signal of deletion symbol. If the cycle number is larger or equal, output and send the SKIP OS indication signal of addition symbol. When the cycle number difference is zero, output and send the SKIP OS indication signal of normal length.

5. The method for implementing Retimer mode switching according to any one of claims 1 to 4, characterized in that: The execution mode exit timeout logic includes: Set a timeout counter. When each lane exits EQ phase 3, start counting up. If the execution mode is exited within the specified time, the counter is cleared. Otherwise, the execution mode is forced to exit after the counter times out.

6. The method for implementing Retimer mode switching according to claim 5, characterized in that: The timeout counter includes a counter c working in execution mode, the counter c increases or decreases under the action of the clock edge, the initial value or threshold of the counter c is controlled by an n-bit register, and one of 2^n values ​​is selected; when the counter c times out, an enable signal is generated, and the enable signal forces the Retimer to switch from the execution mode to the forwarding mode.

7. A device for implementing a Retimer mode switch, characterized in that: The method comprises at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, and the memory stores instructions that can be executed by the at least one processor, and after being executed by the processor, the instructions are used to complete the Retimer mode switching implementation method according to any one of claims 1 to 6.

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