Driving circuit and liquid crystal display

Abstract

The present application discloses a driving circuit, characterized in that it comprises: a level voltage generating circuit; a first modulation voltage generating circuit; and a first chamfering circuit module, comprising a first voltage level conversion circuit and a first output stage circuit, wherein the first output stage circuit comprises a P-type transistor PO, an N-type transistor NO, and a transistor combination, wherein the drain of the P-type transistor PO and the source of the N-type transistor NO are coupled to form a first output voltage V OUT , the source of the P-type transistor PO is coupled to the high voltage V GH , the drain of the N-type transistor NO is coupled to the low voltage V GL The first voltage level conversion circuit and the transistor combination are configured to convert the first voltage level into a voltage level according to the two inverted signals output by the first voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO and the N-type transistor NO.

Description

Technical Field

[0001] The present application belongs to the field of drive circuits and relates to a drive circuit for chamfering the falling edge of an output signal. Background Art

[0002] Liquid crystal display screen is the most commonly used display technology. Figure 1 , which is a schematic diagram of the structure of a liquid crystal display screen 100 according to the prior art. The liquid crystal display screen 100 includes pixel modules 130 arranged in a two-dimensional array, and each pixel module 130 includes at least one transistor, such as a thin film transistor (TFT). The data signal driving circuit module 110 and the gate signal driving circuit module 120 are connected to the transistor of each pixel module 130 through a plurality of data lines 141 and a plurality of scanning lines 142, respectively.

[0003] Please refer to Figure 2 , which is a schematic diagram of a pixel module 130 according to the prior art. The pixel module 130 includes a transistor 210 and a capacitor C S The gate G of the transistor 210 is connected to the aforementioned scan line 142, and the drain D of the transistor 210 is connected to the aforementioned data line 141. When the gate G receives the gate drive signal from the scan line 142, the data signal of the data line is stored in the capacitor C through the drain D. S The aforementioned gate drive signal can usually be expressed as a high voltage V GH After the charge storage is completed, the scan line 142 returns to its original voltage, which may be, for example, a ground voltage or a low voltage V GL , used to turn off transistor 210.

[0004] However, there is often a stray capacitance C between the gate G and the drain D of the transistor 210 or the thin film transistor 210. P , there is often a stray capacitance C between the gate G and the source S P When the gate drive signal of the scan line 142 changes from the high voltage V GH When the voltage is restored to the original voltage, the stray capacitance C P This tends to lower the voltage level between the gate G and the source S, thus affecting the capacitor C. S The amount of charge stored in the pixel module 130 causes color non-uniformity defects (mura defects) in the pixel module 130. The cause of the above defects is called feed-through phenomenon.

[0005] In order to improve or reduce the feedthrough phenomenon, the gate drive signal can be modulated at the falling edge. Figure 3 As shown, it is a schematic diagram of the signal falling edge chamfer waveform in the prior art. Figure 3 It is divided into three parts: upper, middle and lower. The upper part is the original gate drive signal V g The voltage drops sharply at time t2, from the high voltage V GH Drops to a low voltage V GL , resulting in the feedthrough phenomenon mentioned above. Figure 3 The middle part is a modulated signal V GHM At time point t1, the modulation signal V GHM At time t2, the modulation signal V GHM When the modulation signal V GHM For the original gate drive signal V g After the modulation, it forms Figure 3 The chamfered gate drive signal V in the lower half g It can be seen that it drops first after time t1, forming a missing corner on the upper right of the square wave. After time t2, let the gate drive signal V g Drop to low voltage V GL .

[0006] The gate drive signal V g The modulation method is called waveform shaping. The waveform after chamfering changes from high voltage V GH First, the voltage level drops to a low voltage V at time t2. GL To provide the above-mentioned waveform shaping or chamfering function, it is necessary to control a more complex timing, such as the aforementioned time points t1 and t2. In addition, the existing chamfering function requires a complex pulse signal modulation circuit unit to output the above-mentioned modulation signal V GHM The complex pulse signal modulation circuit unit requires a larger circuit area, which is not conducive to power consumption. In addition, the complex pulse signal modulation circuit unit needs to be able to withstand the high voltage V GH Charging and discharging the voltage-stabilizing capacitor is also not conducive to power consumption.

[0007] In summary, there is an urgent need for a driver circuit with a simplified design that can provide a high voltage output signal chamfering function with lower power consumption. When applied to a gate signal driver circuit module of a liquid crystal display screen, the feedthrough phenomenon and mura defect of the liquid crystal display screen can be reduced or avoided. Summary of the invention

[0008] The present application is a driving circuit proposed to solve the deficiencies in the prior art, and aims to provide a chamfered waveform of an output signal at a falling edge.

[0009] In order to achieve the above purpose, this application adopts the following technical solutions:

[0010] According to an embodiment of the present application, a driving circuit is provided, characterized in that it includes: a level voltage generating circuit for generating a voltage according to a high voltage V GH With low voltage V GL Generates a voltage level V GN ; A first modulation voltage generating circuit for selecting a first modulation voltage V according to a first control signal GPM At this high voltage V GH With the voltage level V GN and a first chamfering circuit module, comprising a first voltage level conversion circuit and a first output stage circuit, wherein the first output stage circuit comprises a P-type transistor PO, an N-type transistor NO, and a transistor combination, the drain of the P-type transistor PO and the source of the N-type transistor NO are coupled to a first output voltage V OUT , the source of the P-type transistor PO is coupled to the high voltage V GH , the drain of the N-type transistor NO is coupled to the low voltage V GL The first voltage level conversion circuit and the transistor combination are configured to convert the first voltage level into a voltage level according to the two inverted signals output by the first voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO and the N-type transistor NO.

[0011] In order to make the output voltage the high voltage V GH The above driving circuit is characterized in that when the first modulation voltage V GPM At this high voltage V GH and the input signal V IN When the first logic potential is reached, the P-type transistor PO is turned on and the N-type transistor NO is turned off, so that the first output voltage V OUT For the high voltage V GH .

[0012] In order to allow the parasitic charges of the output stage circuit to flow out of the driving circuit quickly, the driving circuit is characterized by further comprising: a first modulation voltage discharge circuit for selectively connecting the first modulation voltage V GPM and the low voltage V GL , when the first modulation voltage V GPM At this high voltage V GH And the first output voltage V OUT For the high voltage V GHWhen the first modulation voltage discharge circuit is connected to the first modulation voltage V GPM and the low voltage V GL The first modulation voltage V GPM drops to the voltage level V GN .

[0013] In order to allow the parasitic charge of the output stage circuit to flow out of the driving circuit quickly, the driving circuit is characterized in that the first modulation voltage discharge circuit comprises a P-type transistor P4 and an N-type transistor N1, wherein the source of the P-type transistor P4 is connected to the first modulation voltage V GPM The gate of the P-type transistor P4 is connected to the voltage level V GN The drain of the P-type transistor P4 is connected to the source of the N-type transistor N1, and the drain of the N-type transistor N1 is connected to the low voltage V GL The gate of the N-type transistor N1 receives a selection signal NDCG for selectively connecting the first modulation voltage V GPM and the low voltage V GL .

[0014] In order to make the first output voltage V OUT The driving circuit is characterized in that when the first modulation voltage V GPM At this voltage level V GN When the input signal of the first voltage level conversion circuit is a second logic potential corresponding to the first logic potential, the P-type transistor PO is turned off and the N-type transistor NO is turned on, and the gate of the N-type transistor NO is set to the level voltage V GN , so that the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL It descends, forming the first part of the chamfered waveform.

[0015] In order to make the first output voltage V OUT Rapidly drops from the corner to the low voltage V GL The above driving circuit is characterized in that when the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL When the first modulation voltage generating circuit makes the first modulation voltage V GPM At this voltage level V GN Rising to the high voltage V GH , the gate of the N-type transistor NO is set to the high voltage V GH , so that the first output voltage V OUT From this high voltage V GHRapidly drops to the low voltage V GL , forming the second part of the chamfered waveform.

[0016] In order to provide a level voltage V GN The driving circuit is characterized in that the level voltage generating circuit further comprises a circuit for receiving the high voltage V GH The first resistor and the low voltage V GL The second resistor, wherein the voltage level V GN is the output of the first resistor and the second resistor.

[0017] In order to control the first output voltage V OUT The chamfered waveform of the driving circuit is characterized in that the resistance values ​​of the first resistor and the second resistor are related to the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL Descending chamfered waveform.

[0018] In order to control the gate voltage of the N-type transistor NO to form the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL The driving circuit is characterized in that the transistor combination comprises an N-type transistor N2 and an N-type transistor N3, wherein the gate of the N-type transistor N2 and the gate of the N-type transistor N3 are respectively connected to the two inverted signals, and the source of the N-type transistor N2 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL , the drain of the N-type transistor N2 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

[0019] In order to control the gate voltage of the N-type transistor NO to form the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL The driving circuit is characterized in that the transistor combination comprises a P-type transistor P5 and an N-type transistor N3, the gate of the P-type transistor P5 and the gate of the N-type transistor N3 are connected to one of the two inverted signals, the other of the two inverted signals is connected to the gate of the P-type transistor PO, and the source of the P-type transistor P5 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL, the drain of the P-type transistor P5 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

[0020] In order to allow the first modulation voltage generating circuit to select the first modulation voltage V according to the first control signal GPM At this high voltage V GH With the voltage level V GN The driving circuit is characterized in that the first modulation voltage generating circuit further comprises: a P-type transistor P1 for selectively connecting the high voltage V according to the PG1 signal in the first control signal. GH and the first modulation voltage V GPM and a P-type transistor P2 and a P-type transistor P3 for selectively connecting the level voltage V according to the PG2 signal among the first control signal GN and the first modulation voltage V GPM .

[0021] In order to provide more output signals, the driving circuit is characterized in that it also includes: a second chamfering circuit module, including a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit includes a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, and the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to form a second output voltage V OUT , the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO2 and the N-type transistor NO2.

[0022] In order to speed up the modulation voltage V PGM From high potential to low potential V GN , and provide more output signals, the above-mentioned driving circuit is characterized in that it also includes: a second modulation voltage generating circuit for selecting a second modulation voltage V according to a second control signal GPM2 At this high voltage V GH With the voltage level V GN and a second chamfering circuit module, comprising a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit comprises a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to a second output voltage V OUT, the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the second modulation voltage V GPM Control the on and off of the P-type transistor PO2 and the N-type transistor NO2.

[0023] According to an embodiment of the present application, a liquid crystal display is provided, characterized in that it includes: a liquid crystal display; and a driving circuit as described above, for converting the first output voltage V OUT Used to control the display of pixels of the liquid crystal display.

[0024] Due to the adoption of the above scheme, the beneficial effects of the present application are: it is possible to provide a chamfering function of a high voltage output signal with lower power consumption, and it is also possible to discharge parasitic charges at a faster speed, so that the provided driving circuit can operate at a higher frequency. When the provided driving circuit is applied to a gate signal driving circuit module of a liquid crystal display screen, it can reduce or avoid feedthrough and mura defects of the liquid crystal display screen, and can also accelerate the refresh rate of the liquid crystal display screen.

[0025] The main effect of the present application is to use the above transistor combination and voltage level conversion circuit to control the gate voltage of the N-type transistor NO in the output stage circuit, change the equivalent impedance to affect the output pull-down capability to achieve the chamfering function, and also achieve the improved feed-through effect, but without switching the high voltage V in the output stage circuit. GH The voltage of the external large voltage-stabilizing capacitor is charged and discharged, which wastes power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a schematic diagram of the structure of a liquid crystal display screen 100 according to the prior art.

[0027] Figure 2 is a schematic diagram of a pixel module 130 according to the prior art.

[0028] Figure 3 It is a schematic diagram of a signal falling edge chamfer waveform in the prior art.

[0029] Figure 4 is a block diagram of a driving circuit 400 according to an embodiment of the present application.

[0030] Figure 5 FIG. 5 is a circuit diagram of a driving circuit 500 according to an embodiment of the present application.

[0031] Figure 6 for Figure 5 FIG. 5 is a schematic diagram showing a signal timing sequence of the driving circuit 500 .

[0032] Figure 7 Schematic diagram of different chamfered waveforms according to multiple embodiments of the present application.

[0033] Figure 8 FIG. 4 is a circuit diagram of a chamfering circuit module 440 according to another embodiment of the present application.

[0034] Fig. 9A is the output voltage V when the modulation voltage discharge circuit 430 is missing OUT Waveform diagram of .

[0035] Fig. 9B is the output voltage V when the voltage modulation discharge circuit 430 is provided. OUT Waveform diagram of .

[0036] Fig.10 FIG. 1 is a block diagram of a driving circuit 1000 according to an embodiment of the present application.

[0037] Fig.11 is a timing diagram of the enable signal of the driving circuit 1000.

[0038] Fig.12 FIG. 1 is a timing diagram of various signals of the driving circuit 1000 . DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The terms "first", "second", "third", etc. (if any) in the specification and claims of this application and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in these descriptions can be interchanged where appropriate. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware circuits or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0041] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0042] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0044] Please refer to Figure 4 , which is a block diagram of a driving circuit 400 according to an embodiment of the present application. The driving circuit 400 operates at a high voltage V GH With low voltage V GL In this embodiment, the output signal of the driving circuit 400 can be connected to the gate G of the aforementioned transistor 210. The output voltage V OUT have Figure 3 The falling edge chamfer waveform shown can reduce or avoid the feedthrough phenomenon of the transistor 210, thereby preventing the aforementioned mura defect from occurring in the LCD screen 100. However, those skilled in the art can understand that the driving circuit 400 can be applied to other applications and is not limited to the gate signal driving circuit module 120.

[0045] The driving circuit 400 includes a level voltage generating circuit 410, a modulation voltage generating circuit 420, and one or more chamfering circuit modules 440. In one embodiment, the driving circuit 400 further includes an optional modulation voltage discharging circuit 430.

[0046] The voltage level generating circuit 410 has two input terminals, which are respectively input with a high voltage V GH With low voltage V GL . According to the high voltage V GHWith low voltage V GL , the level voltage V output by the level voltage generating circuit 410 GN Enters the modulation voltage generating circuit 420 and the optional modulation voltage discharging circuit 430. The voltage level V GN Can be a high voltage V GH With low voltage V GL Resistor voltage divider. Adjust different output signal voltage V GN Different chamfering effects can be obtained.

[0047] The modulation voltage generating circuit 420 can respectively adjust the level voltage V GN Or high voltage V GH Output modulation voltage V GPM The chamfering circuit module 440 includes a voltage shift conversion circuit (level shifter) 450 and an output stage circuit 460. The voltage shift conversion circuit 450 receives an input voltage V IN , and outputs two inverted signals LS_A and LS_B with larger voltage absolute values ​​to the output stage circuit 460 respectively. IN can be lower than the high voltage V GH A person skilled in the art can understand various implementations of the voltage shift conversion circuit 450, so the present application will not further describe the voltage shift conversion circuit 450.

[0048] The output stage circuit 460 is based on the two signals LS_A and LS_B and the modulation voltage V GPM Output the output voltage V OUT , which has Figure 3 One of the inventive features of the chamfer circuit module 440 is the arrangement of the output stage circuit 460.

[0049] Please refer to Figure 5 , which is a circuit diagram of a driving circuit 500 according to an embodiment of the present application. Figure 4 Similar to the driving circuit 400 shown in the figure, the driving circuit 500 also has a level voltage generating circuit 410 , a modulation voltage generating circuit 420 , a modulation voltage discharging circuit 430 , and one or more chamfering circuit modules 440 .

[0050] The level voltage generating circuit 410 may include two resistors R1 and R2, which receive the high voltage V GH With low voltage V GL The combined output of the two resistors R1 and R2 is the level voltage V GN . Level voltage V GNCan be a high voltage V GH With low voltage V GL The resistor divider.

[0051] The modulation voltage generating circuit 420 may include three PMOS transistors, namely Figure 5 The transistors P1, P2 and P3 are shown. The gates of the transistors P2 and P3 are connected together, and the source of the transistor P2 is connected to the aforementioned voltage level V GN The drains of transistors P1 and P3 are connected together and coupled to the output stage circuit 460 .

[0052] The modulation voltage discharge circuit 430 may include a PMOS transistor P4 and an NMOS transistor N1. The source of the transistor P4 is coupled to the drains of the aforementioned transistors P1 and P3. The drain of the transistor P4 is connected to the source of the transistor N1. The gate of the transistor N1 is controlled by the NDCG signal. The modulation voltage discharge circuit 430 may be used to discharge the charge.

[0053] The output stage circuit 460 includes four transistors, which receive the high voltage V GH The drain of transistor NO is connected to the low voltage V GL The drain of transistor N2, the source of transistor N3 and the gate of transistor NO are connected together to form a parasitic capacitor C g The gates of transistors N2 and N3 are respectively connected to two inverted signals LS_A and LS_B output by the voltage shift conversion circuit 450. The LS_A signal is also connected to the gate of the PMOS transistor PO. The drain of the PMOS transistor PO and the source of the NMOS transistor NO form an output signal with a falling edge chamfer.

[0054] Please refer to Figure 6 , which is Figure 5 Schematic diagram of signal timing of the driving circuit 500. When the enable signal OEB is activated, the input signal V IN The two inverted signals LS_A and LS_B are pulled high to generate two inverted signals LS_A and LS_B. The two inverted signals LS_A and LS_B are used to control the output stage circuit 460. When the signal LS_A is a low voltage, the PMOS transistor PO is turned on, but the NMOS transistor N2 is turned off. At this time, the signal LS_B is an inverted high voltage, so that the NMOS transistor N3 is turned on and the NMOS transistor NO is turned off. In this way, the output signal V OUT A high voltage level.

[0055] The output signal V OUTDuring the period when the high voltage level is reached, the signal PG1 of the control modulation voltage generating circuit 420 is pulled high to a high level, so that the PMOS transistor P1 is turned off. GH The input of the output stage circuit 460 is cut off. Then, the NCDG signal of the control modulation voltage discharge circuit 430 is pulled high to a high level, so that the transistor N1 is turned on. The charge of the parasitic capacitor Cg in the output stage circuit 460 flows out through the PMOS transistor P4 and the NMOS transistor N1 connected in sequence to the NMOS transistor P2. Figure 6 It can be seen that when the NCDG signal is in the high level period of the square wave, the modulation voltage V GPM Gradually decreasing.

[0056] When the modulation voltage V GPM Gradually drops to a value lower than the on-state voltage of the PMOS transistor P4 |(V GN -V GPM )|, the PMOS transistor P4 is automatically turned off. Then, the PG2 signal drops from a high level to a low level, turning on transistors P3 and P4. In this way, the modulation voltage V GPM It will be pulled up to the voltage level V GN The level.

[0057] At time point t1, after the enable signal OEB is pulled low, the input signal V IN The voltage level conversion circuit 450 outputs a signal LS_A which changes from a low level to a high level, turning off the PMOS transistor PO and turning on the NMOS transistor N2. At the same time, the inverted signal LS_B changes from a high level to a low level, turning off the NMOS transistor N3. Since the NMOS transistor N2 is turned on, it has a voltage level corresponding to V GN The modulation voltage V GPM The gate of NMOS transistor NO is controlled, turning on NMOS transistor NO. Since PMOS transistor PO is turned off and NMOS transistor NO is turned on, the output voltage V OUT Slowly pull to low voltage V GL .

[0058] At time point t2, the enable signal OEB is pulled high again, the gate signal PG2 of the PMOS transistors P2 and P3 turns high, and the gate signal PG1 of the PMOS transistor P1 turns low, turning on the PMOS transistor P1 but turning off the PMOS transistors P2 and P3. In this way, the modulation voltage V GPM is pulled to a high voltage V GH Since at time point t1, NMOS transistor N2 is turned on, with a corresponding high voltage V GH The modulation voltage VGPM Controls the gate of the NMOS transistor NO. The gate control voltage of the NMOS transistor NO and the modulation voltage V GPM Similarly, from the level voltage V GN Pull up to high voltage V GH . In this way, the output voltage V OUT is quickly pulled to the low voltage V GL .

[0059] from Figure 6 The output voltage V OUT From the timing of the circuit, at time point t1, it is first slowly pulled down. Then at time point t2, it is quickly pulled to the low voltage V GL . This forms a falling edge chamfered waveform.

[0060] Please refer to Figure 7 As shown, it is a schematic diagram of different chamfered waveforms according to multiple embodiments of the present application. As mentioned above, the output voltage V with the falling edge chamfer characteristic OUT The change between time points t1 and t2 is due to the gate control signal of the NMOS transistor NO changing from the high voltage V GH Converted down to voltage level V GN After time point t2, the gate control signal level voltage V GN Pull back the high voltage V GH Therefore, as long as the level voltage V output by the level voltage generating circuit 410 is controlled according to the characteristics of the NMOS transistor NO, GN , the speed of the falling edge chamfer can be controlled. If you want to control the level voltage V output by the level voltage generating circuit 410 GN Or resistor voltage division, the resistance values ​​of resistors R1 and R2 can be set.

[0061] Please refer to Figure 8 , which is a circuit diagram of a chamfered circuit module 440 according to another embodiment of the present application. Figure 5 The difference of the chamfered circuit module 440 is that the NMOS transistor N2 is replaced by a PMOS transistor N5. The signal LS_B controls the PMOS transistor N5 and the NMOS transistor N3 at the same time, and the inverted signal LS_A charges the PMOS transistor PO. The source of the PMOS transistor N5 is connected to the modulation voltage V output by the modulation voltage generating circuit 420. GPM .

[0062] Please refer to Fig. 9A As shown, it is the output voltage V when the modulation voltage discharge circuit 430 is missing. OUT Waveform diagram. Between time points t1 and t2, the modulation voltage VGPM From the high voltage V GH Converted down to voltage level V GN At high voltage V GH The parasitic charge stored in the Figure 5 As shown, when there is no modulation voltage discharge circuit 430, these parasitic charges can only be released back to the potential voltage V along the current path IDG1 of the modulation voltage generating circuit 420. GN But generally speaking, the resistance value of the resistor divider is large, resulting in a small discharge current and no way to discharge quickly. Fig. 9A As shown, the modulation voltage V GPM It may be too late to switch from the high voltage V GH Converted down to voltage level V GN .

[0063] Please refer to Fig. 9B As shown, it is the output voltage V when the modulation voltage discharge circuit 430 is provided. OUT Waveform diagram of the output signal V OUT During the high voltage level period, the PG1 signal is pulled high to a high level to turn off the PMOS transistor P1, and then the NDCG signal is used to turn on the transistor N1. PGM Higher than the voltage level V GN When you can Figure 5 The current path IDG2 shown releases the parasitic charge mentioned above. The charge is released sequentially through the PMOS transistor P4 and the NMOS transistor N1, so that the modulation voltage V PGM Can quickly drop from high potential to the threshold voltage V GN When the modulation voltage V PGM is less than its level voltage V GN Absolute pressure difference|(V GN -V GPM )|, the PMOS transistor P4 will automatically turn off. The NDCG signal will then turn off the NMOS transistor N1. Subsequently, the discharge path IDG1 slowly turns off the modulation voltage V PGM Reduce to the threshold voltage V GN , to complete the voltage control required for corner chamfering.

[0064] Even with the current path IDG2 provided by the modulation voltage discharge circuit 430, if the modulation voltage V PGM From high potential to low potential V GN , the modulation voltage V PGM Divide one into two, or one into many. This can reduce the modulation voltage V PGMThe voltage of the parasitic charge can more effectively modulate the voltage V within one cycle. PGM From high potential to low potential V GN .

[0065] Please refer to Fig.10 , which is a block diagram of a driving circuit 1000 according to an embodiment of the present application. Figure 4 Compared with the driving circuit 400 shown in FIG. 1 , the driving circuit 1000 includes two or more sets of modulation voltage generating circuits 420O and 420E, modulation voltage discharge circuits 430O and 430E, and chamfering circuit modules 440O and 440E. Each control signal also has two or more sets. A person skilled in the art can understand that although Fig.10 The embodiment only depicts two sets of circuits, odd (ODD) and even (EVEN), but the present application can be applied to more sets of circuits.

[0066] Please refer to Fig.11 As shown, it is a timing diagram of the enable signal of the driving circuit 1000. Fig.11 The first signal OE is the enable signal of the driving circuit 1000, and its waveform includes multiple square waves. The second signal OE_O is Fig.10 The enable signal used by the odd circuit has a waveform that contains an odd square wave corresponding to the OE signal. Similarly, the third signal OE_O is Fig.10 The enable signal used by the even circuit has an even square wave waveform corresponding to the OE signal. The enable signal OE_O is used to control the input signal V INO Similarly, the enable signal OE_E is used to control the input signal V INE .

[0067] Please refer to Fig.12 As shown, it is a timing diagram of various signals of the driving circuit 1000. Fig.12 The signal on the left corresponds to Fig.10 The odd circuit shown, Fig.12 The signal on the right side corresponds to Fig.10 The even circuit shown. A person skilled in the art can understand that Fig.12 The control signal is as Figure 6 .

[0068] exist Figures 10 to 12 In the embodiment shown, since the interval between the square waves of the signal OE_O and the signal OE_D is twice that of the signal OE, it is possible to ensure that the modulation voltage V PGM From high potential to low potential V GN .

[0069] According to an embodiment of the present application, a driving circuit is provided, characterized in that it includes: a level voltage generating circuit for generating a voltage according to a high voltage V GH With low voltage V GL Generates a voltage level V GN ; A first modulation voltage generating circuit for selecting a first modulation voltage V according to a first control signal GPM At this high voltage V GH With the voltage level V GN and a first chamfering circuit module, comprising a first voltage level conversion circuit and a first output stage circuit, wherein the first output stage circuit comprises a P-type transistor PO, an N-type transistor NO, and a transistor combination, the drain of the P-type transistor PO and the source of the N-type transistor NO are coupled to a first output voltage V OUT , the source of the P-type transistor PO is coupled to the high voltage V GH , the drain of the N-type transistor NO is coupled to the low voltage V GL The first voltage level conversion circuit and the transistor combination are configured to convert the first voltage level into a voltage level according to the two inverted signals output by the first voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO and the N-type transistor NO.

[0070] In order to make the output voltage the high voltage V GH The above driving circuit is characterized in that when the first modulation voltage V GPM At this high voltage V GH and the input signal V IN When the first logic potential is reached, the P-type transistor PO is turned on and the N-type transistor NO is turned off, so that the first output voltage V OUT For the high voltage V GH .

[0071] In order to allow the parasitic charges of the output stage circuit to flow out of the driving circuit quickly, the driving circuit is characterized by further comprising: a first modulation voltage discharge circuit for selectively connecting the first modulation voltage V GPM and the low voltage V GL , when the first modulation voltage V GPM At this high voltage V GH And the first output voltage V OUT For the high voltage V GH When the first modulation voltage discharge circuit is connected to the first modulation voltage V GPM and the low voltage V GL The first modulation voltage V GPM drops to the voltage level V GN .

[0072] In order to allow the parasitic charge of the output stage circuit to flow out of the driving circuit quickly, the driving circuit is characterized in that the first modulation voltage discharge circuit comprises a P-type transistor P4 and an N-type transistor N1, wherein the source of the P-type transistor P4 is connected to the first modulation voltage V GPM The gate of the P-type transistor P4 is connected to the voltage level V GN The drain of the P-type transistor P4 is connected to the source of the N-type transistor N1, and the drain of the N-type transistor N1 is connected to the low voltage V GL The gate of the N-type transistor N1 receives a selection signal NDCG for selectively connecting the first modulation voltage V GPM and the low voltage V GL .

[0073] In order to make the first output voltage V OUT The driving circuit is characterized in that when the first modulation voltage V GPM At this voltage level V GN When the input signal of the first voltage level conversion circuit is a second logic potential corresponding to the first logic potential, the P-type transistor PO is turned off and the N-type transistor NO is turned on, and the gate of the N-type transistor NO is set to the level voltage V GN , so that the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL It descends, forming the first part of the chamfered waveform.

[0074] In order to make the first output voltage V OUT Rapidly drops from the corner to the low voltage V GL The above driving circuit is characterized in that when the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL When the first modulation voltage generating circuit makes the first modulation voltage V GPM At this voltage level V GN Rising to the high voltage V GH , the gate of the N-type transistor NO is set to the high voltage V GH , so that the first output voltage V OUT From this high voltage V GH Rapidly drops to the low voltage V GL , forming the second part of the chamfered waveform.

[0075] In order to provide a level voltage V GNThe driving circuit is characterized in that the level voltage generating circuit further comprises a circuit for receiving the high voltage V GH The first resistor and the low voltage V GL The second resistor, wherein the voltage level V GN is the output of the first resistor and the second resistor.

[0076] In order to control the first output voltage V OUT The chamfered waveform of the driving circuit is characterized in that the resistance values ​​of the first resistor and the second resistor are related to the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL Descending chamfered waveform.

[0077] In order to control the gate voltage of the N-type transistor NO to form the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL The driving circuit is characterized in that the transistor combination comprises an N-type transistor N2 and an N-type transistor N3, wherein the gate of the N-type transistor N2 and the gate of the N-type transistor N3 are respectively connected to the two inverted signals, and the source of the N-type transistor N2 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL , the drain of the N-type transistor N2 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

[0078] In order to control the gate voltage of the N-type transistor NO to form the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL The driving circuit is characterized in that the transistor combination comprises a P-type transistor P5 and an N-type transistor N3, the gate of the P-type transistor P5 and the gate of the N-type transistor N3 are connected to one of the two inverted signals, the other of the two inverted signals is connected to the gate of the P-type transistor PO, and the source of the P-type transistor P5 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL , the drain of the P-type transistor P5 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

[0079] In order to allow the first modulation voltage generating circuit to select the first modulation voltage V according to the first control signal GPM At this high voltage VGH With the voltage level V GN The driving circuit is characterized in that the first modulation voltage generating circuit further comprises: a P-type transistor P1 for selectively connecting the high voltage V according to the PG1 signal in the first control signal. GH and the first modulation voltage V GPM and a P-type transistor P2 and a P-type transistor P3 for selectively connecting the level voltage V according to the PG2 signal among the first control signal GN and the first modulation voltage V GPM .

[0080] In order to provide more output signals, the driving circuit is characterized in that it also includes: a second chamfering circuit module, including a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit includes a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, and the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to form a second output voltage V OUT , the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO2 and the N-type transistor NO2.

[0081] In order to speed up the modulation voltage V PGM From high potential to low potential V GN , and provide more output signals, the above-mentioned driving circuit is characterized in that it also includes: a second modulation voltage generating circuit for selecting a second modulation voltage V according to a second control signal GPM2 At this high voltage V GH With the voltage level V GN and a second chamfering circuit module, comprising a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit comprises a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to a second output voltage V OUT , the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the second modulation voltage V GPMControl the on and off of the P-type transistor PO2 and the N-type transistor NO2.

[0082] According to an embodiment of the present application, a liquid crystal display is provided, characterized in that it includes: a liquid crystal display; and a driving circuit as described above, for converting the first output voltage V OUT Used to control the display of pixels of the liquid crystal display.

[0083] According to the driving circuit provided in each embodiment of the present application, it is possible to provide a chamfering function of a high voltage output signal with lower power consumption, and it is also possible to discharge parasitic charges at a faster speed, so that the driving circuit provided can operate at a higher frequency. When the driving circuit provided is applied to a gate signal driving circuit module of a liquid crystal display screen, it is possible to reduce or avoid feedthrough and mura defects of the liquid crystal display screen, and it is also possible to accelerate the refresh rate of the liquid crystal display screen.

[0084] The main effect of the present application is to use the above transistor combination and voltage level conversion circuit to control the gate voltage of the N-type transistor NO in the output stage circuit, change the equivalent impedance to affect the output pull-down capability to achieve the chamfering function, and also achieve the improved feed-through effect, but without switching the high voltage V in the output stage circuit. GH The voltage of the external large voltage-stabilizing capacitor is charged and discharged, which wastes power consumption.

[0085] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A driving circuit, characterized in that: Include: The level voltage generating circuit is used to generate a voltage according to the high voltage V GH With low voltage V GL Generates a voltage level V GN ; The first modulation voltage generating circuit is used to select the first modulation voltage V according to the first control signal GPM At this high voltage V GH With the voltage level V GN between; and The first chamfering circuit module includes a first voltage level conversion circuit and a first output stage circuit, wherein the first output stage circuit includes a P-type transistor PO, an N-type transistor NO, and a transistor combination, and the drain of the P-type transistor PO and the source of the N-type transistor NO are coupled to form a first output voltage V OUT , the source of the P-type transistor PO is coupled to the high voltage V GH , the drain of the N-type transistor NO is coupled to the low voltage V GL The first voltage level conversion circuit and the transistor combination are configured to convert the first voltage level into a voltage according to the two inverted signals output by the first voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO and the N-type transistor NO.

2. The driving circuit according to claim 1, characterized in that: When the first modulation voltage V GPM At this high voltage V GH and the input signal V IN When the first logic potential is reached, the P-type transistor PO is turned on and the N-type transistor NO is turned off, so that the first output voltage V OUT For the high voltage V GH .

3. The driving circuit according to claim 1, wherein: Also includes: a first modulation voltage discharge circuit, used for selectively connecting the first modulation voltage V GPM and the low voltage V GL , when the first modulation voltage V GPM At this high voltage V GH And the first output voltage V OUT For the high voltage V GH When the first modulation voltage discharge circuit is connected to the first modulation voltage V GPM and the low voltage V GL The first modulation voltage V GPM drops to the voltage level V GN .

4. The driving circuit according to claim 3, characterized in that: The first modulation voltage discharge circuit comprises a P-type transistor P4 and an N-type transistor N1. The source of the P-type transistor P4 is connected to the first modulation voltage V GPM The gate of the P-type transistor P4 is connected to the voltage level V GN The drain of the P-type transistor P4 is connected to the source of the N-type transistor N1, and the drain of the N-type transistor N1 is connected to the low voltage V GL The gate of the N-type transistor N1 receives a selection signal NDCG for selectively connecting the first modulation voltage V GPM and the low voltage V GL .

5. The driving circuit according to claim 2, characterized in that: When the first modulation voltage V GPM At this voltage level V GN When the input signal of the first voltage level conversion circuit is a second logic potential corresponding to the first logic potential, the P-type transistor PO is turned off and the N-type transistor NO is turned on, and the gate of the N-type transistor NO is set to the level voltage V GN , so that the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL It descends, forming the first part of the chamfered waveform.

6. The driving circuit according to claim 5, characterized in that: When the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL When the first modulation voltage generating circuit makes the first modulation voltage V GPM At this voltage level V GN Rising to the high voltage V GH , the gate of the N-type transistor NO is set to the high voltage V GH , so that the first output voltage V OUT From this high voltage V GH Rapidly drops to the low voltage V GL , forming the second part of the chamfered waveform.

7. The driving circuit according to claim 1, characterized in that: The voltage level generating circuit further comprises a circuit for receiving the high voltage V GH The first resistor and the low voltage V GL The second resistor, wherein the voltage level V GN is the output of the first resistor and the second resistor.

8. The driving circuit according to claim 7, characterized in that: The resistance values ​​of the first resistor and the second resistor are related to the first output voltage V OUT From this high voltage V GH Gradually towards the low voltage V GL Descending chamfered waveform.

9. The driving circuit according to claim 1, characterized in that: The transistor combination comprises an N-type transistor N2 and an N-type transistor N3, wherein the gate of the N-type transistor N2 and the gate of the N-type transistor N3 are respectively connected to the two inverted signals, and the source of the N-type transistor N2 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL , the drain of the N-type transistor N2 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

10. The driving circuit according to claim 1, wherein: The transistor combination comprises a P-type transistor P5 and an N-type transistor N3. The gate of the P-type transistor P5 and the gate of the N-type transistor N3 are connected to one of the two inverted signals. The other of the two inverted signals is connected to the gate of the P-type transistor PO. The source of the P-type transistor P5 receives the first modulation voltage V GPM , the drain of the N-type transistor N3 is connected to the low voltage V GL , the drain of the P-type transistor P5 and the source of the N-type transistor N3 are connected to the gate of the N-type transistor NO.

11. The driving circuit according to claim 1, characterized in that: The first modulation voltage generating circuit further comprises: a P-type transistor P1 for selectively connecting the high voltage V GH and the first modulation voltage V GPM and a P-type transistor P2 and a P-type transistor P3 for selectively connecting the level voltage V according to the PG2 signal among the first control signal GN and the first modulation voltage V GPM .

12. The driving circuit according to claim 1, wherein: Also includes: The second chamfering circuit module includes a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit includes a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, and the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to form a second output voltage V OUT , the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the first modulation voltage V GPM Control the on and off of the P-type transistor PO2 and the N-type transistor NO2.

13. The driving circuit according to claim 1, wherein: Also includes: The second modulation voltage generating circuit is used to select the second modulation voltage V according to the second control signal GPM2 At this high voltage V GH With the voltage level V GN between; and The second chamfering circuit module includes a second voltage level conversion circuit and a second output stage circuit, wherein the second output stage circuit includes a P-type transistor PO2, an N-type transistor NO2, and a second transistor combination, and the drain of the P-type transistor PO2 and the source of the N-type transistor NO2 are coupled to form a second output voltage V OUT , the source of the P-type transistor PO2 is coupled to the high voltage V GH , the drain of the N-type transistor NO2 is coupled to the low voltage V GL The second voltage level conversion circuit and the second transistor combination are combined according to the two inverted signals output by the second voltage level conversion circuit and the second modulation voltage V GPM Control the on and off of the P-type transistor PO2 and the N-type transistor NO2.

14. A liquid crystal display, characterized in that: Include: Liquid crystal display; and The driving circuit according to any one of claims 1 to 13, used to convert the first output voltage V OUT Used to control the display of pixels of the liquid crystal display.

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