Multi-channel silicon carbide MOSFET and method for manufacturing the same

Abstract

The invention discloses a multi-channel silicon carbide MOSFET and a manufacturing method thereof, comprising a drain; a substrate; an epitaxial layer; a first well region; a first source region; a contact region; an upper groove, which runs through the first source region and the first well region, the depth of the upper groove is greater than the depth of the first well region, and the difference between the depths of the two is not less than 0.1µm; a lower groove, which is located below the upper groove and is connected to the upper groove, and the width of the lower groove is less than the width of the upper groove; a second well region; a second source region, the width and depth of the second source region are both smaller than the second well region, and the distance between the boundaries of the two ranges from 0.1µm to 0.4µm; a third well region; a third source region, the width and depth of the third source region are both smaller than the third well region; a gate dielectric; a T-shaped conductive material; an isolation dielectric; a source electrode; the invention can realize the regulation of the length of the conductive channel, greatly enhance the current carrying capacity of the device, and significantly reduce the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-channel silicon carbide MOSFET and a manufacturing method thereof. Background Art

[0002] The development of the power electronics industry has made it increasingly difficult for silicon devices to meet the increasingly stringent application requirements. Silicon carbide (SiC) material has become one of the most important semiconductor materials for making high-power devices that can adapt to extreme environments due to its excellent physical and chemical properties.

[0003] Silicon carbide-SiC metal oxide semiconductor field effect transistor (MOSFET) has attracted widespread attention due to its advantages such as simple gate drive and unipolar conduction. The two mainstream SiC MOSFET power devices currently include planar gate SiC MOSFET devices and trench gate SiC MOSFET devices. The former has a low channel mobility and a parasitic junction field effect transistor structure, both of which limit the device's conduction capability. The latter makes conductive channels on different crystal planes to achieve higher channel mobility; at the same time, the introduction of trenches eliminates the parasitic junction field effect transistor structure, reduces the cell size, and further reduces the device's on-resistance.

[0004] However, the reliability of trench-gate SiC MOSFET devices needs to be improved urgently. The key problem is that the electric field concentration effect at the bottom corner of the trench under high voltage will affect the reliability of the gate dielectric, causing the device to break down prematurely. In addition, since the interface state density of the SiC / SiO2 interface is more than two orders of magnitude larger than that of Si / SiO2, the channel mobility of SiC MOSFET is always far lower than theoretical expectations, resulting in too large a channel resistance of the device. The currently used NO annealing and other solutions cannot significantly improve the channel mobility. Summary of the invention

[0005] Technical purpose: In view of the shortcomings of existing trench-gate SiC MOSFET devices, the present invention discloses a multi-channel silicon carbide MOSFET and a manufacturing method thereof, which sets multiple parallel conductive channels in the cell, significantly improving the current carrying capacity of the device and effectively protecting the gate dielectric.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:

[0007] A multi-channel silicon carbide MOSFET, comprising:

[0008] Drain;

[0009] a substrate, located above the drain;

[0010] an epitaxial layer, located on the substrate;

[0011] A first well region is located on the epitaxial layer;

[0012] A first source region, located in the first well region and having a width smaller than the first well region;

[0013] A contact region, located in the first well region and on both sides of the first source region, and adjacent to the first source region;

[0014] An upper trench, passing through the first source region and the first well region, wherein the depth of the upper trench is greater than the depth of the first well region, and the difference between the depths of the upper trench and the first well region is not less than 0.1 μm;

[0015] A lower groove is located below the upper groove and communicated with the upper groove, and a width of the lower groove is smaller than a width of the upper groove;

[0016] A second well region is located below the upper trench and on both sides of the lower trench, and the depth of the second well region is less than the depth of the lower trench;

[0017] A second source region is located in the second well region, the width and depth of the second source region are smaller than the second well region, and the distance between the boundaries of the second source region and the second well region is in the range of 0.1µm to 0.4µm;

[0018] A third well region is located in the epitaxial layer and surrounds the bottom surface and part of the side surface of the lower trench;

[0019] A third source region is located in the third well region and surrounds the bottom surface and part of the side surface of the lower trench. The width and depth of the third source region are smaller than the third well region. The distance between the boundaries of the third source region and the third well region is in the range of 0.1µm to 0.4µm.

[0020] A gate dielectric is located on the sidewalls and bottom of the upper trench and the lower trench;

[0021] T-shaped conductive material is located in the upper trench and the lower trench;

[0022] An isolation dielectric is located on the epitaxial layer, completely covers the T-shaped conductive material and is located on the first source region on both sides;

[0023] The source is located on the isolation medium and surrounds the isolation medium on three sides.

[0024] The present invention also provides a method for manufacturing a multi-channel silicon carbide MOSFET, which is used to manufacture the multi-channel silicon carbide MOSFET described above, comprising the following steps:

[0025] Step 1: forming a first portion of an epitaxial layer on a substrate by an epitaxial growth process;

[0026] Step 2: forming a third well region and a third source region in the first part of the epitaxial layer by an ion implantation process, wherein the third source region is located in the third well region and has a width and a depth smaller than the third well region;

[0027] Step 3: forming a second portion of the epitaxial layer by an epitaxial growth process, and forming a second well region and a second source region in the second portion of the epitaxial layer by an ion implantation process, wherein the second source region is located in the second well region and has a width and a depth smaller than the second well region;

[0028] Step 4: forming the remaining epitaxial layer by an epitaxial process, and forming a first well region in the remaining epitaxial layer by an ion implantation process;

[0029] Step 5: forming a first source region and a contact region on the surface of the device prepared in step 4 by an ion implantation process, wherein the first source region and the contact region are both located in the first well region, and the contact region is located on both sides of the first source region and is adjacent to the first source region;

[0030] Step 6: Remove the structure from the device surface to part of the third source region formed in step 5 by etching process to form an upper trench and a lower trench connected to each other, wherein the upper trench runs through the first well region and the first source region, the lower trench runs through the second well region and the second source region, the lower bottom surface extends to the third source region, and the width of the upper trench is greater than the width of the lower trench;

[0031] Step 7: forming a gate dielectric on the sidewalls and bottom surfaces of the upper trench and the lower trench by a low-pressure chemical vapor deposition process or a thermal oxidation process, and forming a T-shaped conductive material in the upper trench and the lower trench by a low-pressure chemical vapor deposition process;

[0032] Step eight, forming an isolation dielectric that completely covers the T-shaped conductive material on the epitaxial layer, with both sides of the isolation dielectric located on the first source region, depositing source metal on both sides and on the isolation dielectric to form a source ohmic contact, depositing drain metal on the bottom layer of the substrate to form a drain ohmic contact, forming a source on the surface of the source ohmic contact, and forming a drain on the surface of the drain ohmic contact.

[0033] Beneficial effects: The multi-channel silicon carbide MOSFET and the manufacturing method thereof provided by the present invention have the following beneficial effects:

[0034] (1) The multi-channel silicon carbide MOSFET proposed in the present invention has a gate trench formed by interconnected upper and lower trenches, a T-shaped conductive material is formed in the gate trench, a second well region, a second source region, a third well region and a third source region are formed on both sides and below the gate trench, and in addition to the conductive channels possessed by the conventional trench-gate silicon carbide MOSFET cell structure, six parallel conductive channels are integrated to form a total of eight conductive channels. By adjusting the process parameters of the gate trench and the doping region, the length of the conductive channel can be controlled, thereby greatly enhancing the current carrying capacity of the device and significantly reducing the on-resistance of the device.

[0035] (2) The multi-channel silicon carbide MOSFET proposed in the present invention has a second well region and a third well region arranged on the sidewall and bottom of the lower trench, which can effectively protect the gate dielectric, avoid premature breakdown of the gate dielectric, and ensure device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0037] Figure 1 Schematic diagram of a multi-channel silicon carbide MOSFET according to Embodiment 1 of the present invention;

[0038] Figure 2 Schematic diagram of a multi-channel silicon carbide MOSFET according to Embodiment 2 of the present invention;

[0039] Figure 3 Schematic diagram of a multi-channel silicon carbide MOSFET according to Embodiment 3 of the present invention;

[0040] Figure 4 is a flow chart of a method for manufacturing a multi-channel silicon carbide MOSFET in Example 1 of the present invention;

[0041] Figure 5~Figure 12 Schematic diagram of the preparation process of the multi-channel silicon carbide MOSFET according to Example 1 of the present invention.

[0042] Explanation of the accompanying drawings: 1. drain; 2. substrate; 3. epitaxial layer; 4. third well region; 5. third source region; 6. second well region; 7. second source region; 8. first well region; 9. contact region; 10. first source region; 11. gate dielectric; 12. T-type conductive material; 13. isolation dielectric; 14. source; 15. first current extension region; 16. second current extension region; 101. upper trench; 102. lower trench. DETAILED DESCRIPTION

[0043] The present invention will be described more clearly and completely below by way of a preferred embodiment in conjunction with the accompanying drawings, but the present invention is not limited to the scope of the embodiment.

[0044] Example 1

[0045] like Figure 1 As shown, a multi-channel silicon carbide MOSFET includes: a drain 1, the material of the drain 1 can be one or more metals such as Ti, Al, Ag, Au, etc.; a substrate 2, located on the drain 1 and the lower surface of which is in contact with the upper surface of the drain 1; an epitaxial layer 3, located on the substrate 2 and the lower surface of which is in contact with the upper surface of the substrate 2, the depth of the epitaxial layer 3 ranges from 5µm to 100µm, and the doping concentration is 1e15cm -3 ~1e17cm-3 The first well region 8 is located on the epitaxial layer 3 and the lower surface is in contact with the lower surface of the epitaxial layer 3. The depth of the first well region 8 is in the range of 0.5µm to 1.5µm, and the doping concentration is 5e16cm -3 ~5e17cm -3 The first source region 10 is located in the first well region 8 and has a width smaller than the first well region 8. The depth of the first source region 10 is in the range of 0.2µm to 0.5µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 The contact region 9 is located in the first well region 8, on both sides of the first source region 10 and adjacent to the first source region 10. The depth of the contact region ranges from 0.2µm to 0.5µm. The depth of the contact region 9 is not necessarily equal to the depth of the first source region 10. The doping concentration is 1e19cm -3 ~1e20cm -3 , the upper surfaces of the first well region 8 , the first source region 10 and the contact region 9 are flush with the upper surface of the epitaxial layer 3 ;

[0046] An upper trench 101 runs through the first source region 10 and the first well region 8, the depth of the upper trench 101 ranges from 0.7µm to 2.0µm, the width ranges from 1.5µm to 3.5µm, the depth of the upper trench 101 is greater than the depth of the first well region 8, and the difference between the depths of the two is not less than 0.1µm; a lower trench 102 is located below the upper trench 101 and is connected to the upper trench 101, the depth of the lower trench 102 ranges from 0.4µm to 1.5µm, the width ranges from 1.0µm to 3.0µm, the width of the lower trench 102 is less than the width of the upper trench 101, and the difference between the two is not less than 0.5µm, and the upper trench 101 and the lower trench 102 constitute a gate trench;

[0047] The second well region 6 is located below the upper trench 101 and on both sides of the lower trench 102. The depth of the second well region 6 ranges from 0.3µm to 0.7µm, and the doping concentration is 5e16cm -3 ~5e17cm -3 , the depth of the second well region 6 is less than the depth of the lower trench 102; the second source region 7 is located in the second well region 6, the depth of the second source region 7 ranges from 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 The width and depth of the second source region 7 are smaller than the second well region 6, and the distance between the two boundaries ranges from 0.1µm to 0.4µm. The upper surfaces of the second well region 6 and the second source region 7 are in contact with the lower bottom surface of the upper trench 101, and one side surface of both is in contact with the side surface of the lower trench 102. The third well region 4 is located in the epitaxial layer 3 and surrounds the bottom surface and part of the side surface of the lower trench 102. The depth of the third well region 4 is 0.3µm to 0.7µm, and the doping concentration is 5e16cm-3 ~5e17cm -3 The third source region 5 is located in the third well region 4 and surrounds the bottom surface and part of the side surface of the lower trench 102. The depth of the third source region 5 is in the range of 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 , the width and depth of the third source region 5 are smaller than the third well region 4, and the distance between the boundaries of the two ranges from 0.1µm to 0.4µm;

[0048] The gate dielectric 11 is located on the sidewalls and bottom of the upper trench 101 and the lower trench 102. The thickness of the gate dielectric 11 is uniform and the thickness ranges from 30nm to 100nm. The material of the gate dielectric 11 can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide. The T-shaped conductive material 12 is located in the upper trench 101 and the lower trench 102. The T-shaped conductive material can be metal or doped polysilicon. The isolation dielectric 13 is located on the epitaxial layer 3, completely covers the T-shaped conductive material 12 and is located on both sides of the first source region 10. The isolation dielectric 13 can be silicon dioxide or nitride or a composite of silicon dioxide and nitride. The source 14 is located on the isolation dielectric 13 and surrounds the isolation dielectric 13 on three sides. The material of the source 14 can be one or more metals such as Ti, Al, Ni, Cu, Au, etc. The semiconductor material used in the device of the present invention can be 3C-SiC, 4H-SiC or 6H-SiC.

[0049] Among them, Figure 1In the area marked by the middle arrow, two longitudinal conductive channels are formed between the first well region 8 and the second well region 6, two transverse and two longitudinal conductive channels are formed between the second well region 6 and the second source region 7, and two longitudinal conductive channels are formed between the third well region 4 and the third source region 5, forming a total of eight conductive channels, wherein the four conductive channels formed by the second well region 6 and the second source region 7 and the two conductive channels formed by the third well region 4 and the third source region 5 form six parallel conductive channels, and at the same time, the difference in width between the lower trench 102 and the upper trench 101 is not less than 0.5µm, the difference in depth range between the upper trench 101 and the first well region 8 is not less than 0.1µm, the width of the first source region 10 is smaller than that of the first well region 8, and the width of the second source region 7 is smaller than that of the second well region 8. The distance between the boundaries of the well region 6 ranges from 0.1µm to 0.4µm, and the distance between the boundaries of the third source region 5 and the third well region 4 ranges from 0.1µm to 0.4µm. Therefore, by adjusting the width and depth of the gate trench, as well as the depth or width of the well region or source region, the size of the conductive channel formed between the gate trench and the well region and the source region can be changed, thereby realizing the regulation of the conductive channel length, greatly enhancing the current carrying capacity of the device, and significantly reducing the on-resistance of the device; the first well region 8, the second well region 6, the third well region 4, the first source region 10, the second source region 7 and the third source region 5 are all short-circuited with the source 14, and the short-circuiting is realized in the depth direction of the device, which can ensure that each well region and source region function normally in each working quadrant.

[0050] like Figure 4 As shown, the present invention also provides a method for manufacturing a multi-channel silicon carbide MOSFET, which is used to prepare the multi-channel silicon carbide MOSFET described above, comprising the following steps:

[0051] Step 1: Figure 5 As shown, a first partial epitaxial layer is formed on the substrate 2 by an epitaxial growth process;

[0052] Step 2: Figure 6 As shown, a third well region 4 and a third source region 5 are formed in the first part of the epitaxial layer by an ion implantation process. The third source region 5 is located in the third well region 4 and has a width and a depth smaller than the third well region 4. Two longitudinal conductive channels are formed between the two sides near the lower trench 102. The depth of the third well region 4 ranges from 0.3µm to 0.7µm, and the doping concentration is 5e16cm -3 ~ 5e17cm -3 The depth of the third source region 5 ranges from 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~ 1e20cm -3 , the distance between the two boundaries ranges from 0.1µm to 0.4µm;

[0053] Step 3: Figure 7As shown, a second part of the epitaxial layer is formed by an epitaxial growth process, and a second well region 6 and a second source region 7 are formed in the second part of the epitaxial layer by an ion implantation process. The second source region 7 is located in the second well region 6 and has a width and a depth smaller than the second well region 6. Two lateral conductive channels are formed between the two near the bottom surface of the upper trench 101, and two vertical conductive channels are formed near the two sides of the lower trench 102. The depth of the second well region 6 is 0.3µm ~ 0.7µm, and the doping concentration is 5e16cm -3 ~ 5e17cm -3 The depth of the second source region 7 is 0.1µm ~ 0.3µm, and the doping concentration is 1e19cm -3 ~ 1e20cm -3 , the distance between the two boundaries ranges from 0.1µm to 0.4µm;

[0054] Step 4: Figure 8 As shown, the remaining epitaxial layer is formed by an epitaxial process, and the first well region 8 is formed in the remaining epitaxial layer by an ion implantation process. The depth of the first well region 8 is in the range of 0.5µm to 1.5µm, and the doping concentration is 5e16cm -3 ~5e17cm -3 , the partial epitaxial layers formed in step 1, step 3 and step 4 together constitute epitaxial layer 3;

[0055] Step 5: Fig. 9 As shown, a first source region 10 and a contact region 9 are formed on the surface of the device prepared in step 4 by an ion implantation process. The first source region 10 and the contact region 9 are both located in the first well region 8. The contact region 9 is located on both sides of the first source region 10 and is adjacent to the first source region 10. The depth of the first source region 10 ranges from 0.2µm to 0.5µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 The depth of contact region 9 ranges from 0.2µm to 0.5µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 ;

[0056] Step 6: Fig.10As shown, the structure from the device surface to part of the third source region 5 formed in step five is removed by an etching process to form an upper trench 101 and a lower trench 102 that are interconnected. The upper trench 101 penetrates the first well region 8 and the first source region 10, and the lower trench 102 penetrates the second well region 6 and the second source region 7. The bottom surface extends to the third source region 5. The depth of the upper trench 101 ranges from 0.7µm to 2.0µm, and the width ranges from 1.5µm to 3.5µm. The depth of the lower trench 102 ranges from 0.4µm to 1.5µm, and the width ranges from 1.0µm to 3.0µm. The width of the upper trench 101 is greater than that of the lower trench 102, and the difference between the widths is not less than 0.5µm. In this step, an inductively coupled plasma (ICP) etching process may be used, and the etching gas used may be one or more of SF6, HBr, Cl2, O2, Ar, and the like.

[0057] Step 7: Fig.11 As shown, a gate dielectric 11 is formed on the sidewalls and bottom surfaces of the upper trench 101 and the lower trench 102 by low pressure chemical vapor deposition (LPCVD) or thermal oxidation process, and the gate dielectric 11 material is SiO2 with a thickness of 30nm-100nm. A T-shaped conductive material 12 is formed in the upper trench 101 and the lower trench 102 by the LPCVD process, and the material of the T-shaped conductive material 12 is polysilicon, and the T-shaped conductive material 12 is implanted and activated by annealing;

[0058] Step 8: Fig.12 As shown, an isolation dielectric 13 is formed on the epitaxial layer 3 to completely cover the T-shaped conductive material 12, and both sides of the isolation dielectric 13 are located on the first source region 10. A source metal is deposited on both sides and on the isolation dielectric 13 to form a source ohmic contact, a drain metal is deposited on the bottom layer of the substrate 2 to form a drain ohmic contact, a source 14 is formed on the surface of the source ohmic contact, and a drain 1 is formed on the surface of the drain ohmic contact.

[0059] Example 2

[0060] like Figure 2 The multi-channel silicon carbide MOSFET shown in the embodiment is different from the embodiment 1 in that a first current extension region 15 is formed between the first well region 8 and the second well region 6, and the doping type of the first current extension region 15 is the first type, the depth is 0.2µm~1.0µm, and the doping concentration is 1e16cm -3 ~1e17cm -3 , the first current extension region 15 can further reduce the on-resistance of the device.

[0061] The specific steps of manufacturing the multi-channel silicon carbide MOSFET of this embodiment are as follows:

[0062] Step 1: forming a first portion of an epitaxial layer on the substrate 2 by an epitaxial growth process;

[0063] Step 2: forming a third well region 4 and a third source region 5 in the first part of the epitaxial layer by an ion implantation process, wherein the third source region 5 is located in the third well region 4 and has a smaller width and depth than the third well region 4;

[0064] Step 3: forming a second portion of the epitaxial layer by an epitaxial growth process, and forming a second well region 6 and a second source region 7 in the second portion of the epitaxial layer by an ion implantation process, wherein the second source region 7 is located in the second well region 6 and has a smaller width and depth than the second well region 6;

[0065] Step 4: forming the remaining epitaxial layer by an epitaxial process, forming a first current extension region 15 in the remaining epitaxial layer by an ion implantation process, and forming a first well region 8 on the first current extension region 15 and in the remaining epitaxial layer by an ion implantation process, wherein the upper surface of the first current extension region 15 is flush with or not flush with the lower bottom surface of the first well region 8;

[0066] Step 5: forming a first source region 10 and a contact region 9 on the surface of the device prepared in step 4 by an ion implantation process;

[0067] Step 6: Remove the structure from the device surface to a part of the third source region 5 formed in step 5 by an etching process to form an upper trench 101 and a lower trench 102 that are interconnected, wherein the upper trench 101 penetrates the first well region 8 and the first source region 10, and the lower trench 102 penetrates the second well region 6 and the second source region 7, and the lower bottom surface extends into the third source region 5, wherein the lower bottom surface of the upper trench 101 is located below the lower bottom surface of the first current extension region 15 or is flush with the lower bottom surface of the first current extension region 15;

[0068] Step 7: Form a gate dielectric 11 on the sidewalls and bottom surfaces of the upper trench 101 and the lower trench 102 by an LPCVD process or a thermal oxidation process, form a T-shaped conductive material 12 in the upper trench 101 and the lower trench 102 by an LPCVD process, and perform implantation and activation annealing on the T-shaped conductive material 12;

[0069] Step eight, an isolation dielectric 13 is formed on the epitaxial layer 3 to completely cover the T-shaped conductive material 12, and both sides of the isolation dielectric 13 are located on the first source region 10. Source metal is deposited on both sides and on the isolation dielectric 13 to form a source ohmic contact, and a drain metal is deposited on the bottom layer of the substrate 2 to form a drain ohmic contact. A source 14 is formed on the surface of the source ohmic contact, and a drain 1 is formed on the surface of the drain ohmic contact.

[0070] Example 3

[0071] like Figure 3 The multi-channel silicon carbide MOSFET shown in the embodiment is different from the embodiment 1 in that a second current extension region 16 is formed between the second well region 6 and the third well region 4, and the doping type of the second current extension region 16 is the first type, the depth is 0.4µm~1.5µm, and the doping concentration is 1e16cm -3 ~ 1e17cm -3 , the second current extension region 16 can further reduce the on-resistance of the device.

[0072] The specific steps of manufacturing the multi-channel silicon carbide MOSFET of this embodiment are as follows:

[0073] Step 1: forming a first portion of an epitaxial layer on the substrate 2 by an epitaxial growth process;

[0074] Step 2: forming a third well region 4 and a third source region 5 in the first part of the epitaxial layer by an ion implantation process, wherein the third source region 5 is located in the third well region 4 and has a smaller width and depth than the third well region 4;

[0075] Step 3, forming a second partial epitaxial layer by an epitaxial growth process, forming a second current extension region 16 in the second partial epitaxial layer by an ion implantation process, forming a second well region 6 and a second source region 7 on the second current extension region 16 by an ion implantation process, the second source region 7 is located in the second well region 6 and has a width and a depth smaller than the second well region 6, the upper surface of the second current extension region 16 is flush with the lower bottom surface of the second well region 6 or is located below the lower bottom surface of the second well region 6, and the lower bottom surface of the second current extension region 16 is flush with the upper surface of the third well region 4 or is located above the upper surface of the third well region 4;

[0076] Step 4: forming the remaining epitaxial layer by an epitaxial process, and forming a first well region 8 in the remaining epitaxial layer by an ion implantation process;

[0077] Step 5: forming a first source region 10 and a contact region 9 on the surface of the device prepared in step 4 by an ion implantation process;

[0078] Step 6: Remove the structure from the device surface to a part of the third source region 5 formed in step 5 by an etching process to form an upper trench 101 and a lower trench 102 that are interconnected, wherein the upper trench 101 penetrates the first well region 8 and the first source region 10, and the lower trench 102 penetrates the second well region 6 and the second source region 7, and the lower bottom surface extends into the third source region 5, wherein the lower bottom surface of the upper trench 101 is located below the lower bottom surface of the second current extension region 16 or is flush with the lower bottom surface of the second current extension region 16;

[0079] Step 7: Form a gate dielectric 11 on the sidewalls and bottom surfaces of the upper trench 101 and the lower trench 102 by an LPCVD process or a thermal oxidation process, form a T-shaped conductive material 12 in the upper trench 101 and the lower trench 102 by an LPCVD process, and perform implantation and activation annealing on the T-shaped conductive material 12;

[0080] Step eight, an isolation dielectric 13 is formed on the epitaxial layer 3 to completely cover the T-shaped conductive material 12, and both sides of the isolation dielectric 13 are located on the first source region 10. Source metal is deposited on both sides and on the isolation dielectric 13 to form a source ohmic contact, and a drain metal is deposited on the bottom layer of the substrate 2 to form a drain ohmic contact. A source 14 is formed on the surface of the source ohmic contact, and a drain 1 is formed on the surface of the drain ohmic contact.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-channel silicon carbide MOSFET, characterized in that: include: Drain; a substrate, located above the drain; an epitaxial layer, located on the substrate; A first well region is located on the epitaxial layer; A first source region, located in the first well region and having a width smaller than the first well region; A contact region, located in the first well region and on both sides of the first source region, and adjacent to the first source region; An upper trench, passing through the first source region and the first well region, wherein the depth of the upper trench is greater than the depth of the first well region, and the difference between the depths of the upper trench and the first well region is not less than 0.1 μm; A lower groove is located below the upper groove and communicated with the upper groove, and a width of the lower groove is smaller than a width of the upper groove; A second well region is located below the upper trench and on both sides of the lower trench, and the depth of the second well region is less than the depth of the lower trench; A second source region is located in the second well region, the width and depth of the second source region are smaller than the second well region, and the distance between the boundaries of the second source region and the second well region is in the range of 0.1µm to 0.4µm; A third well region is located in the epitaxial layer and surrounds the bottom surface and part of the side surface of the lower trench; A third source region is located in the third well region and surrounds the bottom surface and part of the side surface of the lower trench. The width and depth of the third source region are smaller than the third well region. The distance between the boundaries of the third source region and the third well region is in the range of 0.1µm to 0.4µm. A gate dielectric is located on the sidewalls and bottom of the upper trench and the lower trench; T-shaped conductive material is located in the upper trench and the lower trench; An isolation dielectric is located on the epitaxial layer, completely covers the T-shaped conductive material and is located on the first source region on both sides; A source electrode is located on the isolation medium and surrounds the isolation medium on three sides; The first well region, the second well region, the third well region, the first source region, the second source region and the third source region are all short-circuited with the source electrode.

2. A multi-channel silicon carbide MOSFET according to claim 1, characterized in that: A first current extension region is formed between the first well region and the second well region. The doping type of the first current extension region is the first type, the depth range is 0.2µm~1.0µm, and the doping concentration is 1e16cm -3 ~1e17cm -3 .

3. A multi-channel silicon carbide MOSFET according to claim 1, characterized in that: A second current extension region is formed between the second well region and the third well region. The doping type of the second current extension region is the first type, the depth range is 0.4µm~1.5µm, and the doping concentration is 1e16cm -3 ~1e17cm -3 .

4. A multi-channel silicon carbide MOSFET according to claim 1, characterized in that: The depth of the first well region ranges from 0.5µm to 1.5µm, the depth of the second well region ranges from 0.3µm to 0.7µm, and the depth of the third well region ranges from 0.3µm to 0.7µm. The doping concentration of the first well region, the second well region, and the third well region is 5e16cm -3 ~5e17cm -3 .

5. The multi-channel silicon carbide MOSFET according to claim 1, characterized in that: The depth of the first source region is in the range of 0.2µm to 0.5µm, the depth of the second source region is in the range of 0.1µm to 0.3µm, and the depth of the third source region is in the range of 0.1µm to 0.3µm. The doping concentration of the first source region, the second source region, and the third source region is 1e19cm -3 ~1e20cm -3 .

6. The multi-channel silicon carbide MOSFET according to claim 1, characterized in that: The depth of the upper groove ranges from 0.7µm to 2.0µm, and the width ranges from 1.5µm to 3.5µm. The depth of the lower groove ranges from 0.4µm to 1.5µm, and the width ranges from 1.0µm to 3.0µm. The difference in width between the upper groove and the lower groove is not less than 0.5µm.

7. The multi-channel silicon carbide MOSFET according to claim 1, characterized in that: The contact area depth ranges from 0.2µm to 0.5µm, and the doping concentration is 1e19cm -3 ~1e20cm -3 .

8. The multi-channel silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the gate dielectric is uniform, ranging from 30nm to 100nm.

9. A method for manufacturing a multi-channel silicon carbide MOSFET, used to manufacture a multi-channel silicon carbide MOSFET according to any one of claims 1 to 8, characterized in that: The following steps are involved: Step 1: forming a first portion of an epitaxial layer on a substrate by an epitaxial growth process; Step 2: forming a third well region and a third source region in the first part of the epitaxial layer by an ion implantation process, wherein the third source region is located in the third well region and has a width and a depth smaller than the third well region; Step 3: forming a second portion of the epitaxial layer by an epitaxial growth process, and forming a second well region and a second source region in the second portion of the epitaxial layer by an ion implantation process, wherein the second source region is located in the second well region and has a width and a depth smaller than the third well region; Step 4: forming the remaining epitaxial layer by an epitaxial process, and forming a first well region in the remaining epitaxial layer by an ion implantation process; Step 5: forming a first source region and a contact region on the surface of the device prepared in step 4 by an ion implantation process, wherein the first source region and the contact region are both located in the first well region, and the contact region is located on both sides of the first source region and is adjacent to the first source region; Step 6: Remove the structure from the device surface to part of the third source region formed in step 5 by etching process to form an upper trench and a lower trench connected to each other, wherein the upper trench runs through the first well region and the first source region, the lower trench runs through the second well region and the second source region, the lower bottom surface extends to the third source region, and the width of the upper trench is greater than the width of the lower trench; Step 7: forming a gate dielectric on the sidewalls and bottom surfaces of the upper trench and the lower trench by a low-pressure chemical vapor deposition process or a thermal oxidation process, and forming a T-shaped conductive material in the upper trench and the lower trench by a low-pressure chemical vapor deposition process; Step eight, forming an isolation dielectric that completely covers the T-shaped conductive material on the epitaxial layer, with both sides of the isolation dielectric located on the first source region, depositing source metal on both sides and on the isolation dielectric to form a source ohmic contact, depositing drain metal on the bottom layer of the substrate to form a drain ohmic contact, forming a source on the surface of the source ohmic contact, and forming a drain on the surface of the drain ohmic contact.

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