A semiconductor electronic component electroplating rack and electroplating method

Abstract

The present invention discloses a semiconductor electronic component electroplating hanger and an electroplating method, which relate to the field of semiconductor electroplating technology. The hanger includes a pair of shells and a pair of masks. The masks are made of flexible deformable materials and are used to shield the non-electroplating area of ​​the workpiece to be plated. The corresponding positions of the shells and the masks are provided with hollow areas, and the shape of the hollow areas corresponds to the area to be plated of the workpiece to be plated. A locking mechanism is provided between the two shells to fix the two shells, and at the same time, the mask located in the shell is pressed against the surface of the workpiece to be plated to form a seal. Through the precise shielding characteristics of the mask, the function of local electroplating of semiconductor electronic components is realized. The precise local electroplating semiconductor electronic components provided by the mask can solve the technical problems such as lack of electroplating precision and lack of plating of electronic products, and achieve the goal of improving the stability and reliability of semiconductor electronic component products, as well as producing and manufacturing high-performance and high-precision semiconductor electronic components.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor coating, and in particular to a semiconductor electronic component electroplating rack and an electroplating method. Background Art

[0002] The gold plating layer of semiconductor electronic components has the characteristics of dense surface, corrosion resistance, and excellent conductivity. It is widely used in semiconductor electronic component products in the fields of new energy vehicles, aerospace, communications, etc., especially high-precision high-power electronic products. Gold plating is the preferred electroplating process. Therefore, in recent years, in the field of electronic product manufacturing, the development trend of high-end electroplating manufacturing gold plating is unstoppable.

[0003] At present, high-end semiconductor electronic component products have increasingly higher requirements for gold plating technology. The high-end design of electronic products in the fields of aerospace electronics, new energy automotive electronics, and communications requires not only high precision in the gold-plated area, but also high production capacity and low budget. Therefore, high-precision local electroplating hangers and electroplating methods are needed to solve the continuous development of semiconductor electronic component products towards high-end electroplating technology.

[0004] The rack plating processing of semiconductor electronic component products usually uses a rack to process the entire plated part. However, with the high-end precision design of electronic products in the fields of new energy vehicle electronic products, aerospace electronic products and communications, the demand for local electroplating of semiconductor electronic components is increasing, and the precision requirements are also getting higher and higher. Under this high-end demand development trend, although the use of special electroplating tape to fit and mask the non-plated area of ​​the plated part is an effective method, this method can only be applied to relatively flat semiconductor electronic components, and cannot meet the requirements of local electroplating for plated parts with complex shapes. In addition, even for flat plated products, the fitting effect of special electroplating masking tape is different depending on the electroplating solution and the length of electroplating time. The electroplating solution often penetrates into the non-plated area and the fitting tape falls off, resulting in an increase in the missing rate of local electroplated products. It cannot meet the demand of the high-end electronic product market for precision local electroplating products.

[0005] There are currently no literature reports on solutions to the above-mentioned technical problems. The existence of scientific problems and technical difficulties in the field of mounting plating technology for semiconductor electronic component products has hindered the growing demand for high-end precision electronic materials in the aerospace, new energy vehicle, and communications electronics industries, and is a research topic that urgently needs innovative breakthroughs. Summary of the invention

[0006] The technical problem to be solved by the present invention is that the use of tape masking for local electroplating in the prior art easily causes the electroplating solution to penetrate into the non-electroplating area and the bonding tape to fall off.

[0007] The semiconductor electronic component electroplating rack provided by the present invention comprises a pair of shells and a pair of masks; a groove is arranged in the shell for accommodating the mask and the workpiece to be plated, the mask corresponds to the shell one-to-one, the mask is made of a flexible deformable material, and is used to shield the non-electroplating area of ​​the workpiece to be plated, and hollow areas are arranged at corresponding positions of the shell and the mask, and the shape of the hollow area corresponds to the area to be plated of the workpiece to be plated; a locking mechanism is arranged between the two shells for fixing the two shells, and at the same time pressing the mask located in the shell against the surface of the workpiece to be plated to form a seal.

[0008] Furthermore, the superimposed thickness of the mask and the workpiece to be plated is greater than the thickness of the accommodating space formed by the two housing grooves.

[0009] Preferably, the difference between the superimposed thickness of the mask and the workpiece to be plated and the thickness of the accommodating space formed by the two housing grooves is 0.45-1.35 mm, and the thickness of the mask is preferably 1.4-3.3 mm.

[0010] Furthermore, it also includes a positioning mechanism, which is used to achieve the overlapping of the two shells.

[0011] Furthermore, the positioning mechanism includes a positioning hole and a matching positioning pin, the positioning hole is located on one of the shells, and the positioning pin is located on the other shell.

[0012] Preferably, the mask is made of polysiloxane.

[0013] Furthermore, the mask is pasted in the housing groove.

[0014] Furthermore, the locking mechanism includes screw holes and screws, and the two shells are fixed by the screws.

[0015] In addition, the present invention also provides an electroplating method for a semiconductor electronic component mold, using the electroplating rack as described above, comprising the following steps:

[0016] Step S1, performing alkali degreasing and acid activation treatment on the plated parts;

[0017] Step S2, performing a bottom nickel plating process on the plated part;

[0018] Step S3, according to the electroplating area and form of the plated part, select multiple groups of masks with different thicknesses and shells with different depths of grooves, and configure corresponding conductive sheets to form a hanger, and install the hanger in an electroplating device equipped with an anode; the method for selecting the mask thickness is as follows: select n groups of masks with continuously increasing or decreasing thicknesses, n is greater than or equal to 5; the method for selecting the depth of the shell groove is as follows: select n groups of shells with continuously increasing or decreasing groove depths, n is greater than or equal to 5.

[0019] Step S4, determining the electroplating time according to the size of the plated piece, the required coating thickness requirement, and different surface areas to be electroplated;

[0020] Step S5, according to the size of the plating area of ​​the plated piece, select the output power of the corresponding forward and reverse pulse electrolysis power supply to determine the electroplating parameter conditions of the semiconductor electronic component;

[0021] Step S6, completing the electroplating process according to the semiconductor electronic component rack;

[0022] Step S7, check the electroplated appearance of the plated part to verify whether the mask design in the rack meets the electroplating requirements;

[0023] Step S8: Repeat S3 The experimental steps of S8 verify the electroplating effect of masks with different thicknesses;

[0024] Step S9, all experimental data are counted, and mask thickness data and shell groove depth data that meet the electroplating requirements of semiconductor electronic component hangers are screened out. In the screened data, after the mask thickness data that meets the requirements are screened out, the screening is continued to screen out the mask thickness data with the best electroplating effect under the same groove depth condition; after the groove depth data that meets the requirements are screened out, the screening is continued to screen out the groove depth data with the best electroplating effect under the same mask thickness condition.

[0025] Beneficial effects of the present invention: The electroplating rack and method of the present invention are easy to operate, and the non-electroplating area of ​​the semiconductor electronic component is shielded by a mask. It has excellent sealing, strong adaptability to the local plating area, low process cost, simple equipment, and is easy to realize electroplating processing of local areas of precision semiconductor electronic component products. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of an electroplating rack provided by an embodiment of the present invention being located in an electroplating tank;

[0027] Figure 2 A plan view of an electronic component provided by an embodiment of the present invention;

[0028] Figure 3 for Figure 2 A partial enlarged view of

[0029] Figure 4 A front view of a housing provided by an embodiment of the present invention;

[0030] Figure 5 A side view of a housing provided by an embodiment of the present invention;

[0031] Figure 6 A front view of a mask provided by an embodiment of the present invention;

[0032] Figure 7 A front view of a composite structure of a shell and a mask provided by an embodiment of the present invention;

[0033] Figure 8 A front view of a composite structure of a shell and a mask provided by an embodiment of the present invention;

[0034] Fig. 9 A front view of a composite structure of a housing, a mask and an electronic component provided by an embodiment of the present invention;

[0035] Fig.10 A side view of the composite structure of the housing, mask and electronic components provided by an embodiment of the present invention;

[0036] Fig.11 A front view of the assembled hanger provided by an embodiment of the present invention;

[0037] Fig.12 A side view of the assembled hanger provided by an embodiment of the present invention;

[0038] In the figure: 20, plating tank; 30a, first anode; 30b, second anode; Ps, electroplating solution; 100, hanger; 110, cathode conductive sheet; 300a, first shell; 300b, second shell; 310, positioning pin; 320, positioning hole; 120, hollow area; 400a, first mask; 400b, second mask; 500, complex; 600, laminate. DETAILED DESCRIPTION

[0039] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions.

[0041] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] Please refer to Figures 4 to 8 The semiconductor electronic component electroplating rack of the present invention includes a first shell 300a and a second shell 300b. Both the shell 300a and the shell 300b are provided with a hollow area 120 of the same size as the electroplating area of ​​the plated part. A concave structure of the same size as the first mask 400a and the second mask 400b is provided inside the shell for fixing the mask; 4 positioning pins 310 and 4 positioning holes 320 are respectively located in the first shell 300a and the second shell 300b for precise positioning when the shell 300a and the shell 300b overlap, and the positioning pin 310 is made of SUS316. The shell 300a and the shell 300b can be made of a composite material of glass fiber and resin rolling, with a thickness of 200 300mm, the specific thickness is determined by the size of the electronic components;

[0043] The mask is a pair, namely the first mask 400a and the second mask 400b, with a hollow area 120 of the same size as the electroplating area of ​​the plated part. They correspond to the shell one by one, and the mask is fixed in the concave structure of the shell by pasting. It is used to shield the non-electroplating area of ​​the plated part. The mask is made of a flexible deformable material, which can be made of polysiloxane, and has properties similar to silicone rubber. It can be deformed within a certain range after being subjected to pressure, and its deformation can form a close fit with the masked plated part, thereby preventing the occurrence of plating caused by the infiltration of the electroplating solution.

[0044] like Figure 8 , Fig. 9 as well as Fig.10 As shown, the specific assembly method of the semiconductor electronic component electroplating rack of the present invention is as follows. First, assemble the mask and the shell, and paste the first mask 400a in the groove of the first shell 300a to form a composite body 500. The installation method of the second mask 400b is the same. The composite body 500 is precisely fitted with the semiconductor electronic component 200, and the surface a of the electronic component forms a precise composite body 600 with the first mask 400a; the conductive sheet 110 is closely overlapped and connected with the electronic component 200; the electroplating area of ​​the semiconductor electronic component is consistent with the through-hole area 120 to ensure that the electroplating solution runs smoothly through.

[0045] like Fig.10 and Fig.11 As shown, after the composite body 600 is formed, the composite body 600 and the second housing 300b are precisely inlaid and overlapped according to the positioning pins 300a and the positioning holes 300b, and the b surface of the electronic component 200 is precisely fitted with the second mask 400b. Afterwards, the housings are locked with 8 screws 150 with balanced positions, and the contact surface between the mask and the electronic component is pressed. Finally, the hanger 100 for local electroplating processing is formed.

[0046] The plating tank of the rack 100 of the present invention is as follows Figure 1 As shown, the electronic component 200 to be electroplated is as shown in FIG. Figure 2 and Figure 3 As shown, the electroplating tank includes a tank body 20b, in which a capacitor solution Ps is arranged, a first anode plate 30a and a second anode plate 30b are arranged in the tank body, and the hanger 100 is located between the two anode plates.

[0047] During the design process, the mask thickness needs to take full account of its own deformable characteristics. Here, the concept of "compressible space height" is introduced. The compressible space height refers to the difference between the mask thickness and the superposition height of the mask and the plated part in the hanger and the housing space height.

[0048] The electroplating method of the present invention is described in detail below with reference to embodiments.

[0049] Test method:

[0050] Gold plating film thickness test: Tested using FISCHERSCOPE X-RAY XDV-SDD detector manufactured by Fischer Figure 2 The thickness of the gold-plated film at the center of 15 white circles in 5 test positions of each of the plating areas Ⅰ, Ⅱ and Ⅲ of the semiconductor electronic component is measured; the a-side and b-side of the plated component 200 are tested respectively.

[0051] Appearance inspection of gold-plated semiconductor electronic components: Appearance inspection, using a 40x optical microscope and an electron microscope magnified 5000x for observation, the results are judged according to the following standards;

[0052] Excellent: The gold-plated layer should be uniform and smooth, without missing plating or seepage plating, and the plating area should remain unchanged. The total defect area = 0.0, which is evaluated as excellent.

[0053] Good: The gold-plated layer is uniform, smooth, has no missing plating, no seepage plating, and the plating area remains unchanged. The total area of ​​the absolute value of defects is less than 2% of the overall test area, which is evaluated as good.

[0054] Medium: The gold-plated layer is uniform, smooth, has no missing plating, no seepage plating, and the plating area remains unchanged. The defect area is > 2% of the overall test area, and the total area of ​​the absolute value of the defects is < 5% of the overall test area. The evaluation is medium.

[0055] Unqualified: The uniformity, smoothness, no missing plating, no seepage plating, unchanged plating area of ​​the gold plating layer, etc., the total area of ​​the absolute value of the defects > 5% of the overall test area, is evaluated as unqualified.

[0056] Corrosion resistance test of gold-plated semiconductor electronic components: According to the national standard GB2423.33-2005, sulfur dioxide gas test method. Experimental time: 24 hours.

[0057] Test samples: Examples 1 to 26 and Comparative Examples 1 to 12, a total of 38 samples were tested simultaneously in the same test equipment.

[0058] The test was conducted by sulfur dioxide gas test method, and the corrosion resistance was judged according to the following standards. The gold-plated samples of the semiconductor electronic components to be tested were simultaneously suspended in the sulfur dioxide gas test equipment. Three data were tested on the a and b sides of each example sample, totaling 6 data, and the total corrosion area of ​​the sulfur dioxide gas test was calculated. Among them, the corrosion area is expressed as a percentage relative to the total test area; the larger the percentage of the corrosion area, the worse the corrosion resistance of the gold plating; conversely, the smaller the percentage of the corrosion area, the better the corrosion resistance of the gold plating.

[0059] The corrosion resistance of the gold plating layer is judged according to the following standards; corrosion area 0.0%, evaluated as excellent; 0.0%<corrosion area ≤1.0%, evaluated as good; 1.0%<corrosion area ≤2.0%, evaluated as medium, 2.0%<corrosion area, evaluated as unqualified.

[0060] Gold-plated semiconductor electronic component product gold plating surface roughness test: implemented in accordance with the national standard GB3505-83, the surface roughness is tested using the 3D profile measuring instrument VR-6000 manufactured by Keyence.

[0061] Test of the arithmetic mean Ra of the surface roughness of the gold plating layer: Three data are tested on the a and b sides of each example sample, for a total of 6 data; the arithmetic mean Ra of the surface roughness of the gold plating layer is expressed in nm. The larger the arithmetic mean Ra of the surface roughness of the gold plating layer, the worse the surface smoothness and flatness, which means that the thickness distribution of the gold plating layer is more uneven; conversely, the smaller the arithmetic mean Ra of the surface roughness, the better the surface smoothness and flatness, and the more uniform the thickness distribution of the gold plating layer.

[0062] The plated parts to be processed are as follows: Figure 2 As shown, the size of the plated part 100 is 120×55mm, and the thickness is 0.25mm; double-sided electroplating, each terminal in the local plated area is 9.5mm long and 8.9mm wide; the dotted line is the product inspection range for judging the electroplating appearance, coating adhesion and other performances. The area of ​​the two sides of the three terminals in the local area is 9.5×8.9×6=507.3mm 2=0.05073dm 2 .

[0063] The plated parts 200 are pre-treated for degreasing, pickling and acid activation, and the whole is nickel plated 1300 After 1700nm, it is placed in the hanger 100 of the present invention, and the gold plating specification requires ≥760nm. The gold plating conditions are: current 0.3A (ampere), electroplating time 41 seconds, and solution temperature 50°C.

[0064] The plated parts 200 are pre-treated for degreasing, pickling and acid activation, and the whole is nickel plated 1300 After 1700nm, it is placed in the hanger 100 of the present invention, and the gold plating specification requires ≥300nm. The gold plating conditions are: current 0.3A (ampere), electroplating time 17 seconds, and solution temperature 50°C.

[0065] The dimensions of the first mask 400a and the second mask 400b in the hanger 100 are 125mm×60mm, with a thickness of 0.5mm; the hollow area is 9.7mm×9.1mm; the dimensions of the first shell 300a and the second 300b of the hanger are 165mm×100mm, with a thickness of 25mm; the hollow area is 9.7mm×9.1mm, and the dimensions of the area inside the shell that is bonded to the first mask 400a and the second mask 400b are 125.2mm×60.2mm, with a depth of 0.6mm; the dimensions of the conductive sheet 110 are 27.5mm×6.0mm, with a thickness of 0.08mm.

[0066] The spatial height of the first shell 300a and the second shell 300b in the hanger 100 to accommodate the first mask 400a, the second mask 400b and the plated component 200 is 0.6+0.6mm=1.2mm; and the superimposed height of the first mask 400a, the second mask 400b and the plated component 200 is 0.5mm×2+0.25mm=1.25mm. Therefore, the compressible space height = the superimposed height of the two masks and the plated component - the height of the space accommodated by the two shells = 1.25mm-1.2mm, which is 0.05mm.

[0067] Examples 1 to 13

[0068] The "compressible space height" of the hanger is fixed at 0.05 mm. The thickness of the first mask 400a and the second mask 400b starts from 0.5 mm and increases by 0.3 mm. That is, the mask thickness is in the interval of 0.5 4.2mm increments, and the corresponding accommodation space of the first housing 300a and the second housing 300b of the hanger is 0.6 The 4.3mm range increases gradually.

[0069] After the semiconductor electronic component 200 is pre-treated for degreasing, pickling and acid activation, and nickel-plating, a semi-finished product with an overall nickel coating of 1538 nm is obtained. According to the assembly method of the hanger 100, the plated component with a nickel coating of 1538 nm is placed between the first mask 400a and the second mask 400b. After the housing is screwed, a tightly sealed hanger 100 is obtained and placed in the hanger 100. Figure 1 In the rack plating equipment shown, the gold-plated semiconductor electronic component product 200 is obtained by processing according to the predetermined electroplating conditions.

[0070] The film thickness of the plated article 200 of Example 1 is measured according to the film thickness test method and the specific test position. The film thickness data of the a-side and b-side of the plated article 200 are shown in Table 1.

[0071] Table 1 Gold-plated film thickness of Example 1 (nm)

[0072]

[0073] The data shown in Table 1 are based on Figure 2 Areas Ⅰ, Ⅱ, Ⅲ and five test points in each area 1 5 is obtained by positioning test; the result of the film thickness test point of the prepared plated part must be ≥300nm. From the test results, it can be seen that the film thickness at the center position 3 of each area is relatively low, and the film thickness at the edge of the surrounding area is relatively high.

[0074] Example 1 The rack data of Example 13 are shown in Table 2. The gold plating film thickness data are shown in Table 3. The rack-plated sample 200 was subjected to an appearance inspection, and the results are shown in Table 4.

[0075] Table 2 Example 1 Example 13 Data related to the thickness of the mask of the rack

[0076]

[0077]

[0078] Table 3 Example 1 Example 13 Appearance Inspection

[0079]

[0080] Table 4 Example 1 Example 13 Gold-plated film thickness (nm)

[0081]

[0082]

[0083] Any flaws in the appearance of the tin gold layer of semiconductor electronic components or poor uniformity in film thickness will lead to a decrease in the corrosion resistance of the gold plating layer, unstable transmission signals of electronic products, and a sharp decline in the precision control function of the semiconductor electronic component mounting plating products, ultimately resulting in a major loss of electronic products being scrapped.

[0084] As can be seen from Table 3, according to the inspection and evaluation results of the appearance, no penetration and electroplating area under an electron microscope at 5000 times, Examples 1, 12 and 13 are unqualified; Examples 2, 3 and 11 are good, and Examples 4 to 10 are determined to be excellent, so the hanger configuration effect of the embodiments in this range is better; in other words, as can be seen from Table 2, the thickness of the first mask 400a and the second mask 400b is in the range of 1.4 to 3.3 mm and is in the best preferred range.

[0085] As can be seen from Table 4, although there is no significant difference in the test results of the gold plating film thickness of Examples 1 to 13, it can be seen that the gold film thickness range of the a and b sides of the best preferred range Examples 4 to 10 is Min302~Max320nm, the difference Max-Min is 18nm, and the error between the maximum value Max and the standard value of the film thickness of 300nm is (320-300) / 300=0.0666=6.66%; while the gold film thickness range of Examples 1 to 3 and Examples 11 to 13 is Min302~Max327nm, the difference Max-Min is 25nm, and the error between the maximum value Max and the standard value of the film thickness of 300nm is (327-300) / 300=0.09=9.0%; it is obvious that the gold plating film thickness distribution of the preferred range Examples 4 to 10 has more excellent uniformity.

[0086] Table 5 Example 1 Example 13 Sulfur dioxide gas experiment (%)

[0087]

[0088]

[0089] As can be seen from Table 5, the total corrosion areas of Examples 1 and 13 are >1.0%, which are evaluated as unqualified according to the judgment criteria; the total corrosion areas of Examples 2, 3 and Examples 11, 12 are 0.0%<Corrosion area≤1.0%, which are evaluated as good; the total corrosion areas of Examples 4 to 10 are all 0.0%, which are evaluated as excellent.

[0090] Table 6 Example 1 Example 13 Roughness test results (nm)

[0091]

[0092]

[0093] As can be seen from Table 6, the roughness range of 136-150nm of Examples 1 to 3 and 11 to 13 is slightly higher than the roughness range of 124-129nm of Examples 4 to 10; it is confirmed that Examples 4 to 10 have lower surface roughness, which is consistent with their excellent appearance and excellent uniform distribution of gold plating film thickness; while the roughness of Examples 1 to 3 and 11 to 13 is relatively high, that is, the uniform distribution of the gold plating film thickness on the plated surface is poor, resulting in reduced corrosion resistance in the sulfur dioxide gas test.

[0094] In summary, in Examples 4 to 10, the semiconductor electronic components are subjected to rack plating processing by bonding the polysiloxane mask to the housing with good sealing performance, and the obtained semiconductor electronic components simultaneously achieve excellent appearance, excellent uniformity of tin plating film thickness distribution and excellent resistance to sulfur dioxide gas corrosion. Therefore, the thickness of the polysiloxane mask in the rack of the present invention is preferably 1.4 to 3.3 mm. When the mask thickness is less than 1.4 mm, the uniformity of the appearance film thickness and corrosion resistance of the gold plating obtained under the same conditions are evaluated to be good and unqualified, and the surface of the gold plating has different degrees of uneven film thickness distribution and surface pinhole corrosion; when the mask thickness is higher than 3.3 mm, as the mask thickness increases, its own compressed space increases. Under the condition that the "compressible space height" of the rack remains unchanged, the mask and the semiconductor electronic component tend to have a downward trend in the degree of fit, resulting in an increase in the area of ​​gradual infiltration of the electroplating solution, the precipitated gold particles gradually tend to be rough, the density of the gold plating is poor, and the sulfur dioxide gas corrosion performance is reduced.

[0095] Embodiment 14 Embodiment 26:

[0096] Embodiment 14 26 hanger mask thickness selection embodiment 4 The preferred range of Example 10 is 2.3mm; the "compressible space height" increases from 0.0mm with an amplitude of 0.15mm, and the accommodating space of the first shell 300a and the second shell 300b increases from 2.425mm with an increment of 0.3mm. The plated part 200 and other conditions are the same as those of Example 1.

[0097] Embodiment 14 The hanger data of Example 26 is shown in Table 7; the appearance inspection is shown in Table 8.

[0098] Embodiment 14 The gold-plated film thickness data of Example 26 is shown in Table 9.

[0099] Table 7 Example 14 Example 26 Data related to the height of the hanger's compressible space

[0100]

[0101]

[0102] Table 8 Example 14 Example 26 Appearance Inspection

[0103]

[0104] Table 9 Example 14 Example 26 Gold-plated film thickness (nm)

[0105]

[0106]

[0107] As can be seen from Table 8, based on the inspection and evaluation results of the appearance, no plating, and electroplating areas under an electron microscope at 5000 times magnification, it is determined that the hangers of Examples 17 to 23 have better effects; in other words, as can be seen from Table 7, the "compressible space height" of the hanger is in the range of 0.45 to 1.35 mm and is in the best preferred range.

[0108] As can be seen from Table 9, although there is no significant difference in the test results of the gold plating film thickness of Examples 14 to 26, it can be seen that the gold film thickness range of the best preferred range Examples 17 to 23 on both sides a and b is Min302~Max319nm, the difference Max-Min is 17nm, and the error between the maximum value Max and the standard value 300nm is (319-300) / 300=0.0633=6.33%; while the gold film thickness range of Examples 14 to 16 and Examples 24 to 26 is Min302~Max328nm, the difference Max-Min is 26nm, and the error between the maximum value Max and the standard value 300nm is (328-300) / 300=0.0933=9.33%; it is obvious that the gold plating film thickness distribution of the preferred range Examples 17 to 23 has more excellent uniformity.

[0109] Table 10 Example 14 Example 26 Sulfur dioxide gas experiment (%)

[0110]

[0111]

[0112] As can be seen from Table 10, the total corrosion area of ​​Example 14 and Example 26 is >1.0%, which is evaluated as unqualified according to the judgment standard; the total corrosion area of ​​Examples 15, 16 and Examples 24, 25 is 0.0%<Corrosion area≤1.0%, which is evaluated as good; the total corrosion area of ​​Examples 17 to 23 is 0.0% and is evaluated as excellent.

[0113] Table 11 Example 14 Example 26 Roughness test results (nm)

[0114]

[0115]

[0116] As can be seen from Table 11, the roughness range of 135-150 nm of Examples 14 to 16 and Examples 24 to 26 is slightly higher than the roughness range of 125-128 nm of Examples 17 to 23; it is confirmed that Examples 17 to 23 have lower surface roughness, which is consistent with their excellent appearance and excellent uniform distribution of gold-plated film thickness; while the relatively high roughness of Examples 14 to 16 and Examples 24 to 26, that is, the uniform distribution of the gold-plated film thickness on the plated surface is poor, resulting in reduced corrosion resistance in the sulfur dioxide gas test.

[0117] In summary, in Examples 17 to 23, the excellent sealing performance of the hanger is formed by the "compressible space height", and the semiconductor electronic component 200 is subjected to hang plating processing, and the obtained semiconductor electronic component simultaneously achieves excellent appearance, excellent uniformity of gold plating film thickness distribution and excellent sulfur dioxide gas corrosion resistance. Therefore, the preferred range of the "compressible space height" of the hanger of the present invention is 0.45 to 1.35 mm. When the "compressible space height" is lower than 0.45mm, the uniformity of the appearance film thickness and the corrosion resistance of the gold plating obtained under the same conditions are evaluated to be good and unqualified, and the surface of the gold plating has different degrees of uneven film thickness distribution and surface pinhole corrosion; when the "compressible space height" is higher than 1.35mm, as its height increases, its own compressed space increases. Under the condition that the thickness of the hanger mask remains unchanged, the mask is compressed and deformed and expanded, resulting in a decrease in the local plating area of ​​the semiconductor electronic component, and a decrease in the close fit between the edge of the mask and the semiconductor electronic component. The infiltration of the electroplating solution makes the precipitated gold particles gradually rough, the density of the gold plating is poor, and the corrosion resistance of sulfur dioxide gas is reduced.

[0118] In summary, the semiconductor electronic component hanger and the electroplating method thereof of the present invention, through the application of the preferred mask thickness range of 1.4 to 3.3 mm and the preferred "compressible space height" range of 0.45 to 1.35 mm, can provide excellent shielding effect on the plated parts, strong adaptability to the local plating area, low process cost, simple equipment, and easy to realize electroplating processing of precision semiconductor electronic component products.

[0119] Comparative Example 1 In comparative example 12, the semiconductor electronic component 200 was masked with a special electroplating tape for masking the non-electroplating area, and then treated with the existing rack plating technology. The other electroplating conditions were the same as those in Example 1, and a gold-plated semiconductor electronic component product 200 was obtained. The special electroplating tape was 3M China Company's 3M TM Circuit plating tape 851 product; circuit board plating protective film from Dongguan Yizhou Adhesive Products Co., Ltd. and plating masking tape from Suzhou Tukun Electronic Technology Co., Ltd.

[0120] Comparative Example 1 Comparative Example 4 uses 3M tape;

[0121] Comparative Example 5 Comparative Example 8 uses Dongguan tape;

[0122] Comparative Example 9 Comparative Example 12 uses Suzhou tape;

[0123] Comparative Example 1 The appearance inspection results of the gold-plated semiconductor electronic component product 200 of Comparative Example 12 are shown in Table 11.

[0124] Table 12 Comparative Example 1 Comparative Example 12 Appearance Inspection

[0125]

[0126] Note: a appearance = a area % + a penetration %; similarly, b appearance = b area % + b penetration %;

[0127] (a+b) appearance = a appearance + b appearance

[0128] From Table 12, it can be seen that Comparative Example 1 The appearance inspection of the gold-plated sample of the semiconductor electronic component 20 masked with 3M tape in comparative example 4 shows that the appearance missing rate is in the range of 1.1 1.8%, in the judgment range of 0.0%<appearance loss rate<2.0%, evaluated as good; Comparative Example 5 The appearance inspection of the gold-plated sample of Dongguan tape masking semiconductor electronic component 20 of comparative example 8 and if the appearance missing rate range is 3.2 4.1%, which is in the range of 2.0%<appearance loss rate<5.0%, and is evaluated as medium; Comparative Example 9 The appearance inspection of the gold-plated sample of Suzhou tape masking semiconductor electronic component 20 of comparative example 12 and if the appearance missing rate range is 4.0 The value of 4.4% is in the range of 2.0%<appearance loss rate<5.0%, and is evaluated as medium.

[0129] In other words, the 3M tape masking method cannot completely and accurately cover the non-plating area of ​​semiconductor electronic components. Under electroplating conditions, the electroplating solution easily penetrates from the edge of the tape, causing plating, and the appearance inspection results can only reach good and medium levels.

[0130] Table 13 Comparative Example 1 Comparative Example 12 Gold-plated film thickness (nm)

[0131]

[0132] Any flaws in the appearance of the tin gold layer of semiconductor electronic components or poor uniformity in film thickness will lead to a decrease in the corrosion resistance of the gold plating layer, unstable transmission signals of electronic products, and a sharp decline in the precision control function of the semiconductor electronic component mounting plating products, ultimately resulting in a major loss of electronic products being scrapped.

[0133] As can be seen from Table 13, the test results of the gold plating film thickness of Comparative Examples 1 to 4 of the 3M tape are in the range of Min302 to Max330nm, the difference Max-Min is 28nm, and the error between the maximum value Max and the standard value of the film thickness of 300nm is (330-300) / 300=0.10=10.0%; compared with the error range of 6.33-6.66% in the preferred embodiment of the present invention, the uniformity of the gold plating film thickness distribution is at a deficient level; in other words, the electroplating method of the semiconductor electronic component hanger of the present invention is compared with the tape masking electroplating method, and the uniformity of the gold plating film thickness distribution has been significantly improved.

[0134] Furthermore, the gold plating film thickness test results of Comparative Examples 5 to 8 of the tape of Dongguan Yizhou Adhesive Products Co., Ltd. range from Min302 to Max335nm, and the difference Max-Min is 33nm. The error between the maximum value Max and the standard value of the film thickness of 300nm is (335-300) / 300=0.1166=11.66%; compared with the error of 6.33~6.66% in the preferred embodiment of the present invention, the uniformity of the gold plating film thickness distribution is at a deficient level; in other words, the electroplating method of the semiconductor electronic component hanger of the present invention is compared with the tape masking electroplating method, and the uniformity of the gold plating film thickness distribution is also significantly improved.

[0135] Furthermore, the gold plating film thickness test results of Comparative Examples 9 to 12 of the tape of Dongguan Yizhou Adhesive Products Co., Ltd. range from Min302 to Max341nm, and the difference Max-Min is 39nm. The error between the maximum value Max and the standard value of the film thickness of 300nm is (341-300) / 300=0.1366=13.66%; compared with the error range of 6.33~6.66% in the preferred embodiment of the present invention, the uniformity of the gold plating film thickness distribution is at a deficient level; in other words, compared with the tape masking electroplating method, the electroplating method of the semiconductor electronic component hanger of the present invention has a further significant improvement in the uniformity of the gold plating film thickness distribution.

[0136] Table 14 Comparative Example 1 Comparative Example 12 Sulfur dioxide gas experiment (%)

[0137]

[0138] As can be seen from Table 14, the comparative example 1 of 3M tape The corrosion area of ​​comparative example 4 is 1.24 1.58%, which is in the area of ​​1.0%<corrosion area ≤2.0%, and is evaluated as medium according to the judgment standard; the corrosion area of ​​Dongguan tape in comparison columns 5, 6 and 8 is 1.52 The corrosion area of ​​comparative example 7 is 2.46%, which exceeds 2.0% and is judged as unqualified. The corrosion areas of comparative examples 9 and 12 of Suzhou Tukun Electronic Technology Co., Ltd.'s tape are 1.84% and 1.68%, which are judged as medium. The corrosion areas of comparative examples 10 and 11 are 3.13% and 2.13%, which are judged as unqualified.

[0139] Table 15 Comparative Example 1 Comparative Example 12 Roughness Test Results (nm)

[0140]

[0141]

[0142] As can be seen from Table 15, the comparative example 1 of 3M tape The gold-plated surface roughness of Comparative Example 4 ranges from 135 to 154 nm; Comparative Example 5 of Dongguan tape The gold-plated surface roughness of Comparative Example 8 is in the range of 145 to 162 nm; Comparative Example 9 of Suzhou tape The gold-plated surface roughness of Comparative Example 12 ranges from 150 to 171 nm.

[0143] Comparative Example 1 The gold-plated surface roughness ranges of various tape electroplating methods in comparative example 12 are compared with the preferred gold-plated surface roughness ranges of 124 to 129 nm and 125 to 128 nm of the mask hanger electroplating method of the present invention. The maximum gold-plated surface roughness of 129 nm of the present invention is deducted from the maximum value of 171 nm of the tape of Suzhou Tukun Electronic Technology Co., Ltd., and then divided by the maximum value of 171 nm of the tape of Suzhou Tukun Electronic Technology Co., Ltd., and the calculation formula is: (129-171)÷171=-0.2456=-24.56%; that is, the mask hanger electroplating method of the present invention can reduce the gold-plated surface roughness of the tape of Suzhou Tukun Electronic Technology Co., Ltd. by 24.56%; in other words, the gold-plated surface is flat and smooth, and the uniformity of film thickness distribution is improved.

[0144] Furthermore, using the same calculation method, the technology of the present invention can reduce 20.37% compared with the tape of Dongguan Yizhou Adhesive Products Co., Ltd.; compared with 3M tape, it can reduce 16.23%.

[0145] In summary, the electroplating method of the mask rack of the present invention has obvious advantages over the electroplating method of the existing film tape. It can not only solve the problem of poor performance of plated parts caused by seepage and plating due to scratches and roughness on the surface of semiconductor electronic components and loose bonding in the existing tape method, but also solve the electroplating process that cannot be completed by the tape method for complex product structures, thereby providing an electroplating method for semiconductor electronic component mask racks to achieve precise manufacturing of precision semiconductor electronic component products.

[0146] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A semiconductor electronic component electroplating rack, characterized in that: include: A housing assembly comprising a first housing (300a) and a second housing (300b); A mask assembly, comprising a first mask (400a) and a second mask (400b); The first shell (300a) is provided with a groove for accommodating the first mask (400a) and the workpiece to be plated, and the second shell (300b) is provided with a groove for accommodating the second mask (400b) and the workpiece to be plated, the first shell (300a) corresponds to the first mask (400a), and the second shell (300b) corresponds to the second mask (400b), the first mask (400a) and the second mask (400b) are made of flexible deformable material, and are used to shield the non-electroplating area of ​​the workpiece to be plated, and the corresponding positions of the shell and the mask are provided with hollow areas (120), and the shape of the hollow areas (120) corresponds to the area to be electroplated of the workpiece to be plated; A locking mechanism, used for fixing the first shell (300a) and the second shell (300b), and simultaneously pressing the first mask (400a) and the second mask (400b) located in the first shell (300a) and the second shell (300b) onto the surface of the piece to be plated to form a seal; The superposition thickness of the two masks and the workpiece to be plated is greater than the thickness of the accommodation space formed by the grooves of the two shells; The difference between the thickness of the two masks and the plated object superimposed on each other and the thickness of the accommodation space formed by the two housing grooves is 0.45 to 1.35 mm; The thickness of the first mask (400a) and the second mask (400b) ranges from 1.4 to 3.3 mm.

2. The semiconductor electronic component electroplating rack according to claim 1, characterized in that: Also included is a positioning mechanism for achieving overlapping of the two shells.

3. The semiconductor electronic component electroplating rack according to claim 2, characterized in that: The positioning mechanism comprises a positioning hole (320) and a matching positioning pin (310), wherein the positioning hole is located on one of the housings, and the positioning pin is located on the other housing.

4. The semiconductor electronic component electroplating rack according to claim 1, characterized in that: Both masks are made of polysiloxane.

5. A method for electroplating a semiconductor electronic component mold, characterized in that: The electroplating rack according to any one of claims 1 to 4 is used, comprising the following steps: Step S1, performing alkali degreasing and acid activation treatment on the plated parts; Step S2, performing a bottom nickel plating process on the plated part; Step S3, selecting multiple sets of masks with different thicknesses and housings with grooves of different depths according to the electroplating area and the form of the plated parts, configuring corresponding conductive sheets to form a hanger, and installing the hanger in an electroplating device equipped with an anode; Step S4, determining the electroplating time according to the size of the plated piece, the required coating thickness requirement, and different surface areas to be electroplated; Step S5, according to the size of the plating area of ​​the plated piece, select the output power of the corresponding forward and reverse pulse electrolysis power supply to determine the electroplating parameter conditions of the semiconductor electronic component; Step S6, completing the electroplating process according to the semiconductor electronic component rack; Step S7, check the electroplated appearance of the plated part to verify whether the mask design in the rack meets the electroplating requirements; Step S8, repeating the experimental steps of S3 to S8 to verify the electroplating effect of masks with different thicknesses; Step S9, counting all experimental data, and selecting mask thickness data and housing groove depth data that meet the electroplating requirements of the semiconductor electronic component hanger.

6. The electroplating method for semiconductor electronic component mold according to claim 5, characterized in that: In step S3, the method for selecting the mask thickness is as follows: selecting n groups of masks with continuously increasing or decreasing thicknesses, where n is greater than or equal to 5; The depth selection method of the shell groove is as follows: select n groups of shells with groove depths that continuously increase or decrease, where n is greater than or equal to 5.

7. The electroplating method for semiconductor electronic component mold according to claim 5 or 6, characterized in that: In step S9, in the screening data, after screening out the mask thickness data that meets the requirements, continue screening to screen out the mask thickness data with the best electroplating effect under the same groove depth conditions; after screening out the groove depth data that meets the requirements, continue screening to screen out the groove depth data with the best electroplating effect under the same mask thickness conditions.

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