Chip static current test circuit, chip and electronic device

Abstract

This invention relates to the field of IC design and testing, and provides a static current testing circuit, a chip, and an electronic device. The circuit includes an amplifier circuit, an output circuit, a voltage divider resistor path, a load circuit, and an external input power supply. A first bypass switch is provided between the first output terminal of the amplifier circuit and the third input terminal of the output circuit. The first bypass switch is used to control the power supply of the internal power supply of the chip under test to the output circuit. A second bypass switch and a third bypass switch are provided between the output circuit and the voltage divider resistor path. The second bypass switch is used to control the conduction or cutoff of the voltage divider resistor path, and the third bypass switch is used to ground the source of the second bypass switch. A fourth bypass switch is provided between the input terminal of the external input power supply and the input terminal of the load circuit. The fourth bypass switch is used to control the conduction or cutoff of the external input power supply and the load circuit.

Description

Technical Field

[0001] The present invention relates to the field of IC design and testing, and in particular to a static current testing circuit of a chip, a chip and an electronic device. Background Art

[0002] During the manufacture and testing of integrated circuits, IDDQ (Integrated Circuit Quiescent Current Test) is usually used to detect circuit faults within the chip to prevent errors or faults in the circuit. Under normal circumstances, the static leakage current of the chip's internal circuit is very small, but when there is a fault within the circuit, the static leakage current will increase significantly, so by measuring the static leakage current, potential problems in the circuit can be detected.

[0003] Generally, the IDDQ test requires an external power supply voltage to the IC chip to be tested, and by measuring the current value on the corresponding pin and comparing it with the expected current value, it can be determined whether there is a fault in the circuit. However, this IDDQ test method is only applicable when the power supply is external. If the chip uses an internal power supply, that is, the power supply of the digital circuit comes from the current generated by the internal PMU, this chip has no external pins and cannot be powered directly from the outside of the chip, which limits the existing IDDQ test method. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to propose a static current test circuit for a chip. Through the static current test circuit for a chip provided by the embodiment of the present invention, when the chip adopts an internal Capless LDO power supply mode, an external port is used to input a small current during the Capture period to perform an IDDQ test, thereby measuring the static current of the chip, solving the problem of being unable to measure the internal Capless LDO current size. At the same time, the external port can be reused with the ordinary GPIO of the chip, without the need for an additional power PAD, thereby saving pins; in addition, the power supply of the SHIFT mode and the CAPTURE mode is switched using an internal digital signal, which does not affect the normal power supply mode of the circuit to be tested during the SHIFT period, and the static current is tested in a timely manner while ensuring the normal operation of the chip.

[0005] The second objective of the present invention is to provide a chip.

[0006] A third objective of the present invention is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a static current test circuit for a chip, comprising an amplifier circuit, an output circuit, a voltage-divider resistor path, a load circuit and an external input power supply; a first bypass switch is arranged between the first output end of the amplifier circuit and the third input end of the output circuit, and the first bypass switch is used to manage the input control of the internal power supply of the chip to be tested to the output circuit; a second bypass switch and a third bypass switch are arranged between the output circuit and the voltage-divider resistor path, the second bypass switch is used to control the conduction or cutoff of the voltage-divider resistor path, and the third bypass switch is used to ground the source of the second bypass switch; a fourth bypass switch is arranged between the input end of the external input power supply and the input end of the load circuit, and the fourth bypass switch is used to control the conduction power supply or cutoff power supply of the external input power supply and the load circuit.

[0008] In addition, the static current test circuit of the chip according to the above embodiment of the present invention may also have the following additional technical features:

[0009] According to some embodiments of the present invention, the first input terminal of the amplifier circuit is used to receive a reference voltage, the second input terminal of the amplifier circuit is used to receive a feedback voltage of a voltage divider resistor path, the first output terminal of the amplifier circuit is connected to the third input terminal of the output circuit, the fourth input terminal of the output circuit is used to receive an internal input voltage of an internal power supply of a chip to be tested, the second output terminal of the output circuit is connected to the input terminal of a load circuit, and the output terminal of an external input power supply is connected to the input terminal of the load circuit.

[0010] According to some embodiments of the present invention, the voltage-dividing resistor path includes a first load resistor and a second load resistor, and the feedback voltage is a voltage between the first load resistor and the second load resistor.

[0011] According to some embodiments of the present invention, the first bypass switch is a first NMOS tube, the drain of the first NMOS tube is connected to the first output end of the amplifier circuit, and the source of the first NMOS tube is grounded; the second bypass switch is a second NMOS tube, the drain of the second NMOS tube is connected to the second output end of the output circuit, and the source of the second NMOS tube is connected to the input end of the voltage divider resistor path; the third bypass switch is a third NMOS tube, the drain of the third NMOS tube is connected to the source of the second NMOS tube, and the source of the third NMOS tube is grounded; the fourth bypass switch is a fourth NMOS tube, the drain of the fourth NMOS tube is connected to the external input power supply through the ATB bus, and the source of the fourth NMOS tube is connected to the load circuit.

[0012] According to some embodiments of the present invention, in the SHIFT stage of the IDDQ test mode, when the gate of the first NMOS tube receives a low-level control signal, the gate of the second NMOS tube receives a high-level control signal, the gate of the third NMOS tube receives a low-level control signal, and the gate of the fourth NMOS tube receives a low-level control signal, the first bypass switch is turned off, the second bypass switch is turned on, the third bypass switch is turned off, and the fourth bypass switch is turned off, and the static current test circuit of the chip supplies power to the load circuit through the internal power supply.

[0013] According to some embodiments of the present invention, in the CAPTURE stage of the IDDQ test mode, when the gate of the first NMOS tube receives a high-level control signal, the gate of the second NMOS tube receives a low-level control signal, the gate of the third NMOS tube receives a high-level control signal, and the gate of the fourth NMOS tube receives a high-level control signal, the first bypass switch is turned on, the second bypass switch is turned off, the third bypass switch is turned on, and the fourth bypass switch is turned on, and the static current test circuit of the chip supplies power to the load circuit through an external input power supply.

[0014] According to some embodiments of the present invention, when the static current test circuit of the chip supplies power to the load circuit through an external input power supply, the load circuit generates a leakage current in a static state; wherein the leakage current is used to determine whether there is an abnormality in the chip under test.

[0015] According to some embodiments of the present invention, when the leakage current is greater than a preset current threshold, it is determined that the chip under test is abnormal.

[0016] In order to achieve the above-mentioned purpose, a chip is proposed in an embodiment of the second aspect of the present invention. The chip applies the static current test circuit provided in the embodiment of the present invention and has the same beneficial effects.

[0017] To achieve the above objectives, a third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the electronic device uses the above chip.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a static current test circuit for a chip provided in an embodiment of the present invention.

[0021] Figure 2 A schematic diagram of a normal working mode circuit of a chip provided by an embodiment of the present invention.

[0022] Figure 3 A schematic diagram of a chip IDDQ test mode circuit provided by an embodiment of the present invention.

[0023] Figure 4 This is a structural block diagram of a chip provided in an embodiment of the present invention.

[0024] Description of reference numerals:

[0025] 100-static current test circuit of the chip, 1-amplifier circuit, 2-output circuit, 3-voltage divider resistor path, 4-load circuit, 5-external input power supply, 13-first output terminal, 21-third input terminal, S1-first bypass switch, S2-second bypass switch, S3-third bypass switch, S4-fourth bypass switch, 11-first input terminal, 12-second input terminal, 22-fourth input terminal, 23-second output terminal, 51-input terminal of external input power supply, 52-output terminal of external input power supply, 41-input terminal of load circuit, R1-first load resistor, R2-second load resistor, 400-chip. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0027] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] As described in the background technology section, the SCAN test of integrated circuits is an important test technology used to improve the testability of circuits. Scan test technology mainly involves integrating a set of shift registers (scan chain) into the circuit, which allows test engineers to input test data into the circuit through shift operations and shift response data out of the circuit, thereby achieving a comprehensive test of the circuit function. Scan test technology is particularly suitable for testing combinational logic and sequential logic because it provides direct control of the internal state of the circuit and direct observation of the output response.

[0029] Scan test technology is not only used to test the core part of the circuit, but also includes boundary scan test for testing peripheral circuits and IO pads. This technology improves the testability of the circuit, making it possible to perform effective testing and verification even without direct access to the internal nodes of the circuit. The application of Scan test technology has greatly improved the efficiency and accuracy of integrated circuit testing and is an indispensable part of modern integrated circuit design and testing.

[0030] When performing SCAN mass production testing of integrated circuits, the commonly used basic SCAN DC (Stuck-at scan test, slow test mode) and SCAN AC (at-speed scan test, high-speed test mode) test methods only detect common faults such as electrical characteristics, basic logic faults, and delay faults. Some faults caused by the manufacturing process that cannot be discovered by functional tests, such as gate oxide short circuits, bridge faults, open circuit faults, etc., need to be detected by IDDQ testing. Under normal circumstances, the IDDQ test relies on adding a power supply voltage to the VDD of the chip to be tested. By comparing the measured current value on the VDD pin with the expected current value, it can be determined whether there is a fault in the circuit. However, this method is only applicable when the chip is externally powered.

[0031] In the process of implementing the present invention, the applicant discovered that if the chip under test uses an internal power supply mode of Capless LDO (low-dropout linear regulator without external large capacitor), that is, the power supply of the digital part circuit comes from the power provided by the internal PMU (Power Management Unit), this chip under test is designed to save costs without connecting a large capacitor outside the chip, the circuit is simplified, and has a higher degree of integration. Therefore, this chip under test does not have external pins and cannot be directly powered from the outside of the chip. Therefore, it is impossible to directly use the IDDQ test to detect the current inside the chip.

[0032] The technical solution of the present invention is further described in detail below through specific embodiments.

[0033] refer to Figure 1 , is a schematic diagram of a static current test circuit of a chip provided in an embodiment of the present invention.

[0034] In an embodiment of the present invention, a static current test circuit 100 of a chip includes an amplifier circuit 1, an output circuit 2, a voltage-dividing resistor path 3, a load circuit 4 and an external input power supply 5; a first bypass switch S1 is arranged between a first output terminal 13 of the amplifier circuit 1 and a third input terminal 21 of the output circuit 2, and the first bypass switch S1 is used to control the internal power supply of the chip under test to supply power to the load circuit 4 through the output circuit 2; a second bypass switch S2 and a third bypass switch S3 are arranged between the output circuit 2 and the voltage-dividing resistor path 3, the second bypass switch S2 is used to control the conduction or cutoff of the voltage-dividing resistor path 3, and the third bypass switch S3 is used to ground the source of the second bypass switch S2; a fourth bypass switch S4 is arranged between an input terminal 51 of the external input power supply and an input terminal 41 of the load circuit, and the fourth bypass switch S4 is used to control the conduction or cutoff of the external input power supply 5 and the load circuit 4.

[0035] Specifically, the first output terminal 13 of the amplifier circuit 1 of the embodiment of the present invention is connected to the third input terminal 21 of the output circuit 2, the second output terminal 23 of the output circuit 2 is connected to the second bypass switch S2, the source of the second bypass switch S2 is connected to the voltage-dividing resistor path 3, the source of the second bypass switch S2 is also connected to the drain of the third bypass switch S3, the source of the third bypass switch S3 is grounded, the source of the fourth bypass switch S4 serves as the output terminal 52 of the external input power supply, and the output terminal 52 of the external input power supply is connected to the input terminal 41 of the load circuit.

[0036] The chip using the Capless LDO architecture has a negative feedback circuit inside, which can adjust the input voltage through the internal error amplifier and other circuit elements. In the negative feedback circuit, the two input terminals (non-inverting input terminal and inverting input terminal) of the op amp will maintain basically equal voltages (i.e., "virtual short") in a stable state, that is, Vfb (Voltage Feedback) and Vref (Voltage Reference) are approximately equal, so the output voltage of the digital circuit to be tested satisfies the formula:

[0037]

[0038] in, is the output voltage of the circuit, R1 and R2 are voltage-dividing resistors, and Vfb is the voltage feedback value.

[0039] As an optional embodiment, the first input terminal 11 of the amplifier circuit 1 is used to receive a reference voltage, the second input terminal 12 of the amplifier circuit 1 is used to receive a feedback voltage of the voltage divider resistor path 3, the first output terminal 13 of the amplifier circuit 1 is connected to the third input terminal 21 of the output circuit 2, the fourth input terminal 22 of the output circuit 2 is used to receive the internal input voltage of the internal power supply of the chip to be tested, the second output terminal 23 of the output circuit 2 is connected to the input terminal 41 of the load circuit, and the output terminal 52 of the external input power supply is connected to the input terminal 41 of the load circuit.

[0040] Specifically, in the amplifier circuit 1, the Vref of the amplifier is the first input terminal 11 of the amplifier circuit 1, which is independent of factors such as load, power, time, etc. in the circuit, and its voltage is always kept constant, serving as a comparison reference of the circuit, and is used for comparison with the Vfb voltage; the Vfb of the amplifier is the second input terminal 12 of the amplifier circuit 1, which is used to receive the feedback voltage of the voltage-dividing resistor path 3, and the output voltage of the circuit can be stabilized at a preset value by comparing the voltage value of Vfb with the voltage value of Vref; the first output terminal 13 of the amplifier circuit 1 is connected to the third input terminal 21 of the output circuit 2, wherein the third input terminal 21 of the output circuit 2 is preferably a gate of an NMOS tube, and the working voltage of the NMOS tube is 5V; the fourth input terminal 22 of the output circuit 2 is used to receive the internal input voltage of the internal power supply of the chip to be tested, and is connected to the drain of the NMOS tube with the working voltage of 5V; the source of the NMOS tube with the working voltage of 5V is used as the second output terminal 23 of the output circuit 2, and is connected to the input terminal 41 of the load circuit, and the output terminal 52 of the external input power supply is connected to the input terminal 41 of the load circuit.

[0041] As an optional embodiment, the voltage-dividing resistor path 3 includes a first load resistor R1 and a second load resistor R2 , and the feedback voltage is a voltage between the first load resistor R1 and the second load resistor R2 .

[0042] Specifically, the second input terminal 12 is connected between the first load resistor R1 and the second load resistor R2 of the voltage-dividing resistor path 3, that is, the feedback voltage is the voltage between the first load resistor R1 and the second load resistor R2. In the negative feedback circuit, when the output voltage drives the feedback voltage to fluctuate, the amplifier circuit 1 controls and regulates the current flowing into the resistor by controlling the output circuit 2, so that the current change direction is opposite to the feedback voltage fluctuation direction, thereby maintaining the relative stability of the feedback voltage and finally achieving the stability of the output voltage.

[0043] As an optional embodiment, the first bypass switch S1 is a first NMOS tube, the drain of the first NMOS tube is connected to the first output terminal 13 of the amplifier circuit 1, and the source of the first NMOS tube is grounded; the second bypass switch S2 is a second NMOS tube, the drain of the second NMOS tube is connected to the second output terminal 23 of the output circuit 2, and the source of the second NMOS tube is connected to the input end of the voltage divider resistor path 3; the third bypass switch S3 is a third NMOS tube, the drain of the third NMOS tube is connected to the source of the second NMOS tube, and the source of the third NMOS tube is grounded; the fourth bypass switch S4 is a fourth NMOS tube, the drain of the fourth NMOS tube is connected to the external input power supply 5 through the ATB bus, and the source of the fourth NMOS tube is connected to the load circuit 4.

[0044] Specifically, the first bypass switch S1 is a first NMOS tube, the drain of the first NMOS tube is connected to the first output terminal 13 of the amplifier circuit 1, the source of the first NMOS tube is grounded, and the gate of the first NMOS tube is used to receive the first external signal; the second bypass switch S2 is a second NMOS tube, the drain of the second NMOS tube is connected to the second output terminal 23 of the output circuit 2, the source of the second NMOS tube is connected to the input end of the voltage-dividing resistor path 3, and the gate of the second NMOS tube is used to receive the second external signal; the third bypass switch S3 is a third NMOS tube, the drain of the third NMOS tube is connected to the source of the second NMOS tube, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is used to receive the first external signal; the fourth bypass switch S4 is a fourth NMOS tube, the drain of the fourth NMOS tube is connected to the external input power supply 5 through the ATB bus, the source of the fourth NMOS tube is connected to the load circuit 4, and the gate of the fourth NMOS tube is used to receive the first external signal.

[0045] refer to Figure 2 , is a schematic diagram of a normal working mode circuit of a chip provided in an embodiment of the present invention.

[0046] As an optional embodiment, in the SHIFT stage of the IDDQ test mode, when the gate of the first NMOS tube receives a low-level control signal, the gate of the second NMOS tube receives a high-level control signal, the gate of the third NMOS tube receives a low-level control signal, and the gate of the fourth NMOS tube receives a low-level control signal, the first bypass switch S1 is turned off, the second bypass switch S2 is turned on, the third bypass switch S3 is turned off, and the fourth bypass switch S4 is turned off, and the static current test circuit of the chip supplies power to the load circuit 4 through the internal power supply.

[0047] Specifically, the SHIFT phase of the IDDQ test mode usually refers to the loading phase of the test vector, at which the test vector is sequentially loaded into the Scan Chain of the circuit under test, and the Scan Chains are all flipping. At this time, the current required for the test is relatively large, and a normal PMU LDO power supply method needs to be adopted. At this time, the first external signal input to the gate of the first NMOS tube is a low level, the second external signal input to the gate of the second NMOS tube is a high level, the first external signal input to the gate of the third NMOS tube is a low level, and the first external signal input to the gate of the fourth NMOS tube is a low level. Correspondingly, according to the characteristics of the NMOS tube, the first bypass switch S1 is turned off, the second bypass switch S2 is turned on, the third bypass switch S3 is turned off, and the fourth bypass switch S4 is turned off. At this time, the current in the circuit is input from VDD to the output circuit 2, and flows to the input terminal 41 of the load circuit through the first output terminal 13 of the output circuit 2. The load circuit 4 monitors the current of the digital circuit to be tested in the SHIFT stage. According to the "virtual short" feature of the operational amplifier, the voltages of the first input terminal 11 and the second input terminal 12 of the amplifier circuit 1 are equal, so the current does not flow through the amplifier circuit 1. In addition, the current also flows to the voltage divider resistor path 3 through the first output terminal 13 of the output circuit 2 and the second bypass switch S2. At this time, the second bypass switch S2 is turned on, and the current flows normally through the voltage divider resistor path 3.

[0048] It should be noted that SCAN Chain is a commonly used digital integrated circuit testing technology. SCAN Chain simplifies the testing of digital logic circuits by connecting all internal triggers into a long string (or several long strings) to form one or more "chains" that can be accessed through external ports.

[0049] It should be noted that the flip of the SCAN Chain mainly refers to the change of the state of the flip-flops on the scan chain during the test and the injection and reading of test data. The flip of the SCAN Chain connects the flip-flops into a chain and injects test data to achieve comprehensive testing of the circuit, which is of great significance to improving test coverage, simplifying test complexity and improving test efficiency.

[0050] refer to Figure 3 , is a schematic diagram of a chip IDDQ test mode circuit provided in an embodiment of the present invention.

[0051] As an optional embodiment, in the CAPTURE stage of the IDDQ test mode, when the gate of the first NMOS tube receives a high-level control signal, the gate of the second NMOS tube receives a low-level control signal, the gate of the third NMOS tube receives a high-level control signal, and the gate of the fourth NMOS tube receives a high-level control signal, the first bypass switch S1 is turned on, the second bypass switch S2 is turned off, the third bypass switch S3 is turned on, the fourth bypass switch S4 is turned on, the LDO power supply loop inside the chip is cut off, and the external power supply path is opened. The static current test of the chip supplies power to the digital circuit to be tested through the external input power supply 5.

[0052] Specifically, in the CAPTURE stage of the IDDQ test mode, the circuit is in a cycle of no clock operation, the power supply port of the digital circuit to be tested is switched to the external port, and the static current of the digital circuit to be tested is measured. In the CAPTURE stage, the first external signal input to the gate of the first NMOS tube is a high level, the second external signal input to the gate of the second NMOS tube is a low level, the first external signal input to the gate of the third NMOS tube is a high level, and the first external signal input to the gate of the fourth NMOS tube is a high level. Correspondingly, according to the characteristics of the NMOS tube, the first bypass switch S1 is turned on, the second bypass switch S2 is turned off, the third bypass switch S3 is turned on, and the fourth bypass switch S4 is turned on. When the first bypass switch S1 is turned on, the voltage between the first output terminal 13 and the third input terminal 21 is 0, that is, the power supply loop inside the chip to be tested is closed. At this time, the current in the circuit flows from the external input power supply 5 through the ATB (Analog Test Bus) input, flows through the fourth bypass switch S4, and flows to the load circuit 4. The load circuit 4, that is, the digital circuit in the CAPTURE stage, generates a static current load to monitor the static current generated by the digital circuit to be tested; in addition, the voltage divider resistor path 3 is closed by turning off the second bypass switch S2 to prevent the voltage divider resistor from discharging to the ground and affecting the test result, and the fourth bypass switch S4 is turned on to ground the second bypass switch S2 to prevent the circuit node from being suspended and affecting the stability of the circuit.

[0053] As an optional embodiment, when the static current test circuit of the chip supplies power to the output circuit 2 through the external input power supply 5, the load circuit 4 outputs the leakage current of the chip under test in the static state; wherein the leakage current is used to determine whether there is an abnormality in the chip under test.

[0054] Specifically, the static current test circuit of the chip uses an external input power supply 5 to power the load circuit 4 during the CAPTURE period. At this time, the external input power supply 5 only needs to input a small current to the load circuit 4. Therefore, the external port of the external input power supply 5 can be used with a common GPIO (General-purpose input / output) port, and no additional independent pins are required. During the period when the load circuit 4 is powered by the external input power supply 5, the current output by the load circuit 4 is the leakage current of the chip under test in the static state, and the leakage current is used to detect whether the chip under test has an abnormality.

[0055] As an optional embodiment, when the leakage current is greater than a preset current threshold, it is determined that the chip under test is abnormal.

[0056] Specifically, the leakage current of a fault-free chip under static conditions is very small, usually in the order of microamperes. When a fault occurs in the chip under test (such as bridging or gate-source shorting), a low-resistance path from the positive power supply to the ground is formed in the static current test circuit of the chip, resulting in a significant increase in the total power supply current, which may exceed the order of milliamperes, that is, exceed the preset current threshold. Therefore, it is possible to determine whether the chip under test is abnormal based on whether the leakage current measured during the static current test of the chip is greater than the preset current threshold.

[0057] As an optional embodiment, the static current test circuit of the chip uses an internal digital signal to switch the power supply between the SHIFT mode and the CAPTURE mode without affecting the normal power supply mode during the SHIFT period.

[0058] Specifically, the switching between the SHIFT mode and the CAPTURE mode of the static current test circuit of the chip can be divided into the following steps:

[0059] Step S1, connecting the external input power 5 to the external port;

[0060] According to the size of the digital circuit to be tested, a stable voltage source is provided to the chip to be tested from an external input port. Usually, the current of the external input power source 5 is in the microampere level.

[0061] Step S2, setting the internal SCAN EN and IDDQ MODE signals to jointly control the switching of the power supply;

[0062] The chip enters the IDDQ test mode state by configuring the test register, and the default power supply of the digital circuit to be tested comes from the inside of the chip.

[0063] In the IDDQ test SHIFT process, the power supply is switched by configuring the SCAN EN and IDDQ MODE signals. In the program source code, when the value of tcu_mode_iddq_scan&~ tcu_scan_enable is 0, the value of the corresponding control signal bypass_en is L, and the value of the control signal bypass_enb is H, that is, the gates of the first NMOS tube, the third NMOS tube, and the fourth NMOS tube input low-level signals, and the gate of the second NMOS tube inputs high-level signals. At this time, the power supply mode is the internal LDO power supply;

[0064] During the IDDQ test CAPTURE process, all devices in the circuit are in static state and only have static leakage current. In the program source code, when the value of tcu_mode_iddq_scan&~ tcu_scan_enable is 1, the corresponding control signal bypass_en is H, and the control signal bypass_enb is L, that is, the gates of the first NMOS tube, the third NMOS tube and the fourth NMOS tube input high-level signals, and the gate of the second NMOS tube inputs low-level signals. At this time, the power supply mode is the external input power supply 5.

[0065] Step S3, determining whether there is any abnormality inside the entire chip;

[0066] Among them, when the IDDQ test is in the CAPTURE process, by measuring whether the current value of the external input power supply 5 input to the digital circuit to be tested exceeds the set threshold, it can be determined whether there is an abnormality inside the chip. When the current value of the digital circuit to be tested does not exceed the set threshold, there is no abnormality inside the chip and it can be used normally; when the current value of the digital circuit to be tested exceeds the set threshold, there is an abnormality inside the chip.

[0067] By switching the power supply between the IDDQ test SHIFT mode and the CAPTURE mode, not only is it ensured that the digital circuit under test of the chip can be powered normally during the SHIFT mode, but also the circuit can be detected for abnormalities by inputting only a small current during the CAPTURE mode, ensuring that the port of the external input power supply 5 can be reused with the ordinary GPIO of the chip, without the need for an additional power supply interface, thus saving the pins of the chip.

[0068] As can be seen from the above description, a static current test circuit of a chip provided by the present invention comprises an amplifier circuit, an output circuit, a voltage-dividing resistor path, a load circuit and an external input power supply; a first bypass switch is arranged between the first output end of the amplifier circuit and the third input end of the output circuit, and the first bypass switch is used to control the internal power supply of the chip to be tested to supply power to the output circuit; a first bypass switch and a third bypass switch are arranged between the output circuit and the voltage-dividing resistor path, the first bypass switch is used to control the conduction or cutoff of the voltage-dividing resistor path, and the third bypass switch is used to ground the source of the first bypass switch; a fourth bypass switch is arranged between the input end of the external input power supply and the input end of the load circuit, and the fourth bypass switch is used to control the conduction or cutoff of the external input power supply and the load circuit. When the chip is powered by a Capless LDO, only the chip's own GPIO pin is used as the external power supply port during the IDDQ test to measure the static current of the internal Capless LDO, so that the IDDQ test method can be used to detect the fault of the chip's digital circuit. At the same time, the conversion of the power supply between the SHIFT mode and the CAPTURE mode is realized through the internal digital signal, so that the normal power supply of the digital circuit to be tested during the SHIFT mode is not affected, and the IDDQ test method is reliably applied.

[0069] It should be noted that some embodiments of the present invention are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0070] refer to Figure 4 , which is a structural block diagram of a chip provided in an embodiment of the present invention.

[0071] Based on the same inventive concept, corresponding to the static current test circuit of the chip described in any of the above embodiments, the present invention further provides a chip, and the chip 400 includes the static current test circuit of the chip described in any of the above embodiments.

[0072] The chip of the embodiment of the present invention, when the chip adopts the internal Capless LDO power supply mode, uses the external port to input a small current during the Capture period to perform the IDDQ test, so as to measure the static current of the chip, which solves the problem that the internal Capless LDO current cannot be measured. At the same time, the external port can be reused with the common GPIO of the chip, without the need for an additional power PAD, thereby saving pins; in addition, the power supply of the SHIFT mode and the CAPTURE mode is switched by using the internal digital signal, which does not affect the normal power supply mode of the circuit to be tested during the SHIFT period, and the static current is tested in time while ensuring the normal operation of the chip.

[0073] Based on the same inventive concept, corresponding to the test circuit described in any of the above embodiments, the present invention also provides an electronic device, including the chip described above, for implementing the static current test circuit of the corresponding chip in any of the above embodiments, and having corresponding beneficial effects, which will not be repeated here.

[0074] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0075] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0077] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0079] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0080] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0081] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A static current test circuit for a chip, characterized in that: It includes an amplifier circuit (1), an output circuit (2), a voltage divider resistor path (3), a load circuit (4) and an external input power supply (5); A first bypass switch is provided between the first output terminal (13) of the amplifier circuit (1) and the third input terminal (21) of the output circuit (2), the first bypass switch being used to control the input of the internal power supply of the chip under test to the output circuit (2); A second bypass switch and a third bypass switch are provided between the output circuit (2) and the voltage-dividing resistor path (3), the second bypass switch being used to control the on or off state of the voltage-dividing resistor path (3), and the third bypass switch being used to ground the source of the second bypass switch; A fourth bypass switch is provided between the input end (51) of the external input power source and the input end (41) of the load circuit, the fourth bypass switch being used to control whether the external input power source (5) supplies power to the load circuit (4) or not; The first input terminal (11) of the amplifier circuit (1) is used to receive a reference voltage, the second input terminal (12) of the amplifier circuit (1) is used to receive a feedback voltage of the voltage-dividing resistor path (3), the first output terminal (13) of the amplifier circuit (1) is connected to the third input terminal (21) of the output circuit (2), the fourth input terminal (22) of the output circuit (2) is used to receive an internal input voltage of an internal power supply of the chip under test, the second output terminal (23) of the output circuit (2) is connected to an input terminal (41) of the load circuit, and the output terminal (52) of the external input power supply is connected to the input terminal (41) of the load circuit.

2. The static current test circuit of the chip according to claim 1, characterized in that: The voltage-dividing resistor path (3) comprises a first load resistor and a second load resistor, and the feedback voltage is a voltage between the first load resistor and the second load resistor.

3. The static current test circuit of a chip according to claim 1, characterized in that: The first bypass switch is a first NMOS transistor, the drain of the first NMOS transistor is connected to the first output end (13) of the amplifier circuit (1), and the source of the first NMOS transistor is grounded; the second bypass switch is a second NMOS transistor, the drain of the second NMOS transistor is connected to the second output end (23) of the output circuit (2), and the source of the second NMOS transistor is connected to the input end of the voltage divider resistor path (3); the third bypass switch is a third NMOS transistor, the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, and the source of the third NMOS transistor is grounded; the fourth bypass switch is a fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the external input power supply (5) through an ATB bus, and the source of the fourth NMOS transistor is connected to the load circuit (4).

4. The static current test circuit of the chip according to claim 3, characterized in that: include: In the SHIFT phase of the IDDQ test mode, when the gate of the first NMOS tube receives a low-level control signal, the gate of the second NMOS tube receives a high-level control signal, the gate of the third NMOS tube receives a low-level control signal, and the gate of the fourth NMOS tube receives a low-level control signal, the first bypass switch is turned off, the second bypass switch is turned on, the third bypass switch is turned off, and the fourth bypass switch is turned off, and the static current test circuit of the chip supplies power to the load circuit (4) through an internal power supply.

5. The static current test circuit of the chip according to claim 3, characterized in that: include: In the CAPTURE stage of the IDDQ test mode, when the gate of the first NMOS tube receives a high-level control signal, the gate of the second NMOS tube receives a low-level control signal, the gate of the third NMOS tube receives a high-level control signal, and the gate of the fourth NMOS tube receives a high-level control signal, the first bypass switch is turned on, the second bypass switch is turned off, the third bypass switch is turned on, and the fourth bypass switch is turned on, and the static current test circuit of the chip supplies power to the load circuit (4) through an external input power supply (5).

6. The static current test circuit of the chip according to claim 5, characterized in that: include: When the static current test circuit of the chip supplies power to the load circuit (4) through an external input power supply (5), the load circuit (4) generates a leakage current in a static state; wherein the leakage current is used to determine whether the chip to be tested has an abnormality.

7. The static current test circuit of a chip according to claim 6, characterized in that: include: When the leakage current is greater than a preset current threshold, it is determined that the chip to be tested is abnormal.

8. A chip, characterized in that: A static current test circuit comprising a chip as claimed in any one of claims 1 to 7.

9. An electronic device, characterized in that: A chip comprising the chip as claimed in claim 8.

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