A memory structure

Abstract

A memory structure provided by the present invention includes a memory array and a logic layer, wherein the memory array is arranged at one end or both ends of the logic layer, and the memory array and the logic layer are connected and communicated through a TSV channel, and the memory structure also includes a TSV channel redundancy structure, wherein the redundancy structure includes a redundant channel, and the redundant channel is located on one side of the TSV channel; the TSV channel is provided with a repair circuit, and the repair circuit establishes a connection and communication between a signal transmitting end or a signal receiving end and a TSV channel and a redundant channel where no error occurs based on the position where the error occurs in the TSV channel. The beneficial effect of this technical solution is that the TSV redundant channel structure is improved, the redundant channel is located on one side of the TSV channel, the number of TSV channels is reduced, the TSV channel structure is optimized, and the failed TSV channel is repaired by the repair circuit, which has the advantage of high repair efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory, and in particular relates to a memory structure. Background Art

[0002] DRAM (Dynamic Random Access Memory) is generally composed of two parts: control logic (LOGIC) and storage array (ARRAY). The storage array is mainly composed of a large number of storage cells and detection amplifiers. The storage array determines the storage capacity of DRAM. Figure 1 As shown in the figure, the logic control circuit and storage array circuit of traditional DRAM are integrated on the same plane, which can be called 2D (Two-Dimensional) DRAM. The capacity of 2D DRAM per unit area is mainly limited by the size of the storage unit. Generally, the storage capacity of 2D DRAM per unit area is increased by reducing the area of ​​the storage unit through the process. At present, DRAM technology has gradually entered a bottleneck period. The industry predicts that its reduced size will reach the physical limit, and it is necessary to find new architectures and materials to increase the capacity of DRAM per unit area. Therefore, 3D (Three-Dimensional) DRAM is the industry's first choice as a new path to break through the limits of DRAM technology.

[0003] like Figure 2 As shown in the figure, HBM (High Bandwidth Memory) DRAM stacks DRAM Die (bare die) on LOGIC Die (bare die), and uses TSV (Through Silicon Via) technology to achieve connection and communication between stacked layers. Different DRAM dies share TSVs, and use time-division multiplexing to transmit storage data. The shared TSVs limit the transmission data rate of the stacked layers, and the failure of TSVs may eventually cause the failure of the entire stack. There are many factors that cause TSV failure. For example, during the manufacturing process of TSVs, due to the limitations of process technology and the influence of accidental factors, some TSVs will inevitably fail to work properly. If a TSV fails to work properly during the stacking process, the module connected to it fails, and then the entire 3D DRAM fails to work properly, resulting in a decrease in the reliability of the stacked circuit and a decrease in the yield. In order to improve the reliability of the circuit, redundancy technology is added to the design to repair the faults that occur. Among them, by adding redundant TSVs to replace failed TSVs, the fault tolerance rate is high, but as the number of TSVs increases, the number of redundant TSVs increases, the area increases, the circuit complexity increases, and the cost is higher.

[0004] Therefore, it is necessary to design a new memory structure that can reduce the impact of TSV failure. Summary of the invention

[0005] The present invention provides a memory structure, which reduces the impact of TSV failure while not increasing the redundant TSV area by improving the redundant TSV structure.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a memory structure, including a memory array and a logic layer, wherein the memory array is arranged at one end or both ends of the logic layer, and the memory array and the logic layer are connected and communicated through a TSV channel, and the memory structure also includes a TSV channel redundancy structure, wherein the redundancy structure includes a redundant channel, and the redundant channel is located on one side of the TSV channel; the TSV channel is provided with a repair circuit, and the repair circuit establishes a connection and communication between a signal sending end or a signal receiving end and a TSV channel and a redundant channel where no error occurs based on the position where the error occurs in the TSV channel. The beneficial effect of this technical solution is that the TSV redundant channel structure is improved, the redundant channel is located on one side of the TSV channel, the number of TSV channels is reduced, the TSV channel structure is optimized, and the failed TSV channel is repaired by the repair circuit, which has the advantage of high repair efficiency.

[0008] When the memory arrays are stacked at one end or both ends of a logic layer, the stacked memory arrays do not share a TSV channel.

[0009] When the TSV channel where the error occurs is farthest from the redundant channel, the signal sending end and the signal receiving end establish communication with the adjacent TSV channels of the TSV channel where the error occurs in the direction of the redundant channel setting in sequence, and the last signal sending end and signal receiving end in the direction of the redundant channel setting establish communication with the redundant channel; when the TSV channel where the error occurs is located in the middle of the TSV channel, the TSV channel where the error does not occur establishes communication normally, the TSV channel where the error occurs and the signal sending end and the signal receiving end corresponding to the remaining TSV channels in the direction of the redundant channel setting establish communication with the adjacent TSV channels of the TSV channel where the error occurs in the direction of the redundant channel setting, and the last signal sending end and signal receiving end in the direction of the redundant channel setting establish communication with the redundant channel; when the TSV channel where the error occurs is adjacent to the redundant channel, the signal sending end and the signal receiving end corresponding to the TSV channel where the error occurs establish communication with the redundant channel.

[0010] The repair circuit includes a three-state gate circuit a for transmitting any of the signal sending ends to the corresponding TSV channel, and any of the TSV channels to the corresponding signal receiving ends; a three-state gate circuit b is set between any of the signal sending ends and any of the TSV channels corresponding to the signal sending ends in the direction of the redundant channel setting, and between any of the TSV channels and any of the signal receiving ends corresponding to the TSV channels in the opposite direction of the redundant channel setting; the three-state gate circuit a and the three-state gate circuit b select the connection between the signal sending end and the TSV channel or the redundant channel, and select the connection between the TSV channel or the redundant channel and the signal receiving end through the control of a control signal.

[0011] The repair circuit also includes a logic control circuit, which outputs a tri-state gate circuit a control signal and a tri-state gate b control signal according to an input TSV channel error signal and an enable signal; the voltage states of the tri-state gate circuit a control signal and the tri-state gate b control signal are different.

[0012] The control signal of the three-state gate circuit a output by the logic control circuit turns the control signal of the three-state gate circuit a corresponding to the erroneous TSV channel toward the front of the redundant channel into a level for controlling the three-state gate circuit a to transmit data; the control signal of the three-state gate circuit a corresponding to the erroneous TSV channel and the TSV channel toward the front of the redundant channel is output as a level for controlling the three-state gate circuit a to output a high-impedance state.

[0013] It also includes a TSV channel failure detection circuit, which includes a TSV channel located between a signal sending end and a signal receiving end, wherein both the signal sending end and the signal receiving end are provided with a D flip-flop, wherein the data input end of the D flip-flop is connected to the transmission data, and the clock input end of the D flip-flop is connected to the clock signal; a three-state gate circuit c is provided between the D flip-flop of the signal sending end and the TSV channel; a three-state gate circuit d is provided between the TSV channel and the D flip-flop of the signal receiving end; the three-state gate circuit c and the three-state gate circuit d are controlled by a control signal; the signal receiving end is also connected to a signal detection end; the clock signal changes the data stored in the D flip-flop, and the three-state gate circuit c and the three-state gate circuit d are controlled by the control signal, so that a specific signal is transmitted from the signal sending end to the signal receiving end through the TSV channel, and then the transmission data is tested by the signal detection end to detect whether the TSV channel fails.

[0014] The D flip-flop at the signal sending end and the signal receiving end of the failure detection circuit share the same input data end.

[0015] The failure detection circuit stores information of the failed TSV channel, generates the TSV channel error signal and loads it to the logic control circuit of the repair circuit to repair the error TSV channel.

[0016] The number of the TSV channels sharing one redundant channel is 1-128.

[0017] The TSV channels between the signal transmitting end and the signal receiving end are grouped, each group of the TSV channels is configured with a redundant channel, and the number of the TSV channels in each group is 1-128.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The DRAM storage capacity per unit area is increased by stacking the storage array, and the TSV channels are not shared between the stacked layers, which can improve the data transmission rate and increase the flexibility of the spatial layout.

[0019] 2. Provide TSV redundancy technology to limit the number of TSV channels that share redundant channels, reduce the failure probability of TSV channels that share a TSV redundant channel, and reduce the risk of TSV channel failure while ensuring the simplicity of the redundant channel structure.

[0020] 3. Improve the TSV redundant channel structure, group the TSV channels, and each group of TSV channels shares a redundant channel, and the redundant channel is located on one side of the TSV channel, which reduces the number of TSV channels and optimizes the TSV channel structure.

[0021] 4. The failure detection circuit detects the failure of the TSV channel, and the generated error signal is used for the logic control circuit of the failure repair circuit to generate a logic control signal to control the failure repair circuit to repair the TSV channel where the error occurs, with the function of automatic monitoring and automatic repair.

[0022] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 Schematic diagram of traditional 2D DRAM.

[0025] Figure 2 Schematic diagram of HBM DRAM.

[0026] Figure 3 FIG. 1 is a schematic diagram of a 3D DRAM with stacked memory arrays in Embodiment 1.

[0027] Figure 4 This is a repair circuit in which each group of four TSV channels in the first embodiment shares a redundant channel.

[0028] Figure 5 This is a three-state gate circuit enable end logic control circuit in embodiment 1.

[0029] Figure 6 This is another three-state gate circuit enable end logic control circuit in the first embodiment.

[0030] Figure 7 In the present invention, each group of four TSV channels shares a redundant channel for signal repair transmission path.

[0031] Figure 8 Schematic diagram of the failure detection circuit of the present invention.

[0032] Fig. 9 FIG. 4 is a flow chart of TSV testing and repairing according to the present invention. DETAILED DESCRIPTION

[0033] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0034] Embodiment 1

[0035] The first embodiment provides a memory structure. The general 3D DRAM stacking technology uses different layers of shared TSV for connection communication. It transmits the storage data of different layers through time division multiplexing, which limits the data bandwidth and transmission rate. The 3D DRAM stacking in the first embodiment adopts a non-shared TSV structure. Figure 3 The memory structure includes a logic layer at the bottom and a memory array above the logic layer, wherein the memory array may be stacked on the logic layer or not formed on the logic layer in a stacked manner. Figure 3 , Figure 3 In A, the stacked memory arrays do not share TSV channels. Figure 3 In B, the stacked memory array has a shared TSV channel and a non-shared TSV channel. Figure 3In B, the memory array close to the logic chip does not share TSV channels. Not sharing TSV channels can stagger the chips and provide space for the chips to dissipate heat. When the temperature rises, it will affect the data of the memory cell. The higher the temperature, the faster the leakage. Therefore, in order to improve the performance of the memory cell, the stacked memory array does not share TSV channels.

[0036] The reliability of 3D DRAM is related to the number of TSVs. Without any redundancy technology, the relationship is exponential. As the number of TSVs increases, the reliability decreases exponentially. As the number of TSVs per layer and the number of stacked layers increase, the reliability of 3D stacking becomes worse, the yield becomes lower, and the manufacturing cost becomes higher. In order to improve the reliability of stacked circuits and reduce manufacturing costs, a redundancy technology with high fault tolerance and low area overhead is provided.

[0037] Assume that m is the total number of TSVs in the entire 3D DRAM, n is the number of 3D DRAM TSV failures, k is the failure rate of a single TSV, and P is the probability of n failures when the total number of TSVs is m. From the probability formula, we can get:

[0038]

[0039] F(S) is the probability when the number of TSV failures n≤1 in the entire 3D DRAM without adopting any redundancy technology.

[0040]

[0041] According to relevant research, the failure rate k of a single TSV is about 10 -4 to 10 -5 Assuming that the failure rate of a TSV is 10 -4 According to formulas (1) and (2), the probability distribution of the number of TSV failures n≤1 is shown in Table 1.

[0042] Table 1 Probability of TSV failure number n≤1 (%)

[0043]

[0044] It can be seen from Table 1 that when the number of TSVs is controlled within 5000, the probability of TSV failure number n≤1 is greater than 90%. In other words, after repair, when only TSVs are considered, the chip yield is greater than 90%.

[0045] The redundant channel set in this paper uses multiple TSV channels to share one redundant channel. In order to ensure that the chip yield is greater than 99.99%, it can be obtained from formula (1) and formula (2) that when the number of TSVs sharing a redundant channel is between 1 and 128, the chip yield can meet the requirements. Multiple TSV channels sharing a redundant channel are called a TSV chain. When the chain length decreases, it means that the number of redundant channels needs to be increased. At this time, the circuit area overhead is large and the cost will increase accordingly. The relationship between the TSV chain length and the repair rate is shown in Table 2. The TSV chain length is selected based on the demand. The data in Tables 1 and 2 will improve with the advancement of process technology, indicating the high portability of this method.

[0046] Table 2 Relationship between TSV chain length and repair rate (%)

[0047]

[0048] In order to describe the TSV error channel repair process for redundant channels in detail, 32 TSV signals are used as an example. In order to optimize the redundant channel structure, the TSV signals can be grouped, and each group of TSV channels shares a redundant channel, where the number of TSV channels in each group is less than or equal to 2. R , R is the number of bits of the error signal input to the logic control circuit of the repair circuit (the error signal characterizes the position of the TSV channel where the error occurs through a multi-bit signal), and each group of shared redundant channels is located on one side of the TSV channel of this group. According to the relationship between the TSV chain length and the failure rate mentioned above, in order to ensure the yield of the chip, the number of TSV channels in each group is 1-128. When there are 32 TSV signals, they can be divided into 8 groups with a chain length of 4. Each group adds 1 redundant channel, so the actual chain length of each group is "4+1", where "4" is the normal TSV[3:0] and "1" is the redundant channel TSV[4].

[0049] Repair circuit diagram see Figure 5 , Figure 4 , Figure 6 as well as Figure 7 , Figure 4 The circuit diagram of the repair circuit for each group of 4 TSV channels sharing a redundant channel, Figure 5 The logic control circuit diagram of the repair circuit for the two-bit variable input error signal, Figure 6 The logic control circuit diagram of the repair circuit for the three-bit variable input error signal (each group of 8 TSV channels share a redundant channel). The repair process of each group of 4 TSV channels sharing a redundant channel is shown in Figure 7 The repair process of each group of 8 TSV channels sharing a redundant channel is similar to Figure 7The repair process of is similar and will not be described here. The repair circuit of the present invention includes a transmitting end and a receiving end, the transmitting end and the receiving end are located between different layers, there are three-state gate circuits N and three-state gate circuits S between the transmitting end and the TSV channel, and similarly, there are three-state gate circuits N and three-state gate circuits S between the TSV channel and the receiving end. The three-state gate circuits S and the three-state gate circuits N are arranged at intervals, and the three-state gate circuits S are arranged on the upper part of the three-state gate circuits N (the setting direction of the three-state gate circuits S is toward the redundant channel direction), wherein the signals of the transmitting end and the receiving end are directly transmitted to the TSV channel through the three-state gate circuits N, and the signals are directly transmitted through the three-state gate circuits N, which is called the normal path. The three-state gate circuit S is a redundant path for the transmitting end signal or the receiving end signal to transmit the signal, which establishes a signal transmission from the transmission signal {B(0), B(1), B(2), B(3)} to the adjacent channel of the corresponding TSV channel and the redundant channel {TSV(1), TSV(2), TSV(3), TSV(4)}. When an error occurs in a certain TSV channel, the transmitting end signal can open a redundant path under the control of the tri-state gate circuit control signal, so that the signal can be transmitted from the redundant path, thereby repairing the error TSV channel.

[0050] The generation of the three-state gate circuit control signal, see Figure 5 as well as Figure 6 , Figure 5 The error signal of the two-bit variable input can represent up to 4 situations, and the corresponding error information of up to 4 TSV channels can be located. Figure 6 The error signal of the three-bit variable input can represent up to 8 situations, and can locate the error information of up to 8 TSV channels. When there are multiple TSV channels sharing the same redundant channel, the error signal representing the error channel information can be composed of R-bit signals, 2 R Greater than or equal to the number of TSV channels that share a redundant channel.

[0051] Table 3 shows the error information corresponding to the input error signal composed of two variables and the data of the control signal of the output three-state gate circuit N and the three-state gate S.

[0052] Table 3 Input error signal data of two variables

[0053]

[0054] Table 4 shows the error information corresponding to the input error signal composed of three variables and the data of the control signal of the output three-state gate circuit N and the three-state gate S.

[0055] Table 4 Input error signal data of three variables

[0056]

[0057] See also Figure 5 as well as Figure 6 , when the error signal R[1:0] or R[2:0] in Table 3 and Table 4 is input into the control circuit, the enable signal ENB and the low-level input signal VSS are input into the control circuit at the same time, the enable signal is used to characterize whether there is an error TSV channel (taking Table 3 as an example, when there is no error TSV channel, the enable signal outputs 1, and at this time, whether there is an error signal input or not, it does not affect the operation of the three-state gate control circuit), and the control signal N[3:0] or N[7:0] of the three-state gate control circuit N is output, and the control signal S[3:0] or S[7:0] of the three-state gate control circuit S is output. The effective level states of the three-state gate control circuit N and the three-state gate control signal S are opposite, indicating that each input signal can only be output through one three-state gate circuit. When the three-state gate circuit control signal of the present application is output as a high level "1", the three-state gate circuit outputs a high impedance state, and when the three-state gate circuit control signal is a low level signal "0", it is a valid signal, and the three-state gate circuit is used for data transmission between the data sending end and the data receiving end. The control signal data of the output three-state gate circuit N is related to the position of the TSV channel where the error occurs. The control circuit outputs the control signal of the three-state gate circuit N corresponding to all TSV channels before the TSV channel where the error occurs as a low level "0" (the three-state gate circuit works and transmits the signal), and the TSV channel where the error occurs and the TSV channels thereafter are output as a high level "1" (output high impedance state). In this way, it can be ensured that the three-state gate circuit S of the redundant path at the TSV channel where the error occurs is turned on, and the signal is transmitted by the redundant path, thereby skipping the erroneous TSV channel and realizing the repair of the erroneous TSV channel.

[0058] See also Figure 7 The repair of the TSV channel of the present application includes four situations. For example, each group of four TSV channels shares a redundant channel. When no repair occurs, all data transmission paths remain unchanged. When the wrong TSV channel is farthest from the redundant TSV, all data are communicated from the upper-level TSV channel of the TSV channel corresponding to the data transmission (the TSV channel adjacent to the redundant channel setting direction) until the last redundant channel establishes communication with the last data, that is, Figure 7When the erroneous TSV channel is located in the middle of the TSV chain, the TSV channels without errors maintain normal communication, and the data at the TSV channel with errors establishes communication with the upper-level TSV channel of the TSV channel with errors (the TSV channel adjacent to the redundant channel setting direction). When the erroneous TSV channel is located closest to the redundant channel in the TSV chain, the data corresponding to the erroneous TSV channel directly establishes communication with the redundant channel, and the remaining TSV channels transmit data normally.

[0059] Embodiment 1 In order to facilitate the detection of the TSV channel position where an error occurs, a failure detection circuit is also provided. Figure 8 , Figure 8 Taking four TSV channel transmissions as an example, the working principle of the failure detection circuit is explained. The failure detection circuit of the first embodiment includes multiple TSV channels located between different layers for signal transmission, and there are D flip-flops for data transmission between the TSV channels. The data input end of the D flip-flop is connected to the transmission data tm_scanin, and the D flip-flops at both ends of the TSV transmission channel share the same transmission data end tm_scanin. The output ends of the D flip-flops at both ends of the TSV channel select the output signal through two three-state gate circuits. The control signals of the two three-state gate circuits are tm_scanen_lid and tm_scanen_logic, respectively. The two control signals are used to control the transmission signals of TSV channels in different layers. The failure detection circuit is also provided with clock signals tm_scanclk_lid and tm_scanclk_logic connected to the clock input end of the D flip-flop. The two clock signals are used to change or obtain the data stored or transmitted in the D flip-flop. Under the control of the control signals of the two three-state gate circuits, specific data is transmitted from the signal sending end to the signal receiving end through the TSV channel, and finally the result tm_scanout is output. At this time, the result of tm_scanout is monitored and compared with the final required output result to detect which TSV channel has an error. Figure 8 The failure detection results of the TSV failure detection circuit shown are shown in Table 5 below, where “|” in the clock signals tm_scanclk_lid and tm_scanclk_logic represents the clock signal.

[0060] Table 5 Figure 8 The TSV failure detection circuit test results shown

[0061]

[0062] After the failure detection circuit detects the location of the failed TSV channel, it stores the error information and loads the error information to the redundant repair module in the repair module for repair. The redundant repair module inputs the error information to the control circuit input end of the failure repair circuit to generate a control signal of the corresponding three-state gate control circuit, so that the failure repair circuit repairs the failed TSV channel. For a specific flow chart, see Fig. 9 .

[0063] The above is a detailed introduction to a memory structure provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A memory structure, comprising a memory array and a logic layer, wherein the memory array is arranged at one end or both ends of the logic layer, and the memory array and the logic layer are connected and communicated via a TSV channel, characterized in that: The memory structure further includes a TSV channel redundancy structure, wherein the redundancy structure includes a redundant channel, and the redundant channel is located at one side of the TSV channel; The TSV channel is provided with a repair circuit, and the repair circuit establishes connection communication between a signal transmitting end or a signal receiving end and a TSV channel in which no error occurs and a redundant channel based on the position where the error occurs in the TSV channel; The repair circuit includes a tri-state gate circuit a that transmits any of the signal sending ends to the corresponding TSV channel, and any of the TSV channels to the corresponding signal receiving end; A tri-state gate circuit b is provided between any of the signal sending ends and the adjacent TSV channel in the direction in which the TSV channel corresponding to any of the signal sending ends is set toward the redundant channel, and between any of the TSV channels and the adjacent signal receiving end in the direction opposite to the redundant channel in which the signal receiving end corresponding to any of the TSV channels is set; the tri-state gate circuit a and the tri-state gate circuit b select the connection between the signal sending end and the TSV channel or the redundant channel, and select the connection between the TSV channel or the redundant channel and the signal receiving end through the control of a control signal; It also includes a TSV channel failure detection circuit, the TSV failure detection circuit includes a TSV channel located between a signal transmitting end and a signal receiving end, the signal transmitting end and the signal receiving end are both provided with a D flip-flop, the data input end of the D flip-flop is connected to the transmission data, and the clock input end of the D flip-flop is connected to the clock signal; A three-state gate circuit c is arranged between the D flip-flop of the signal sending end and the TSV channel; a three-state gate circuit d is arranged between the TSV channel and the D flip-flop of the signal receiving end; the three-state gate circuit c and the three-state gate circuit d are controlled by a control signal; the signal receiving end is also connected to a signal detection end; the clock signal changes the data stored in the D flip-flop, and controls the three-state gate circuit c and the three-state gate circuit d through the control signal, so that a specific signal is transmitted from the signal sending end to the signal receiving end through the TSV channel, and then the transmitted data is tested by the signal detection end to detect whether the TSV channel fails.

2. A memory structure according to claim 1, characterized in that: When the memory arrays are stacked at one end or both ends of a logic layer, the stacked memory arrays do not share a TSV channel.

3. A memory structure according to claim 1, characterized in that: When the TSV channel where the error occurs is farthest from the redundant channel, the signal sending end and the signal receiving end sequentially establish communication with the TSV channels adjacent to the TSV channel where the error occurs in the direction of the redundant channel setting, and the last signal sending end and signal receiving end in the direction of the redundant channel setting establish communication with the redundant channel; When the TSV channel where the error occurs is located in the middle of the TSV channel, the TSV channel where the error occurs establishes communication normally, the signal sending end and the signal receiving end corresponding to the TSV channel where the error occurs and the remaining TSV channels facing the redundant channel setting direction establish communication with the adjacent TSV channel of the TSV channel where the error occurs facing the redundant channel setting direction, and the last signal sending end and signal receiving end facing the redundant channel setting direction establish communication with the redundant channel; When the TSV channel where the error occurs is adjacent to the redundant channel, the signal transmitting end and the signal receiving end corresponding to the TSV channel where the error occurs establish communication with the redundant channel.

4. A memory structure according to claim 1, characterized in that: The repair circuit further includes a logic control circuit, which outputs a tri-state gate circuit a control signal and a tri-state gate b control signal according to an input TSV channel error signal and an enable signal; The voltage state of the control signal of the tri-state gate circuit a is different from that of the control signal of the tri-state gate circuit b.

5. A memory structure according to claim 4, characterized in that: The logic control circuit outputs a control signal of the tri-state gate circuit a, and outputs the control signal of the tri-state gate circuit a corresponding to the TSV channel in front of the error TSV channel toward the redundant channel as a low level to control the tri-state gate circuit a to transmit data; The control signal output of the tri-state gate circuit a corresponding to the erroneous TSV channel and the TSV channel in front of the redundant channel is a level that controls the tri-state gate circuit a to output a high impedance state.

6. A memory structure according to claim 1, characterized in that: The D flip-flops at the signal sending end and the signal receiving end of the failure detection circuit share the same input data.

7. A memory structure according to claim 5, characterized in that: The failure detection circuit stores information of the failed TSV channel, generates the TSV channel error signal and loads it to the logic control circuit of the repair circuit to repair the error TSV channel.

8. A memory structure according to claim 1, characterized in that: The number of the TSV channels sharing one redundant channel is 1-128.

9. A memory structure according to claim 1, characterized in that: The TSV channels between the signal transmitting end and the signal receiving end are grouped, each group of the TSV channels is configured with a redundant channel, and the number of the TSV channels in each group is 1-128.

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