LDPC decoding device and electronic apparatus

Abstract

The embodiment of the application discloses a kind of LDPC decoding device and electronic equipment applied to chip, it is related to circuit field.The LDPC decoding device of the application includes: demodulation unit, first buffer unit, second buffer unit, LDPC decoder and controller;Wherein, the output of demodulation unit is connected with the input of first buffer unit, the output of first buffer unit is connected with the input of second buffer unit, the output of second buffer unit is connected with LDPC decoding unit;Controller is connected with the control end of first buffer unit and the control end of second buffer unit respectively;First data queue is arranged in first buffer unit, and second data queue is arranged in second buffer unit.The queue buffering mechanism is introduced in the application, the order and integrity of data are guaranteed, decoding requirements are flexibly adapted, and the rate matching problem between the LDPC decoder of rear end and the demodulation unit of front stage is effectively solved by using asynchronous processing mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit, in particular to an LDPC decoding device and electronic equipment. BACKGROUND

[0002] The current FIFO buffer unit is to buffer data by using fixed bit width input and fixed bit width output. In the WIFI protocol, the LDPC code is mainly 648 / 1296 / 1944, but the variable code length of 1 / 2 / 4 / 6 / 8 appears in the demodulation unit of the previous stage. At the same time, there are shorten / puncture / repeat bit structures in the LDPC code, which need to insert some fixed code words in the code length of the previous stage. Therefore, the current FIFO buffer unit cannot meet the flexible and variable code length in the process of executing LDPC decoding. SUMMARY

[0003] The LDPC decoding device and electronic equipment provided by the embodiments of the present application can solve the problem of rate mismatch between the demodulation unit of the previous stage and the LDPC decoder of the back end. The technical solution is as follows:

[0004] In a first aspect, the embodiments of the present application provide an LDPC decoding device, comprising:

[0005] a demodulation unit, a first buffer unit, a second buffer unit, an LDPC decoder and a controller;

[0006] The output end of the demodulation unit is connected with the input end of the first buffer unit, the output end of the first buffer unit is connected with the input end of the second buffer unit, and the output end of the second buffer unit is connected with the LDPC decoding unit. The controller is connected with the control end of the first buffer unit and the control end of the second buffer unit respectively. The first data queue is arranged in the first buffer unit, and the second data queue is arranged in the second buffer unit.

[0007] The demodulation unit is used for demodulating a radio frequency signal into a digital code word sequence.

[0008] The controller is used for reading a first fixed length digital code word sequence from the demodulation unit, performing an enqueue operation on the read digital code word sequence according to the position of the tail element of the first data queue, determining a target length according to the decoding requirement, performing a dequeue operation on the head element of the first data queue according to the position of the target length element, performing an enqueue operation on the dequeued element in the first data queue according to the position of the tail element of the second data queue, and performing a dequeue operation on the second fixed length element according to the position of the head element of the second data queue.

[0009] The LDPC decoder is configured to perform a decoding operation on the element dequeued from the second data queue.

[0010] In a second aspect, the present application provides an electronic device comprising the LDPC decoding apparatus described above.

[0011] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0012] When the rate of the digital codeword sequence demodulated by the demodulation unit from the radio frequency signal does not match the expected input rate of the LDPC decoder, it will cause the decoder to malfunction or have low decoding efficiency. The present application introduces a first data queue and a second data queue as a buffering mechanism to solve this rate mismatch problem. The digital codeword sequence demodulated by the demodulation unit is first stored in the first data queue, and the controller performs data enqueuing and dequeuing operations according to the decoding requirements and the queue state, ensuring that the LDPC decoder can receive data at its expected rate. During data transmission and processing, the order and integrity of the data are crucial to the correctness of the decoding. By using the first-in, first-out (FIFO) feature of the queue, the present application ensures that the digital codeword sequence demodulated by the demodulation unit can be received by the LDPC decoder in the correct order, and the integrity of the data is guaranteed. Different decoding requirements may require different lengths of data input. In the present application, the controller can determine the target length according to the decoding requirements and perform dequeuing operations from the first data queue, thereby ensuring that the LDPC decoder can receive data of a length that meets its decoding requirements. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0014] Figure 1 is a structural diagram of the LDPC decoding apparatus provided by the embodiments of the present application;

[0015] Figure 2 is an operation schematic diagram of the first data queue provided by the embodiments of the present application;

[0016] Figure 3 is an operation schematic diagram of the second data queue provided by the embodiments of the present application. DETAILED DESCRIPTION

[0017] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the present application.

[0018] Please refer to Figure 1 The present application provides a structure diagram of an LDPC decoding device, which comprises a demodulation unit 10, a first buffer unit 11, a second buffer unit 12, an LDPC decoder 13 and a controller 14.

[0019] The connection relationship of the above-mentioned components is that the output end of the demodulation unit 10 is connected with the input end of the first buffer unit 11, the output end of the first buffer unit 11 is connected with the input end of the second buffer unit 12, and the output end of the second buffer unit 12 is connected with the LDPC decoding unit 13; the controller 14 is connected with the control end of the first buffer unit 11 and the control end of the second buffer unit 12 respectively; the first buffer unit 11 is provided with a first data queue, and the second buffer unit 12 is provided with a second data queue. The data queue is a special linear table, which only allows the deletion operation at the front end of the table and the insertion operation at the rear end of the table. This data structure follows the principle of FIFO (First In First Out), that is, the element entering the queue first will be removed from the queue first. The first buffer unit 11 and the second buffer unit 12 are combined and arranged in the same chip, which can improve the integration of the device. The controller 14 can include one or more processing cores. The controller 14 connects each part in the whole server 400 by using various interfaces and lines, and removes, executes or calls the data stored in the memory by running or executing the instructions, programs, code sets or instruction sets stored in the memory. Alternatively, the controller 14 can be realized in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA) and programmable logic array (PLA).

[0020] The working principle of the LDPC decoding device of the present application is as follows:

[0021] The demodulation unit demodulates the radio frequency signal into a digital code word sequence.

[0022] The radio frequency signal can be a WiFi radio frequency signal or other radio frequency signal. A suitable antenna is selected to ensure accurate signal capture. The radio frequency receiver receives the radio frequency signal from the antenna and sends it to the demodulation system. Since the radio frequency signal will be attenuated during transmission, it needs to be amplified to enhance the strength and stability of the signal. The mixer in the demodulation unit mixes the received radio frequency signal with the local oscillation signal to generate an intermediate frequency signal. This step is a key step in the demodulation process, which converts the high-frequency radio frequency signal into a lower-frequency intermediate frequency signal for subsequent processing. The mixed intermediate frequency signal is filtered to remove stray signals and noise and retain the target signal. The design of the filter needs to be optimized for specific frequency signals to improve the signal-to-noise ratio. Techniques such as coherent demodulation or non-coherent demodulation are used to demodulate the intermediate frequency signal to a baseband signal. During demodulation, the appropriate demodulation algorithm needs to be selected according to the modulation mode of the signal (such as ASK, FSK, PSK, etc.). After demodulation to a baseband signal, the continuous baseband signal is converted to a discrete digital signal by an analog-to-digital converter (ADC). The digital signal is then encoded into a series of digital code word sequences.

[0023] The controller reads a first fixed length of digital code word sequences from the demodulation unit, performs an enqueue operation on the read digital code word sequences according to the position of the tail element of the first data queue, determines the target length according to the decoding requirements, and performs a dequeue operation on the elements of the target length according to the position of the head element of the first data queue, performs an enqueue operation on the dequeued elements in the first data queue according to the position of the tail element of the second data queue, and performs a dequeue operation on the elements of the second fixed length according to the position of the head element of the second data queue.

[0024] The controller sends a read request to the demodulation unit, and specifies the length of the code word sequence to be read (i.e., the first fixed length). The demodulation unit sends a digital code word sequence of the specified length to the controller in response to the request. After receiving the digital code word sequence, the controller needs to store it in the first data queue. The controller first checks the position of the tail element of the first data queue to determine the position where the new data should be inserted. The controller performs an enqueue operation on the read digital code word sequence according to the position of the tail element, i.e., adds the new data to the end of the queue. According to the decoding requirement, the controller needs to determine a target length, i.e., the number of elements to be extracted from the first data queue. The controller reads the position of the head element of the first data queue to determine the position from which the data should be extracted. The controller continuously extracts elements of the target length from the head of the first data queue, and performs a dequeue operation. The controller transfers the dequeued elements in the first data queue to the second data queue. The controller first checks the position of the tail element of the second data queue to determine the position where the new data should be inserted. The controller performs an enqueue operation on the dequeued elements in the first data queue according to the position of the tail element, i.e., adds these elements to the end of the second data queue. According to the processing requirement or decoding process, the controller needs to extract elements of a certain length from the second data queue for processing. The controller determines a second fixed length, i.e., the number of elements to be extracted from the second data queue. The controller reads the position of the head element of the second data queue, and extracts elements of the corresponding length from the position, and performs a dequeue operation.

[0025] For example, referring to the schematic diagram of the enqueue and dequeue operations of the first data queue shown in Figure 2 In the initial state, the first data queue is an empty queue, the first fixed length is 6, the controller first receives 6 data (elements) from the decoding unit, performs an enqueue operation on the 6 data, and then reads 3 data from the first data queue for the first time and reads 2 data from the first data queue for the second time.

[0026] For example, referring to the schematic diagram of the enqueue and dequeue operations of the second data queue shown in Figure 3 In the initial state, the second data queue is an empty queue, the second fixed length is 5, the controller first performs an enqueue operation on 2 data from the first data queue, and secondly performs an enqueue operation on 3 data from the first data queue. When the number of current elements in the second data queue is greater than or equal to 5, the previous 5 elements are performed a dequeue operation according to the position of the head element of the second data queue.

[0027] The LDPC decoder performs a decoding operation on the dequeued elements in the second data queue.

[0028] The LDPC decoder receives the dequeued elements from the second data queue, which are the digital codeword sequences that have been demodulated and stored in the queue previously. The decoder takes the received data as input, preparing for the LDPC decoding operation. The LDPC decoder first performs an initialization operation, including loading the check matrix of the predefined LDPC code. The selection of the check matrix is crucial for the performance of the decoder, which defines the relationship between the information bits and the check bits. The initialization can also include setting the parameters of the decoding algorithm, such as the number of iterations, the threshold, etc. The LDPC decoder employs an algorithm based on iterative decoding, such as the belief propagation (BP) algorithm or its optimized versions (such as LLR BP, Min-Sum, etc.). In the iterative process, the decoder passes information between the variable nodes and the check nodes through reliability messages (i.e., "messages") to gradually approach the original transmitted information bits. In each iteration, the decoder updates the node information according to the current soft information (such as the log-likelihood ratio LLR) and detects and corrects possible errors based on these information. The LDPC decoder approaches the best decoding result through multiple iterations. After each iteration, the decoder checks whether the current decoding result satisfies the constraint conditions of the check matrix. If the conditions are met (i.e., the check passes), the decoder considers that the correct decoding result has been found and stops the iteration. If the conditions are not met (i.e., the check fails), the decoder continues the next iteration until the maximum number of iterations is reached or other stopping conditions are met. When the decoder stops the iteration, it outputs the final decoding result. This result is the estimate of the original transmitted information, which has been corrected as much as possible for the errors that may have occurred during transmission. The decoding result can be used by subsequent digital signal processing units, such as performing further checks, error correction, or transmission, etc.

[0029] In one or more possible embodiments, the second data queue is provided with a read pointer, which is used to indicate the position of the head element in the second data queue.

[0030] In the initialization process of the data queue or after that, a read pointer is set. This read pointer is a variable that tracks and indicates the position of the current head element in the queue. In the case of an empty queue, the read pointer can point to a predefined invalid position or an empty marker. When a new element is enqueued, the position of the read pointer remains unchanged because it still points to the head element. However, when an element is dequeued from the queue, the read pointer needs to be updated to point to the new head element. This process usually involves moving the read pointer one position forward. By reading the position pointed to by the read pointer, the head element in the queue can be accessed. Since the read pointer always points to the head, the value of the head element can be obtained by simply reading that position without traversing the entire queue. When performing enqueue and dequeue operations on the queue, it is necessary to ensure that the read pointer is synchronized with the state of the queue. For example, after a dequeue operation, the read pointer must be updated to reflect the new head position

[0031] In one or more possible embodiments, the selecting a second fixed length of digital code word sequences starting from the head element of the second data queue for the dequeue operation comprises:

[0032] Detecting the current number of elements in the second data queue;

[0033] If the current number of elements is equal to the second fixed length, selecting the second fixed length of elements starting from the head element of the second data queue for the dequeue operation;

[0034] If the current number of elements is less than the second fixed length, continue to detect the number of elements in the second data queue.

[0035] In which, using the queue management interface or related functions, the current number of elements in the second data queue is queried. This is usually achieved by reading a counter or state variable inside the queue that records the number of elements currently stored in the queue. The detected current number of elements is compared with the predefined second fixed length. This second fixed length is a constant that represents the number of elements that the queue should contain under certain conditions (such as full queue state). If the current number of elements is equal to the second fixed length, the next step of the dequeue operation is performed; otherwise, continue to detect the number of elements in the queue. When the current number of elements is equal to the second fixed length, the dequeue process is started. This is usually achieved by calling the dequeue function or method of the queue, which removes the head element of the queue and may return the value of the element. Because the second fixed length of elements needs to be removed, the dequeue function or method needs to be called in a loop until the number of dequeued elements reaches the second fixed length. Each dequeue operation updates the read pointer and the element count counter of the queue.

[0036] If the current element count is found to be less than the second fixed length when determining the current element count, the dequeue operation is not performed, and the detection of the element count of the queue is continued. This is usually achieved by setting a timer, event listener, or using a polling mechanism to respond in a timely manner when the queue state changes. During the continued detection, appropriate detection frequency and threshold can be set according to specific application scenarios and requirements to avoid unnecessary overhead on system performance caused by frequent detection operations. Throughout the process, attention should be paid to handling possible errors and exceptions, such as dequeue operations when the queue is empty, enqueue operations when the queue is full, etc. These errors and exceptions should be properly handled to avoid program crashes or data loss. At the same time, boundary conditions such as maximum capacity limit of the queue, minimum element quantity requirement, etc. should be checked. These boundary conditions should be strictly followed to ensure the stability and reliability of the queue. Through the implementation of the above steps, the second data queue can automatically perform the dequeue operation when it reaches a certain length, thereby maintaining the stability and efficiency of the queue. At the same time, by continuing to detect the element count of the queue, the queue state changes can be responded to in a timely manner and appropriate processing can be performed.

[0037] In one or more possible embodiments, the performing an enqueue operation on the read digital code word sequence according to the position of the tail element of the first data queue comprises:

[0038] detecting the number of free elements of the first data queue;

[0039] if the number of free elements is less than the length of the read digital code word sequence, discarding the read digital code word sequence;

[0040] if the number of free elements is greater than or equal to the length of the read digital code word sequence, inserting the read digital code word sequence after the tail element of the first data sequence.

[0041] wherein the number of free elements of the first data queue is detected by:

[0042] First, the current used element count and maximum capacity of the first data queue need to be determined. The number of free elements can be obtained by calculating the difference between the maximum capacity and the current used element count. This usually involves accessing the internal state information of the queue or using specific API functions.

[0043] After reading the digital code word sequence, the length of the sequence is obtained. Next, this length is compared with the number of free elements of the first data queue. If the number of free elements is less than the length of the digital code word sequence, it means that the queue does not have enough space to store the entire sequence.

[0044] If the number of free elements is less than the length of the digital code word sequence, a discard operation is performed. This can be achieved by simply ignoring or deleting the read digital code word sequence to ensure that it will not be attempted to be inserted into the queue with insufficient capacity. In some cases, it may be necessary to return an error indication or status code to the caller to inform it that the data has been discarded.

[0045] If the number of free elements is greater than or equal to the length of the digital code word sequence, an insertion operation is performed. This is usually achieved by calling the queue's enqueue function or method, which will add each element of the digital code word sequence to the end of the queue one by one. During this process, it is necessary to ensure that the order of the digital code word sequence remains unchanged and the state information of the queue (such as the number of used elements) is updated correctly.

[0046] Throughout the process, attention should be paid to handling possible boundary conditions and error situations. For example, if the queue is full (i.e. the number of free elements is 0), it is necessary to ensure that no enqueue operation is attempted. In addition, if the read digital code word sequence is empty or invalid, appropriate measures should be taken to handle such cases (such as returning an error code or throwing an exception).

[0047] If the first data queue is accessed in a multi-threaded or concurrent environment, synchronization and concurrency control issues need to be considered. This can be achieved by using locks, semaphores, mutexes or other synchronization mechanisms to ensure that only one thread or process can modify the state of the queue at any time. This can avoid data race and inconsistency problems.

[0048] Through the implementation of the above steps, it can be ensured that the first data queue has enough space when inserting the digital code word sequence, and discards the sequence that cannot be stored if necessary. At the same time, through appropriate synchronization and concurrency control, the correctness and reliability in a multi-threaded or concurrent environment can be ensured.

[0049] In one or more possible embodiments, the target length is set based on the setting instruction, and the target length can be flexibly set according to actual needs. The number of elements (i.e. the target length) performing dequeue operation on the first data queue each time can be the same or different.

[0050] In one or more possible embodiments, the first buffer unit and the buffer unit perform enqueue and dequeue operations in an asynchronous manner

[0051] Among them, the asynchronous execution strategy of enqueue and dequeue operations is determined, such as using multi-threading, event-driven or interrupt to realize asynchronous operation.

[0052] When there is data to be written into the buffer unit, the producer thread or task encapsulates the data into a digital code word sequence and calls the asynchronous enqueue interface.

[0053] The asynchronous enqueue interface puts the enqueue request into a pending queue or triggers an event / interrupt, and then returns immediately without waiting for the enqueue operation to complete.

[0054] A consumer thread or task (possibly a dedicated enqueue handling thread) is responsible for taking the enqueue request from the pending queue and performing the actual enqueue operation (adding data to the tail of the buffer unit).

[0055] When data needs to be read from the buffer unit, the consumer thread or task calls the asynchronous dequeue interface.

[0056] The asynchronous dequeue interface similarly puts the dequeue request into a pending queue or triggers an event / interrupt, and then returns immediately.

[0057] Another consumer thread or task (possibly a dedicated dequeue handling thread) takes the dequeue request from the pending queue and performs the actual dequeue operation (removing data from the head of the buffer unit).

[0058] To ensure data consistency and integrity, appropriate synchronization mechanisms need to be introduced when using the buffer unit.

[0059] For example, locks, semaphores, or atomic operations can be used to ensure that the state of the buffer unit is not modified simultaneously by multiple threads during enqueue and dequeue operations.

[0060] The synchronization mechanisms should be as efficient as possible to avoid becoming a performance bottleneck.

[0061] Error handling and boundary condition checking need special attention in asynchronous operations.

[0062] For example, when the buffer unit is full, new enqueue requests should be rejected or queued; when the buffer unit is empty, dequeue operations should return an error or wait for new data to arrive.

[0063] Inter-thread communication and cooperation also need to be considered to ensure proper handling in exceptional cases.

[0064] Asynchronous operations can generally improve system throughput and response speed, but may also increase system complexity and overhead.

[0065] Therefore, performance optimization and testing are needed when implementing asynchronous enqueue and dequeue operations to ensure that the system can meet the requirements while maintaining high efficiency and stability.

[0066] The electronic device provided by the embodiments of the present application includes but is not limited to a communication device, a terminal device, a computer device, etc. In addition to the LDPC decoding apparatus, the electronic device can further include a housing for accommodating various components, a display screen, an input device (for example, a keyboard, a mouse or a touch screen), etc.

[0067] The above-described embodiments do not constitute a limitation on the protection scope of the technical solutions. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described embodiments shall be included in the protection scope of the technical solutions.

Claims

1. An LDPC decoding device, comprising: The LDPC decoding device comprises: a demodulation unit, a first buffer unit, a second buffer unit, an LDPC decoder and a controller; an output end of the demodulation unit is connected with an input end of the first buffer unit, an output end of the first buffer unit is connected with an input end of the second buffer unit, and an output end of the second buffer unit is connected with the LDPC decoder; the controller is connected with a control end of the first buffer unit and a control end of the second buffer unit respectively; a first data queue is arranged in the first buffer unit, and a second data queue is arranged in the second buffer unit; the demodulation unit is configured to demodulate a radio frequency signal into a digital code word sequence; the controller is configured to read a first fixed length of the digital code word sequence from the demodulation unit, perform an enqueue operation on the read digital code word sequence according to a position of a tail element of the first data queue, determine a target length according to a decoding requirement, perform a dequeue operation on elements of the target length according to a position of a head element of the first data queue, perform an enqueue operation on the elements dequeued from the first data queue according to a position of a tail element of the second data queue, and perform a dequeue operation on elements of a second fixed length according to a position of a head element of the second data queue; the LDPC decoder is configured to perform a decoding operation on the elements dequeued from the second data queue.

2. The apparatus of claim 1, wherein, The second data queue is provided with a read pointer configured to indicate the position of the head element of the second data queue.

3. The apparatus of claim 1 or 2, wherein, The dequeue operation on the elements of the second fixed length according to the position of the head element of the second data queue comprises: detecting a current number of elements of the second data queue; if the current number of elements is equal to the second fixed length, selecting the elements of the second fixed length from the head element of the second data queue to perform the dequeue operation; if the current number of elements is less than the second fixed length, continuing to detect the number of elements of the second data queue.

4. The apparatus of claim 3, wherein, The enqueue operation on the read digital code word sequence according to the position of the tail element of the first data queue comprises: detecting a number of idle elements of the first data queue; if the number of idle elements is less than a length of the read digital code word sequence, discarding the read digital code word sequence; if the number of idle elements is greater than or equal to the length of the read digital code word sequence, inserting the read digital code word sequence after the tail element of the first data queue.

5. The apparatus of claim 1 or 2 or 4, wherein, The setting target length is set based on the setting.

6. The apparatus of claim 5, wherein, The first buffer unit and the second buffer unit perform the enqueue operation and the dequeue operation in an asynchronous manner.

7. The apparatus of claim 3, wherein, The first buffer unit and the second buffer unit are combined and arranged in the same chip.

8. An electronic device, comprising: The LDPC decoding device comprises any one of claims 1 to 7.

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