Electrical Test Module, Test Device and Test Method for Testing a Chip

Abstract

The present invention relates to an electrical test module, a test device and a test method for testing a chip. The electrical test module includes a contact array layer, a ground wire layer, at least two signal wire layers, a signal power supply layer, a driving power supply and a chip component layer which are stacked in sequence from bottom to top in the vertical direction; the electrical test module provides the following circuit: the contact is turned on only when signals are sent out simultaneously in the at least two signal wire layers, so as to measure the voltage between the contact and the gate probe. The present invention uses electrical scanning to replace mechanical displacement scanning to complete the gate cathode breakdown voltage test for up to tens of thousands of comb bars on the chip, and can screen and locate the failed cathode comb bars, thereby improving the test efficiency, simplifying the structure and reducing the cost.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices, and more particularly, to an electrical test module, a test device, and a test method for testing chips. Background Art

[0002] The working process of high-power power semiconductor devices such as gate turn-off thyristors (GTOs) and integrated gate-commutated thyristors (IGCTs) can be controlled through the gate circuit, and they are widely used in industries such as DC power transmission, locomotive traction, and metallurgy.

[0003] The GTO / GCT chip is a whole-wafer structure, and the active region is composed of a series of cathode comb units and a gate region formed by trenching. During the processing and packaging of such high-power chips, it is easy to occur that the gate-cathode characteristics of some units are abnormal, and insufficient reverse voltage withstand of any one comb may cause the device to burn out during operations such as turn-off and turn-on through gate control. The influence of a single comb on the overall parameters in the device does not exceed 0.1%. By screening and shielding the failed combs, the yield rate during device production can be greatly improved.

[0004] The traditional comb screening method is the dotting test method using an automated gate probe station. Taking a 6-inch chip as an example, the test time exceeds 100 minutes, and the equipment is expensive, significantly restricting the production capacity. The test devices in the prior art mainly use equipment with complex mechanical structures for testing.

[0005] For example, the Chinese patent with the publication number CN208207139U discloses a GCT chip gate / cathode blocking characteristic circular test bench, which can quickly achieve testing by setting up a three-axis displacement stage and a rotational displacement stage. However, the complex mechanical structure makes the cost of the equipment relatively high.

[0006] Again, for example, the Chinese patent with the publication number CN220509086U discloses a GCT chip cathode short-circuit test device and a GCT chip test equipment, which perform step-by-step testing through a multi-stage ring-shaped conductive structure and a ring-shaped sliding gate probe, greatly reducing the use of mechanical structures and being able to achieve testing relatively quickly. However, it still does not get rid of the use of mechanical structures, and multiple toolings need to be replaced multiple times for a single test, and the process is still relatively complex. Summary of the Invention

[0007] The present invention publicly provides an electrical test module for testing chips. The electrical test module uses electrical scanning to replace mechanical displacement scanning to complete the gate-cathode voltage withstand test of up to tens of thousands of combs on the chip, and can screen and locate the failed cathode combs, thereby improving the test efficiency, simplifying the structure, and reducing the cost.

[0008] According to one aspect of the present invention, there is provided an electrical test module for testing a chip, characterized in that the electrical test module includes a contact array layer, a ground wire layer, at least two signal wire layers, a signal power supply layer, a drive power supply, and a chip component layer stacked in sequence from bottom to top in the vertical direction; the contact array layer includes a plurality of contacts, and the contacts are arranged corresponding to the cathode comb bars of the chip so as to crimp the cathode comb bars of the chip when testing the chip; a third through hole is further provided on the electrical test module so that the gate probe of the test device can pass through the third through hole to pierce and connect to the gate of the chip when testing the chip; the electrical test module provides the following circuit: the contacts are turned on only when signals are simultaneously emitted in the at least two signal wire layers, so as to measure the voltage between the contacts and the gate probe.

[0009] Preferably, the ground wire layer is used for grounding, the at least two signal wire layers are used for emitting at least two signals, the signal power supply layer provides the voltage for emitting signals to the at least two signal wire layers, and the drive power supply and the chip component layer provide the working voltage of the circuit.

[0010] Preferably, the at least two signal wire layers are a first signal wire layer and a second signal wire layer, and the first signal wire layer emits signal A n , where n is a natural number, and A n marks the nth circle of cathode comb bars close to the center of the chip; the second signal wire layer emits signal B m , where m is a natural number, and B m marks the cathode comb bars in different radial directions of the chip; the first signal wire layer emits signal A n , and at the same time the second signal wire layer emits signal B m , so as to turn on the contacts on the cathode comb bars to be measured. At this time, the contacts on the cathode comb bars to be measured are marked as A n B m .

[0011] Preferably, the drive power supply and the chip component layer further include a MOS transistor, and the MOS transistor is electrically connected to the contacts when detecting the chip, and the gate probe is grounded.

[0012] Preferably, the drive power supply and the chip component layer further include a main control unit, and the main control unit stores control logic so as to control the at least two signal wire layers to generate signals simultaneously and realize that only one contact is turned on at each moment.

[0013] Preferably, the contacts and the cathode comb bars are in one-to-one correspondence, or multiple contacts correspond to one cathode comb bar.

[0014] Preferably, the center or other parts of the bottom of the electrical test module have a cross-shaped or other-shaped marking through hole so as to be aligned with the alignment mark on the chip.

[0015] According to a second aspect of the present invention, there is provided a test device for testing a chip, characterized in that the test device includes the above-mentioned electrical test module.

[0016] Preferably, the test device further includes: a frame; a fixture module and an analysis module; the fixture module is arranged on the frame, the electrical test module is arranged on the fixture module, and the analysis module is electrically connected to the electrical test module.

[0017] Preferably, the frame includes a device base, a column fixed at the lower end on the device base, and a fixing frame fixed on the upper part of the column. A gate probe and a first through hole for the gate probe to pass downward through the fixing frame are provided on the fixing frame.

[0018] Preferably, the fixture module includes a fixed seat, a rotatable seat, and a fixture; wherein, the fixed seat is immovably fixed in the center of the device base; the rotatable seat is rotatably fixed on the fixed seat; the fixture is slidably arranged on the column in the vertical direction so as to fix the electrical test module on the fixture; the fixture is provided with a second through hole so that the gate probe passing through the first through hole then passes through the second through hole.

[0019] Preferably, the analysis module includes a host computer and graphical control software stored in the host computer; the host computer can provide waveform output of control signal lines to the contacts so that the at least two signal line layers emit signals simultaneously; the graphical control software reads the actual level or current of the contacts, compares with a preset value, and gives a comparison result.

[0020] According to a third aspect of the present invention, there is provided a test method for testing a chip using the above-mentioned test device. The test method includes the following steps: setting alignment marks at the center or other parts of the chip; placing the cathode side of the chip upward on the rotatable seat, rotating the rotatable seat, and completing alignment through the marking through hole of the electrical test module and the alignment marks on the chip, locking the rotatable seat, pressing down the electrical test module and locking it so that the contacts are pressed against the cathode comb bars; making the gate probe pierce the gate ring of the chip, connecting the signal lines and power lines of the electrical test module, connecting the gate ground wire and the ground wire of the signal power supply to ensure common ground; controlling signal scanning through the host computer, reading the comb bar current or comb bar voltage, comparing with a preset value, and graphically marking the failure points on the host computer software; disconnecting the electrical connection, raising the electrical test module and then removing the chip, loosening the rotatable seat, and the test is completed.

[0021] Compared with the prior art, the test device for a chip according to the present invention has the following beneficial effects:

[0022] (1) Greatly reduces the use of mechanical displacement tables, reduces the complexity of the device, and improves reliability.

[0023] (2) The testing process only includes the process of aligning the upper chip. The testing is fully automatically executed by software, reducing the complexity of operation, lowering the requirements for the experience and skills of testing operators, and improving the process stability.

[0024] (3) The electrical scanning speed is much higher than that of mechanical scanning, and the testing time can be compressed within 5 minutes, greatly improving the testing efficiency.

[0025] (4) The electrical testing module using the dense contact matrix of the present invention can also test chips with various comb bar distributions, without the need to customize tooling for each chip layout, greatly reducing the R & D cost.

[0026] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will become apparent from the specification, or will be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the drawings. Brief Description of the Drawings

[0027] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0028] Figure 1 Schematic diagram of a testing device for semiconductor power devices according to an embodiment of the present invention;

[0029] Figure 2A Schematic bottom view of the electrical testing module of the testing device according to an embodiment of the present invention;

[0030] Figure 2B For Figure 2A Enlarged view of circle A in

[0031] Figure 3 Schematic cross-sectional view of the electrical testing module according to an embodiment of the present invention;

[0032] Figure 4 Circuit diagram of a single contact unit of the electrical testing module according to an embodiment of the present invention;

[0033] Figure 5 Schematic electrical scanning logic diagram of the electrical testing module according to an embodiment of the present invention;

[0034] Figure 6 Schematically shows the coordinate positioning of the contacts of the measured cathode comb bar according to an embodiment of the present invention.

[0035] List of reference numerals:

[0036] 1. Device base; 2. Fixed seat; 3. Rotatable seat; 4. Rotatable seat fixing screw; 5. Electrical test module; 6. Alignment hole; 7. First through hole; 8. Liftable microscope barrel; 9. Fixing bracket; 10. Column; 11. Contact; 12. Third through hole; 13. Marking through hole; 14. Contact array layer, 15. Ground wire layer, 16. First signal wire layer, 17. Second signal wire layer, 18. Signal power layer, 19. Drive power and surface mount component layer, 20. Fixture; 21. Column limit hole; 22. Lift screw; 23. Second through hole. Detailed implementation manner

[0037] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in detail in combination with specific embodiments and with reference to the accompanying drawings.

[0038] To make the objectives, technical solutions and advantages of this disclosure clearer and more understandable, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the technical field to understand the fact that the manner and content can be transformed into various forms without departing from the gist and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following implementation manners. Without conflict, the embodiments in this disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0039] In the description of this application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to this application.

[0040] In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include at least one such feature. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0041] In this application, unless otherwise clearly specified or limited, terms such as "installed", "connected", "linked", "fixed", etc. shall be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In this application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first feature and the second feature are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0043] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example" or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. In order to achieve the above purposes according to the embodiments of the present invention, the present invention adopts the following technical solutions.

[0044] According to an embodiment of the present invention, as Figure 1 shown, a test device for testing a chip includes a frame, an electrical test module 5, an analysis module (not shown), and a fixture module. The fixture module is arranged on the frame, the electrical test module 5 is arranged on the fixture module, and the analysis module is electrically connected to the electrical test module.

[0045] Specifically, as Figure 1 shown, the frame includes a device base 1, a column 10 fixedly connected to the device base 1 at the lower end, and a fixing frame 9 fixedly connected to the upper part of the column 10. According to an embodiment of the present invention, as Figure 1As shown, a gate probe (not shown) and a first through hole 7 for allowing the gate probe to pass downward through the fixing bracket 9 are provided on the fixing bracket 9.

[0046] As Figure 1 shown, the fixture module includes a fixed base 2, a rotatable base 3, and a fixture 20. Preferably, the column 10 passes through the column limit hole 21 on the fixture 20. The fixed base 2 is fixedly and non-rotatably fixed at the center of the device base 1. The rotatable base 3 is rotatably fixed on the fixed base 2 and can be fixed at any angle. Preferably, the rotatable base 3 is threadedly connected to the fixed base 2. Exemplarily, as Figure 1 shown, with the help of the rotatable base fixing screw 4, the rotatable base 3 is fixed on the fixed base 2. The device base 1, the fixed base 2, and the rotatable base 3 are arranged one by one from bottom to top in the vertical direction. The chip to be tested is fixed on the rotatable base 3, preferably positioned and fixed through a card slot (not shown) on the rotatable base 3 so that the center of the chip is aligned with the center of the rotatable base 3. Further, an edge pressing piece (not shown) may also be provided on the rotatable base 3 to further fix the chip. Preferably, the electrical test module 5, the fixed base 2, the rotatable base 3, and the chip are all circular in a top view and the centers of these four are concentric. The fixture 20 is slidably arranged on the column 10 in the vertical direction. The electrical test module 5 is fixed on the fixture 20 so as to move up and down with the fixture 20. In addition, as Figure 1 shown, the fixture 20 is provided with a second through hole 23 so that the gate probe passing through the first through hole 7 then passes through the second through hole 23.

[0047] In addition, a vertically movable microscope barrel 8 is also provided on the fixing bracket 9 to observe whether the electrical test module 5 is aligned with the chip. Specifically, the vertically movable microscope barrel 8 is arranged to face the center of the electrical test module 5 so as to observe the electrical test module 5 through the alignment hole 6 provided on the fixture 20. Preferably, the electrical test module 5 is also provided with the alignment hole 6. Preferably, with the help of the lifting screw 22, the vertically movable microscope barrel 8 performs a lifting movement.

[0048] According to an embodiment of the present invention, as Figure 2A and Figure 3 shown, the electrical test module 5 that is circular in a top view includes a contact array layer 14, a ground wire layer 15, at least two signal wire layers, a signal power supply layer 18, a drive power supply, and a patch element layer 19 that are stacked in sequence from bottom to top in the vertical direction. A substrate is between the above layers, and the substrate is usually made of an insulating resin material, etc. The electrical test module 5 is provided with a third through hole 12 so that when testing the chip, the gate probe of the testing device is tied to the gate of the chip. The electrical test module 5 provides a circuit for measuring the voltage between the contact 11 of the contact array layer 14 and the gate probe when signals are simultaneously emitted in the at least two signal wire layers.

[0049] AsFigure 2A and Figure 2B As shown in Figure 2B , the electrical test module 5 is further provided with a marking via hole 13. Preferably, the marking via hole 13 can be arranged at the center of the electrical test module 5. Of course, it can also be arranged at other positions. Preferably, the marking via hole 13 is arranged in a cross shape or other shapes, such as Figure 2B As shown in Figure 2B , so as to align with the alignment marks on the chip, thereby realizing the precise alignment and positioning of the electrical test module 5 and the chip. For example, by rotating the rotatable seat 3, the chip alignment marks are aligned with the marking via hole 13 on the electrical test module 5. In addition, the electrical test module 5 is further provided with a third via hole 12 corresponding to the position of the gate ring of the chip, so that the gate probe passing through the second via hole 23 can continue to pass through the third via hole 12 to contact the gate ring of the chip.

[0050] such as Figure 3 As shown in Figure 3 , the contact array layer 14 includes a plurality of contacts 11. The contacts 11 are located at the lowermost side of the electrical test module 5 and are opposite to the cathode side of the chip to be tested. The contacts 11 are arranged corresponding to the comb bars of the chip, so as to crimp the cathode comb bars of the chip when testing the chip. For example, the contact 11 array is a dot matrix. Preferably, for example, the dot diameter is 30 - 50μm and the period is 60 - 100μm, so as to be able to perform gate cathode characteristic tests on GTO / GCT chips with various types of comb bar arrangements. As Figure 2A As shown in Figure 2A , the contacts 11 are arranged in a ring shape. The size of the contacts 11 is basically the same as the size of the comb bars of the chip. Preferably, it is smaller than the size of the comb bar gaps of the chip. The contacts 11 are arranged to correspond one by one to the comb bars; it can also be that multiple contacts 11 correspond to one comb bar, but one contact 11 cannot contact multiple comb bars. The material of the contacts 11 has certain strength and wear resistance, and can be metals such as titanium, tungsten, nickel, gold, copper or their alloys.

[0051] such as Figure 4 As shown in Figure 4 , each contact 11 is controlled by two or more signal lines. Only when all the signal lines give out on signals at the same time, the contact 11 is connected to the test power supply. The coordinate positioning of the currently on contact 11 can be realized through the signal lines.

[0052] According to an embodiment of the present invention, in the electrical test module 5, the ground wire layer 15 is used for grounding, the at least two signal line layers are used for emitting at least two signals, the signal power supply layer 18 provides the voltage for emitting signals to the at least two signal line layers, and the drive power supply and the chip component layer 19 provide the working voltage of the circuit. See Figure 3 and Figure 4 .

[0053] The signal lines in at least two signal line layers can be two or more groups, and each contact 11 is connected to two or more signal lines. The signal lines can be distributed in the ways of rows, columns, rings, etc. The signal lines corresponding to each row, column, and ring are controlled by the main control, and the coordinates of the contact 11 are identified by recognizing the signal line intersection points (which will be further described below). Preferably, as Figure 3 shown, at least two signal line layers are the first signal line layer 16 and the second signal line layer 17. In the electrical test module 5, the contact 11 is pressed against the chip. Specifically, it contacts the cathode comb of the chip; the ground line layer 15 is grounded; the first signal line layer 16 emits signal A n ; the second signal line layer 17 emits signal B m ; the signal power supply layer 18 provides the voltage Vcc for emitting the signal; the drive power supply and the surface mount component layer 19 provide the operating voltage Vdd of the circuit. Preferably, the main control and the MOS transistor Q1, etc. are also arranged in the drive power supply and the surface mount component layer 19.

[0054] Specifically, for signal A n and signal B m , both n and m are natural numbers. A n marks the nth circle of cathode combs close to the center of the chip; B m marks the cathode combs in different radial directions of the chip. Specifically, the first signal line layer 16 emits signal A n , and at the same time the second signal line layer 17 emits signal B m to turn on the contact 11. Refer to Figure 4 . When the contact 11 is turned on, the gate probe is connected to the gate of the chip, that is, it is connected to the circuit provided by the electrical test module 5. At this time, the contact 11 on the measured cathode comb is marked as A n B m . For example, the first signal line layer 16 emits signal A 5 , and at the same time the second signal line layer 17 emits signal B 1 . Refer to Figure 4 . Since signal A 5 and signal B 1 are turned on simultaneously, the MOS transistor Q1 is turned on, the gate probe is grounded, and the voltage or current between the contact 11 and the gate can be measured. The measured voltage or current is compared with the predetermined value stored in the analysis module. For example, if it is lower than the predetermined value, the comb is invalid. According to the control logic in the main control or the analysis module, refer to Figure 6 , the fifth circle of cathode combs close to the center of the chip in the figure is marked as A 5 , and the combs in the radial direction from the center of the chip to the left are marked as B 1 . Therefore, the contact 11 of the invalid comb in the embodiment can be located by coordinates, that is, A 5 B 1 .

[0055] As Figure 5 shown, through the timing scanning logic stored in the main control, the turn-on of any two contacts 11 will not occur simultaneously, and it can be ensured that only one contact 11 is turned on at each moment, guaranteeing that false alarms will not occur during the test process. Thus, through the scanning logic of the embodiments of the present application, in the face of thousands of contacts 11, there is no need for the main control to have interfaces for thousands of ports, reducing the number of required main control I / O ports. Figure 5 shows the timing scanning logic, where i, j, k are the values of "n" in A n and l, m, n are the values of "m" in B m

[0056] According to an embodiment of the present invention, the analysis module includes: a host computer and graphical control software stored in the host computer. The analysis module can output waveforms of the control signal lines of the contact 11 array through, for example, the main control component and the host computer software, ensuring that only one row (column, ring) of signal lines gives a turn-on signal at the same moment, and the trigger time interval is 20 - 1000 μs. The host computer software of the analysis module can read the actual level or current of the contacts 11 and compare it with an adjustable preset value to give a comparison result.

[0057] Alternatively, the main control chip can also have storage capabilities to read and save the leakage current values and actual voltage values of each comb bar, more precisely determining the differences between the comb bars.

[0058] Alternatively, the control logic can also be implemented through the host computer.

[0059] The test device of the present invention is not only applicable to the illustrated GTO / GCT, but also applicable to the testing of high-power device chips with similar gate-cathode leakage testing requirements. The substrate material is not limited to silicon, and can also be a third-generation semiconductor material such as silicon carbide or gallium nitride. The case where the gate contact ring is in the center of the chip is shown in the drawings, and the test device of the present invention is also applicable to the case where the gate ring is at the edge or there are double gate rings.

[0060] Exemplarily, the present invention provides a test method for GTO / GCT chips with the gate ring located in the center of the chip. Taking a silicon substrate as an example, the structure of the electrical testing module 5 and the host computer software are adjusted accordingly according to the substrate material and the chip structure.

[0061] The chip test method according to the present invention is described as follows:

[0062] Wafer layout design and processing. The electrical structure of the wafer main body can be designed with reference to the well-known techniques in the art. Preferably, alignment marks are provided in the non-working area at the center (or other parts, such as the edge), preferably with a size of 100 μm - 1 mm, facilitating the alignment of the wafer with the electrical testing module 5. ​

[0063] Manual wafer loading and alignment. Place the cathode side of the chip upward on the rotatable base 3, align the center through the card slot and press it tightly with the edge pressing piece; lower the electrical test module 5, but do not press it down, rotate the rotatable base 3 to complete the alignment through the marked through hole 13 of the electrical test module 5 and the alignment mark on the chip, lock the rotatable base 3, lower the electrical test module 5 and lock it.

[0064] Gate probe needle insertion and connection of other electrical and signal lines. Press the gate probe down through the third through hole 12 reserved by the electrical test module 5 to the cathode comb bar of the chip to ensure good contact; connect the signal line and power line of the electrical test module 5, connect the gate ground wire and the ground wire of the signal power supply to ensure good common grounding.

[0065] Gate cathode withstand voltage test. Complete the electrical test by controlling the signal scanning through the host computer. Read the comb bar current or comb bar voltage, compare it with the preset value, and graphically mark the failure point on the host computer software. The preset value is the current or voltage value qualified for the comb bar. The circuit of the gate cathode withstand voltage test and the principle of contact point positioning are as described in the above reference Figure 4 and Figure 5 described, and will not be elaborated here.

[0066] Chip removal. Disconnect the electrical connection, remove the chip after raising the electrical test module 5, loosen the rotatable base 3, and the test is completed.

[0067] The specific embodiments described above have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electrical test module (5) for testing a chip, characterized in that: The electrical test module (5) comprises a contact array layer (14), a ground layer (15), at least two signal line layers, a signal power layer (18), a drive power supply and a patch component layer (19) which are stacked in sequence from bottom to top in a vertical direction; The contact array layer (14) comprises a plurality of contacts (11), wherein the contacts (11) are arranged corresponding to the cathode comb strips of the chip so as to press-connect the cathode comb strips of the chip when testing the chip; The electrical test module (5) is also provided with a third through hole (12), so that when testing the chip, a gate probe of a test device can pass through the third through hole (12) and connect to the gate of the chip; The electrical test module (5) provides the following circuit: the contact (11) is opened only when signals are simultaneously sent out in the at least two signal line layers, so as to measure the voltage between the contact (11) and the gate probe; Wherein, the at least two signal line layers are a first signal line layer (16) and a second signal line layer (17), The first signal line layer (16) transmits signal A n , n is a natural number, A n Mark the nth circle of cathode comb bars close to the center of the chip; The second signal line layer (17) transmits signal B m , m is a natural number, B m Mark the cathode comb strips in different radial directions of the chip; The first signal line layer (16) sends a signal A n At the same time, the second signal line layer (17) sends a signal B m , so as to open the contact (11) on the cathode comb bar to be measured. At this time, the contact (11) on the cathode comb bar to be measured is marked as A n B m ; The driving power supply and patch component layer (19) further includes a MOS tube. When the chip is detected, the MOS tube is electrically connected to the contact point, and the gate probe is grounded. The driving power supply and patch component layer (19) further includes a main control, which stores control logic so as to control the at least two signal line layers to generate signals simultaneously and realize that only one contact (11) is turned on at any time.

2. The electrical test module (5) according to claim 1, characterized in that: The ground line layer (15) is used for grounding, the at least two signal line layers are used for transmitting at least two signals, the signal power supply layer (18) provides the at least two signal line layers with a voltage for transmitting signals, and the driving power supply and patch component layer (19) provide a circuit operating voltage.

3. The electrical test module (5) according to claim 1, characterized in that: The contact points (11) correspond to the cathode comb bars one by one, or a plurality of contact points (11) correspond to one cathode comb bar.

4. The electrical test module (5) according to claim 1, characterized in that: The center or other part of the bottom of the electrical test module (5) has a cross-shaped or other shaped marking through hole (13) so as to be aligned with the alignment mark on the chip.

5. A testing device for testing a chip, characterized in that: The testing device comprises the electrical testing module (5) according to any one of claims 1 to 4.

6. The testing device according to claim 5, characterized in that: The testing device further comprises: a frame; a fixture module and an analysis module; The fixture module is arranged on the frame, the electrical test module (5) is arranged on the fixture module, and the analysis module is electrically connected to the electrical test module.

7. The testing device according to claim 6, characterized in that: The frame comprises a device base (1), a column (10) whose lower end is fixed to the device base (1), and a fixing frame (9) fixed to the upper part of the column (10). A gate probe and a first through hole (7) for allowing the gate probe to pass downward through the fixing frame (9) are provided on the fixing frame (9).

8. The testing device according to claim 7, characterized in that: The clamp module comprises a fixed seat (2), a rotatable seat (3), and a clamp (20); The fixed seat (2) is fixed non-rotatably at the center of the device base (1); the rotatable seat (3) is rotatably fixed on the fixed seat (2); the clamp (20) is slidably arranged on the column (10) along the vertical direction so as to fix the electrical test module (5) on the clamp (20); The fixture (20) is provided with a second through hole (23), so that the gate probe passing through the first through hole (7) can then pass through the second through hole (23).

9. The testing device according to claim 7, characterized in that: The analysis module includes a host computer and graphical control software stored in the host computer; The upper computer can provide a waveform output of a control signal line to the contact (11), so that the at least two signal line layers send out signals simultaneously; The graphical control software reads the actual electrical level or current of the contact (11), compares it with the preset value, and gives a comparison result.

10. A testing method for testing a chip using the testing device according to claim 9, the testing method comprising the following steps: Providing an alignment mark at the center or other part of the chip; Place the cathode side of the chip upward on the rotatable seat (3), rotate the rotatable seat (3), align the marked through hole (13) of the electrical test module (5) and the alignment mark on the chip, lock the rotatable seat (3), press down the electrical test module (5) and lock it so that the contact (11) is crimped to the cathode comb strip; Connect the gate probe to the gate ring of the chip, connect the signal line and power line of the electrical test module (5), and connect the gate ground line and the ground line of the signal power supply to ensure a common ground; Through the host computer control signal scanning, the comb current or comb voltage is read, compared with the preset value, and the failure point is graphically marked on the host computer software; Disconnect the electrical connection, raise the electrical test module (5), remove the chip, and release the rotatable seat (3), and the test is completed.

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