A machine learning-based collaborative optimization method for chip DFN packaging and process

Abstract

The present invention relates to the technical field of chip packaging processes and discloses a collaborative optimization method for chip DFN packaging and processes based on machine learning. The method determines quality indicators of solder paste type, PAD solder layer thickness, chip lower surface solder layer thickness, and chip material type through a percentage-based weighted evaluation method of a Taguchi orthogonal test and a range analysis method of a signal-to-noise ratio. The range value R of each factor is sorted and analyzed to obtain a comprehensive score. The optimal DFN packaging parameter combination of the Taguchi method is further optimized through random forest machine learning and grid search. The reflow soldering temperature curve is also optimized to select the optimal reflow soldering temperature curve. The method solves a series of problems caused by unreasonable material combination or structural design in existing chip DFN packaging. The method greatly improves optimization efficiency and also improves the accuracy of Taguchi method optimization parameters to a certain extent.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to a chip DFN packaging and process collaborative optimization method based on machine learning. Background Art

[0002] In chip DFN packaging, improper material combinations or structural design can lead to structural warping or stress concentration, directly affecting the coplanarity and reliability of the package, leading to chip breakage and solder layer delamination. Furthermore, the rationality of the reflow process settings also directly affects the reliability of the packaged product, thereby affecting product performance and service life. Therefore, collaborative optimization of chip package structural parameters and reflow process parameters can effectively improve package reliability and reduce problems such as solder layer delamination, stress concentration, and chip warpage in the package structure. The existing Taguchi-based optimization method may not list the optimal parameter combinations, and the enumeration method is not very efficient in selecting the optimal parameter combination.

[0003] Faced with fierce competition in the domestic and international chip industry, the requirements for reducing processing cycles and production costs are becoming increasingly stringent. Therefore, it is necessary and indispensable to be able to obtain a synergistically optimized combination of packaging structure and process parameters while improving optimization efficiency in the early stages of new product development. This not only significantly reduces production costs but also avoids potential factors that may affect reliability issues in advance. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a chip DFN packaging and process collaborative optimization method based on machine learning.

[0005] The objective of the present invention is achieved through the following technical solution: a chip DFN packaging and process collaborative optimization method based on machine learning, the method comprising the following steps:

[0006] Step S1: First, determine the chip DFN package structure parameters, including solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type, divide the chip DFN package structure parameters into different level combinations and design a test table according to the Taguchi orthogonal method;

[0007] Step S2, establishing a finite element model of the DFN package product, setting the reflow temperature curve parameters for the finite element model, simulating to obtain various quality indicators, and calculating the signal-to-noise ratio of each quality indicator. The quality indicators are set as the maximum stress value of the chip, the chip warpage, and the stress and warpage values ​​of the solder layer structure on the lower surface of the chip;

[0008] Step S3, using the signal-to-noise ratio range analysis method to obtain the weight of each quality indicator;

[0009] Step S4, based on the weight of each quality indicator, a percentage-based weighted evaluation method is used to determine the comprehensive score of solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type;

[0010] Step S5: Using the combination parameters obtained by the Taguchi method as the input of the random forest machine learning method, and the comprehensive score as the output of the random forest machine learning method to train the optimal model, and further screening the combination parameters using grid search to determine the optimal chip DFN package structure parameters;

[0011] Step S6: Based on the chip DFN package structure parameters selected in step S5, reflow soldering temperature curve parameters are set, where the reflow soldering process parameters include preheating temperature E, heating temperature F, peak temperature G, holding time H, and cooling rate I;

[0012] Step S7, using the PB method to perform a reflow soldering temperature curve parameter screening test design, and combining the chip DFN package structure parameters screened in step S5 to simulate and obtain various quality indicators;

[0013] Step S8, based on the quality indicators obtained in step S7, determine the optimal reflow soldering temperature curve parameters through comprehensive scoring, and then determine the chip DFN package structure parameters and reflow soldering temperature curve parameters;

[0014] Step S9, modifying the finite element model of the chip DFN package product, simulating and obtaining the optimized quality indicators, and verifying and obtaining the optimal chip DFN package structure parameters and reflow soldering temperature curve parameters.

[0015] Furthermore, in step S1, the solder paste types are selected from Sn-3.0Ag-0.5Cu, Sn-1.0Ag-0.5Cu, and nano-silver solder paste; the PAD solder layer thickness is selected from 0.025mm, 0.035mm, and 0.045mm; the chip bottom surface solder layer thickness is selected from 0.02mm, 0.025mm, and 0.03mm; and the chip material types are selected from Si, SiC, and GaN.

[0016] Furthermore, in step S2, the reflow soldering temperature curve parameters are set as follows: heating and soaking to 150°C from 0s to 40s, preheating and soaking from 40s to 140s, first heating to the critical value of the solder melting point from 140s to 146s, then heating to 260°C from 146s to 160s, starting reflow, and then cooling to 25°C at a rate of less than or equal to 6°C / s from 170s to 210s.

[0017] Furthermore, in step S2, the signal-to-noise ratio is analyzed based on the Wang Xiao characteristic, and the calculation formula of the Wang Xiao characteristic is as follows:

[0018]

[0019] where y i is the actual calculated value or measured quantity of the ith experimental result, and n is the total number of experimental results.

[0020] Furthermore, in step S4, the formula of the percentage-based weighted evaluation method is:

[0021] Among them, i is the test number, x k is the kth quality index weight; Y ki is the quality index data result of the kth test in the i-th group of tests, W i is the comprehensive score of the i-th group of tests, and q is the total number of quality indicators.

[0022] Furthermore, in step S5, the combination parameters obtained by the Taguchi method are used as input to the random forest machine learning method, and the comprehensive score is used as the output of the random forest machine learning method to train the optimal model, and the combination parameters are further screened by grid search to determine the optimal chip DFN package structure parameters, specifically including:

[0023] Step S5.1: The data obtained by the Taguchi method is used as sample data and divided into a training set and a test set, with the ratio of the training set to the test set being 7:2;

[0024] Step S5.2: randomly extract n samples from the training set to form a sample subset and generate a decision tree. At each generated node m, randomly select multiple features X j , that is, combining parameters without repetition, and then using them to divide the sample set until the best division feature is found;

[0025] Step S5.3 and step S5.2 are repeated k times, where k is the number of decision trees in the random forest.

[0026] Step S5.4, applying the test set to perform prediction evaluation on the random forest model, and using the average value to determine the prediction result;

[0027] In step S5.5, grid search is used to evaluate and cross-validate each set of parameters, and the optimal parameter combination is finally obtained.

[0028] Furthermore, the reflow soldering temperature curve parameters are set as preheating temperature range: 190-200°C; heating rate range: 2-3°C / s; peak temperature range: 250-260°C; holding time range: 30-40s; cooling rate range: 4-6°C / s.

[0029] The present invention has the following beneficial effects: The influence of various solder paste types, solder layer thicknesses at various locations, and chip material types on quality indicators is determined through Taguchi orthogonal test percentage-based weighted range analysis and signal-to-noise ratio range analysis. The range values ​​(R) of each factor are ranked and analyzed to obtain a comprehensive score. The optimal DFN packaging parameter combination of the Taguchi method is further optimized through random forest machine learning and grid search. Furthermore, the reflow process parameters are optimized to select the optimal reflow soldering process curve. This solves the existing problem of irrational material combinations or structural designs in chip DFN packaging, which can lead to structural warping or stress concentration, directly affecting the coplanarity and reliability of the package, causing chip breakage and solder layer delamination. The combined method reduces the time required for "semi-intelligent" structural optimization from several days to several hours or even minutes, significantly improving optimization efficiency and, to a certain extent, enhancing the accuracy of the Taguchi method's optimized parameters. Machine learning is then used to find the optimal parameter combination from parameter combinations not listed in the Taguchi method.

[0030] Analyze the structural parameter simulation results to obtain the optimal structure and process parameter combination of DFN packaging, improve packaging reliability, reduce trial and error costs, and meet the quality requirements of packaging products. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the process of the present invention;

[0032] Figure 2 This is a structural framework diagram of a DFN package product according to an embodiment of the present invention;

[0033] Figure 3 A side view of the structural frame of a DFN package product according to an embodiment of the present invention;

[0034] Figure 4 This is a diagram explaining the reflow soldering temperature curve parameters;

[0035] Figure 5 is the main effect plot of signal-to-noise ratio;

[0036] Figure 6 Pareto chart of the standardized effect of the comprehensive score of reflow profile parameters;

[0037] Figure 7 This is a comparison chart of the optimal solder paste parameter combination screened by the Taguchi method and the optimal parameter combination screened by the random forest method;

[0038] Figure 8 This is the logic diagram of the random forest algorithm of the present invention;

[0039] Figure 9 The following is a comparison chart of the results before and after optimization of the embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the present invention easier to understand, the present invention is further described below with reference to specific embodiments and drawings, which do not limit the present invention in any way. These embodiments and drawings are only used to illustrate the present invention and are not used to limit the scope of the present invention. Without departing from the technical solution of the present invention, any changes or modifications made to the present invention that can be easily implemented by ordinary technicians in this field will fall within the scope of the claims of the present invention.

[0041] The DFN package product structure of this embodiment includes: chip 1, solder paste 2 on the lower surface of the chip, PAD solder paste 3, Clip bracket 4, solder paste 5 at the connection between Clip bracket 4 and pin 6-2, and Clip pin 6-1.

[0042] A chip DFN packaging and process collaborative optimization method based on machine learning, such as Figure 1-3 As shown, the following steps are included:

[0043] S1 determines the chip DFN package structure parameters and selects the solder paste types required for the orthogonal test. The solder paste types include Sn-3.0Ag-0.5Cu, Sn-1.0Ag-0.5Cu, and nanosilver solder paste. PAD solder layer thickness: 0.025mm, 0.035mm, 0.045mm; chip bottom surface solder layer thickness: 0.02mm, 0.025mm, 0.03mm; chip material types: Si, SiC, GaN. Based on the actual production engineering sample data of the enterprise, the various plastic encapsulation process parameters are divided into different level combinations, as shown in Table 1.

[0044] The Taguchi method was used to design the experimental table, and the selected factors and their respective level values ​​were input into the software Minitab for experimental design.

[0045] Table 1 Experimental factors and levels

[0046]

[0047] S2 designed a Taguchi orthogonal experiment and used Solidworks modeling software to model the finite element model. The reflow soldering temperature curve parameters were set as follows: heating and soaking to 150℃ from 0s to 40s, preheating and soaking at 190℃ from 40s to 140s, first heating to the critical value of the solder melting point from 140s to 146s, then heating to 260℃ from 146s to 160s to start reflow, and then cooling to 25℃ at a maximum rate of 6℃ / s from 170s to 210s. The established DFN package product finite element model was imported into ANSYS finite element software for simulation. The quality indicators were obtained through simulation. The quality indicators were set as the maximum stress value of the chip, the chip warpage, and the stress and warpage value of the solder layer structure on the lower surface of the chip. The signal-to-noise ratio of each quality indicator was calculated and statistically recorded in the test table, as shown in Table 2.

[0048] Table 2 shows the Taguchi orthogonal test results after analysis and statistics. Columns C5-C8 and C9-C12 in Table 2 output the orthogonal test results. The reflow process is a transient process, and the above results are based on the maximum transient value during the reflow process. This value is also the value at which DFN package products are most susceptible to failure, and this is why this is analyzed.

[0049] Table 2 Taguchi orthogonal test table

[0050]

[0051]

[0052] Table 2 Taguchi orthogonal test table (continued)

[0053]

[0054] The reliability of chip packaging products can be measured by the signal-to-noise ratio, which can truly reflect the impact of solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type on quality indicator data. The signal-to-noise ratio can be analyzed based on three characteristics: visible, large, and small. The stress value and warpage of both targets are small characteristics.

[0055] The calculation formula of the low-voltage characteristic is as follows:

[0056] where y i is the actual calculated value or measured quantity of the ith experimental result, and n is the total number of experimental results;

[0057] S3, because the influence of various factors on product quality indicators varies, requires a multi-objective comprehensive evaluation through the range analysis method of the signal-to-noise ratio, and a percentage weighting is performed according to the calculated weight ratio;

[0058] As shown in Tables 3-6, the average signal-to-noise ratio responses of each quality indicator are obtained from the simulation results analysis. The weight R value of each solder paste parameter on the quality indicator is listed through range analysis. The larger the R value, the greater the degree of influence.

[0059] Table 3 shows the range analysis of the maximum stress value of the chip

[0060]

[0061] Table 4 shows the range analysis of the maximum chip warpage

[0062]

[0063]

[0064] Table 5 shows the range analysis of the maximum stress value of the solder layer structure on the bottom surface of the chip.

[0065]

[0066] Table 6 shows the range analysis of the maximum warpage value of the solder layer structure on the bottom surface of the chip.

[0067]

[0068] Since each factor has different effects on the quality indicators of the product, it is necessary to achieve a comprehensive evaluation of multiple objectives through comprehensive scoring. The weight of each quality indicator is determined by summing the mean of the signal-to-noise ratio. As shown in Table 7;

[0069] Table 7 Weights of various quality indicators

[0070]

[0071] S4 then uses a percentage-based weighting to determine the ranking of the comprehensive impact of solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type. The percentage-based weighted evaluation formula is: Among them, i is the test number, x k is the kth quality index weight; Y ki is the quality index data result of the kth test in the i-th group of tests, W i is the comprehensive score of the i-th group test, and q is the total number of quality indicators. The calculated comprehensive scores are summarized in Table 8.

[0072] Table 8 Taguchi orthogonal test table

[0073]

[0074]

[0075] S5 uses the combination parameters derived from the Taguchi method as the input of the random forest machine learning method, and the comprehensive score as the output of the random forest machine learning method to train the optimal model. It then uses grid search to further screen the combination parameters and determine the optimal chip DFN package structure parameters.

[0076] The parameter combination result data set obtained by the Taguchi method is used as sample data, and then the data set is divided into training set and test set with a ratio of 7:2;

[0077] Randomly extract n samples from the training set to form a sample subset and generate a decision tree. At each generated node m, randomly select multiple features X j(i.e., the ABCD combination parameters of the Taguchi method), where j is the number of randomly selected input features, and j is less than or equal to the number of input features (the number of input features of a single set of data), without repetition. Then use them to partition the sample set until the optimal partitioning feature is found; this step is repeated k times, where k is the number of decision trees in the random forest;

[0078] Use the trained random forest to predict the test sample and use the average value to determine the prediction result. The formula of the simple average method is: Where k is the number of random forest decision trees, h i (x) is the numerical output result, i.e. the comprehensive score.

[0079] Data evaluation and cross-validation were performed in the trained random forest model using the grid search method, and the optimal structural parameter combination was finally selected as A2B3C3D1.

[0080] S6 uses the package structure parameter combination determined in step S5 as the simulation analysis condition for determining the reflow process parameters in the subsequent step, and selects the reflow process parameters, including preheating temperature E, heating rate F, peak temperature G, holding time H, and cooling rate I, such as Figure 4 As shown in Table 9, the horizontal range of reflow soldering process parameters is determined according to the IPC / JEDEC J-STD-020C lead-free reflow temperature curve parameter range.

[0081] Table 9 Reflow process parameter value range

[0082]

[0083] S7 designed a test table using the PB method, as shown in Table 10. The package finite element model with the modified optimal structural parameter combination was imported into the simulation and statistically recorded in the test table. The optimal combination of reflow process parameters was determined through comprehensive scoring.

[0084] Table 10 is the PB design test table

[0085]

[0086]

[0087] The two chip quality indicators in Table 10 were weighted to 50% and 50% of their respective proportions, respectively, to calculate a comprehensive score, which is recorded in column C8 of Table 10. Because chip reliability can be measured by its maximum stress and warpage values, with smaller values ​​indicating more reliable chip packages, the reflow process parameter combination with the lower comprehensive score is superior, based on the low signal-to-noise ratio. The optimal reflow process parameter is number 03. The final reflow profile parameters are: heating and soaking to 150°C from 0s to 40s, preheating and soaking at 190°C from 40s to 140s, then heating to the critical solder melting point at a rate of 3°C / s from 140s to 149s, then heating to 250°C from 149s to 160s, and then starting reflow. The temperature was maintained between 255°C and 260°C for 30s, followed by a cooling rate of 4°C / s to 25°C.

[0088] According to Table 10, the Pareto chart of the standardized effect of the comprehensive score of the reflow process curve is obtained, as shown in Figure 6 As shown in the figure, the cooling rate has the greatest impact on the quality indicators, followed by the peak temperature. When determining the reflow process parameters, packaging manufacturers should pay more attention to the impact of the cooling rate and peak temperature on the reliability of chip products.

[0089] S8 finally provides feedback to the company on key DFN package structure parameters and reflow process parameter combinations. Using finite element simulation software, analysis and guidance based on post-processing simulation results are an essential part of actual production. This improves the accuracy of obtaining the optimal process parameter combination and package reliability, reduces production costs, and addresses the unpredictable reliability issues of chip packages currently encountered on production lines.

[0090] Figure 5 This is the main effect diagram of the signal-to-noise ratio. Since the above quality indicators for chip packaging products are as small as possible, the signal-to-noise ratio diagram of ABCD and the comprehensive score is calculated based on the information C9 response in Table 8, as shown in the figure: Figure 5 As shown in the figure, the optimal solder paste parameter combination can be screened out by the Taguchi method as A2B3C2D1.

[0091] Figure 7This is a comparison chart of the optimal solder paste parameter combination A2B3C2D1 screened by the Taguchi method and the optimal parameter combination A2B3C3D1 screened by the random forest method. The reflow temperature curve is as follows: heating and soaking to 150℃ from 0s to 40s, preheating and soaking at 190℃ from 40s to 140s, first heating to the critical value of the solder melting point at a rate of 3℃ / s from 140s to 149s, then heating to 250℃ from 149s to 160s, starting reflow, and maintaining the temperature at 255℃-260℃ for 30s, and then cooling to 25℃ at a rate of 4℃ / s; the optimal solder paste parameter combination A2B3C2D1 structural parameter combination chip screened by the Taguchi method has a maximum stress value of 128.74MPa, and a maximum warpage value of 2.7328um / cry; the optimal parameter combination A2B3C3D1 structural parameter combination chip screened by the random forest method has a maximum stress value of 122.71MPa, and a maximum warpage value of 2.5802um / cry. The maximum stress value of the optimal parameter combination screened by random forest was reduced by 4.68%, and the warpage was reduced by 5.58% compared with the optimal parameter combination screened by Taguchi method.

[0092] Figure 9 This chart compares data from key parts of the DFN package structure before and after optimization. Before optimization, the solder paste used was SAC305, the pad thickness was 0.025mm, the solder layer on the bottom surface of the chip was 0.025mm thick, and the chip material was Si. The temperature was increased from 25°C to 150°C over a period of 0-40 seconds, followed by a preheat soak at 190°C for 40-140 seconds. The temperature was then raised to the critical melting point of the solder paste over a period of 140-146 seconds, then raised to 260°C over a period of 146-160 seconds for reflow. The temperature was then lowered to 25°C at a maximum rate of 6°C / s.

[0093] Open the finite element simulation software ANSYS, open the static structure of Ansys Workbench, insert Von-MiseStress and Directional deformation, and use a probe to check the stress at the key contact points between the chip and the clip. Before structural parameter optimization, the maximum stress value was 435.69MPa, and the maximum warpage value was 2.8816μm / cry; after structural parameter optimization, the maximum stress value was 122.71MPa, and the maximum warpage value was 2.5802μm / cry. After optimization, the maximum stress value was reduced by 71.8% and the warpage was reduced by 10.4% compared to the pre-optimization value. It can be seen that the method of the present invention solves the problem of unreasonable material combination or structural design in existing chip DFN packaging, which can lead to structural warpage or stress concentration, directly affecting the coplanarity and reliability of the package, and causing chip breakage, solder layer delamination and other problems.

[0094] In addition to the above examples, the present invention has other embodiments. Any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of protection required by the present invention.

[0095] The above shows and describes the basic principles, main features, and advantages of the present invention. However, the above is only a specific embodiment of the present invention, and the technical features of the present invention are not limited thereto. Any other implementation methods derived by any person skilled in the art without departing from the technical solution of the present invention should be included in the patent scope of the present invention.

Claims

1. A chip DFN packaging and process collaborative optimization method based on machine learning, characterized in that: The method comprises the following steps: Step S1: First, determine the chip DFN package structure parameters, including solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type, divide the chip DFN package structure parameters into different level combinations and design a test table according to the Taguchi orthogonal method; Step S2, establishing a finite element model of the DFN package product, setting the reflow temperature curve parameters for the finite element model, simulating to obtain various quality indicators, and calculating the signal-to-noise ratio of each quality indicator. The quality indicators are set as the maximum stress value of the chip, the chip warpage, and the stress and warpage values ​​of the solder layer structure on the lower surface of the chip; Step S3, using the signal-to-noise ratio range analysis method to obtain the weight of each quality indicator; Step S4, based on the weight of each quality indicator, a percentage-based weighted evaluation method is used to determine the comprehensive score of solder paste type, PAD solder layer thickness, chip bottom surface solder layer thickness, and chip material type; Step S5: Using the combination parameters obtained by the Taguchi method as the input of the random forest machine learning method, and the comprehensive score as the output of the random forest machine learning method to train the optimal model, and further screening the combination parameters using grid search to determine the optimal chip DFN package structure parameters; Step S6, setting reflow soldering temperature curve parameters based on the chip DFN package structure parameters screened in step S5, where the reflow soldering process parameters include preheating temperature E, heating temperature F, peak temperature G, holding time H, and cooling rate I; Step S7, using the PB method to perform a reflow soldering temperature curve parameter screening test design, and combining the chip DFN package structure parameters screened in step S5 to simulate and obtain various quality indicators; Step S8, based on the quality indicators obtained in step S7, determine the optimal reflow soldering temperature curve parameters through comprehensive scoring, and then determine the chip DFN package structure parameters and reflow soldering temperature curve parameters; Step S9, modifying the finite element model of the chip DFN package product, simulating and obtaining the optimized quality indicators, and verifying and obtaining the optimal chip DFN package structure parameters and reflow soldering temperature curve parameters.

2. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: In step S1, the solder paste types are selected from Sn-3.0Ag-0.5Cu, Sn-1.0Ag-0.5Cu, and nano-silver solder paste; the PAD solder layer thickness is selected from 0.025mm, 0.035mm, and 0.045mm; the chip bottom surface solder layer thickness is selected from 0.02mm, 0.025mm, and 0.03mm; and the chip material types are selected from Si, SiC, and GaN.

3. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: In step S2, the reflow soldering temperature curve parameters are set as follows: heating and soaking to 150°C from 0s to 40s, preheating and soaking from 40s to 140s, first heating to the critical value of the solder melting point from 140s to 146s, then heating to 260°C from 146s to 160s to start reflow, and then cooling to 25°C at a rate of less than or equal to 6°C / s from 170s to 210s.

4. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: In step S2, the signal-to-noise ratio is analyzed based on the Wang Xiao characteristic, and the calculation formula of the Wang Xiao characteristic is as follows: where y i is the actual calculated value or measured quantity of the ith experimental result, and n is the total number of experimental results.

5. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: In step S4, the formula for the percentage-based weighted evaluation method is: Among them, i is the test number, x k is the kth quality index weight; Y ki is the quality index data result of the kth test in the i-th group of tests, W i is the comprehensive score of the i-th group of tests, and q is the total number of quality indicators.

6. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: Step S5 uses the combination parameters obtained by the Taguchi method as the input of the random forest machine learning method, uses the comprehensive score as the output of the random forest machine learning method to train the optimal model, and uses grid search to further screen the combination parameters to determine the optimal chip DFN packaging structure parameters, specifically including: Step S5.1: The data obtained by the Taguchi method is used as sample data and divided into a training set and a test set, with the ratio of the training set to the test set being 7:2; Step S5.2: randomly extract n samples from the training set to form a sample subset and generate a decision tree. At each generated node m, randomly select multiple features X j , that is, combining parameters without repetition, and then using them to divide the sample set until the best division feature is found; Step S5.3 and step S5.2 are repeated k times, where k is the number of decision trees in the random forest. Step S5.4, applying the test set to perform prediction evaluation on the random forest model, and using the average value to determine the prediction result; In step S5.5, grid search is used to evaluate and cross-validate each set of parameters, and the optimal parameter combination is finally obtained.

7. The chip DFN packaging and process collaborative optimization method based on machine learning according to claim 1 is characterized in that: The reflow soldering temperature curve parameters are set as preheating temperature range: 190-200℃; heating rate range: 2-3℃ / s; peak temperature range: 250-260℃; holding time range: 30-40s; cooling rate range: 4-6℃ / s.

Images