A 14T radiation-resistant SRAM memory cell circuit and operating method

Abstract

A 14T radiation-resistant SRAM memory cell circuit and operating method, belonging to the field of integrated circuit memory, solves the problem in the prior art that SRAM is easily affected by ionizing radiation in a radiation environment, resulting in temporary or permanent failure of the memory cell. The circuit comprises eight PMOS transistors and six NMOS transistors, with the gate of PMOS transistor P5 electrically connected to the drain of PMOS transistor P6, and the drain of PMOS transistor P5 electrically connected to the gate of PMOS transistor P6, forming a cross-coupling structure. Simultaneously, a first redundant node and a second redundant node adopt a dual pull-down transistor structure, and the pull-down transistors are respectively controlled by different feedback. The present invention can completely resist data flipping at a single node, and can still restore to an initial state when data flipping occurs simultaneously at two nodes.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit memory and relates to a 14T radiation-resistant SRAM memory unit circuit and a working method. Background Art

[0002] With the rapid advancement of semiconductor technology, the demand for electronic devices operating in extreme environments is increasing. These applications include space exploration, nuclear energy, and high-radiation medical environments. Under these extreme conditions, electronic devices embedded in SoCs must not only meet high performance and high integration requirements but also exhibit excellent radiation resistance to ensure system reliability and stability. Radiation-induced electromagnetic interference, bit flips, and memory cell errors pose significant challenges to on-chip memory devices, particularly static random access memory (SRAM). As a core component in SoC systems, SRAM is directly related to system performance and stability. However, SRAM is susceptible to ionizing radiation in radiation environments. When high-energy particles pass through the silicon substrate, they generate minority carriers, which can be collected by the source or drain electrodes. When these carriers are collected by transistors surrounding a storage node, they can cause changes in the data stored in the storage node, a phenomenon known as a single-event upset (SEU). If these changes are not promptly corrected, they can cause a data upset in the entire cell. This operation can alter the data stored on the node and potentially compromise data integrity, leading to temporary or permanent failure of the storage cell. Therefore, in order to meet the radiation resistance requirements of integrated circuits in spacecraft and other applications, it is necessary to resolve the impact of SEU on SRAM cells and improve the ability of storage cells to resist SEU.

[0003] There are some technical solutions to this problem in the existing technology, but most of these solutions cannot completely restore the data flip of a single node caused by a single particle effect. Although some solutions can completely restore the data flip of a single node caused by a single particle effect, they are basically unable to recover when data flip occurs on two nodes at the same time.

[0004] The invention patent application with application publication number CN116072184A discloses a 12T radiation-resistant SRAM cell using polarity reinforcement technology, a module using this cell circuit layout, and a radiation-resistant circuit designed based on this cell circuit. The comparative document reinforces the storage nodes Q and QB with NMOS transistors based on polarity reinforcement technology, generating only negative pulses. This pulse cannot affect the state of other transistors due to the presence of gate capacitance, effectively preventing the storage nodes Q and QB from flipping. At the same time, data feedback from the peripheral nodes S0 and S1 ensures that the internal nodes Q and QB can be restored to their initial state after a flip. This allows the cell to achieve improved radiation resistance while ensuring that the tolerance performance does not fall behind, and can also achieve recovery even if SEU occurs on some dual nodes. However, the pull-up of the Q and QB nodes in the comparison document is determined by the voltage of the S0 and S1 nodes. In addition, Q and QB are located between two NMOS transistors. NMOS as a pull-up tube will cause the data node to be unable to achieve the full swing of 0-1.2V; at the same time, although the comparison document has achieved an improvement in radiation resistance, its data nodes are not protected, and there may be a risk of leakage, resulting in unstable data output. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that in a radiation environment, SRAM is easily affected by ionizing radiation, resulting in temporary or permanent failure of the storage unit.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] A 14T radiation-resistant SRAM memory cell circuit includes: 8 PMOS transistors and 6 NMOS transistors, the 8 PMOS transistors are sequentially denoted as P1-P8, and the 6 NMOS transistors are sequentially denoted as N1-N6, wherein:

[0008] The source of the NMOS transistor N1 is electrically connected to the first bit line BL; the drain of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N3, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7; the gate of the NMOS transistor N1 is electrically connected to the first word line WL; the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5; the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6 and the source of the PMOS transistor P8; the drain of the NMOS transistor N5 is electrically connected to the source of the PMOS transistor P7 and the source of the NMOS transistor N4; the source of the NMOS transistor N5 is connected to GND; the gate of the NMOS transistor N6 is electrically connected to the gate of the PMOS transistor P6 and the source of the PMOS transistor P5 The source of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4 are electrically connected; the source of the NMOS transistor N6 is connected to GND; the drain of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N2, the source of the PMOS transistor P4, and the gate of the PMOS transistor P8; the source of the NMOS transistor N2 is electrically connected to the second bit line BLB; the gate of the NMOS transistor N2 is electrically connected to the first word line WL; the source of the PMOS transistor P1 is electrically connected to the first bit line BL; the gate of the PMOS transistor P1 is electrically connected to the second word line WWL; the drain of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, and the drain of the PMOS transistor P4 are connected to VDD; the gate of the PMOS transistor P2 is electrically connected to the second word line WWL; the source of the PMOS transistor P2 is electrically connected to the second bit line BLB.

[0009] The 14T radiation-resistant SRAM memory cell circuit and operating method described in the present invention electrically connects the gate of PMOS transistor P5 to the drain of PMOS transistor P6, and the drain of PMOS transistor P5 to the gate of PMOS transistor P6, forming a cross-coupling structure to completely resist data flipping at a single node. At the same time, because the first redundant node and the second redundant node adopt a dual pull-down tube structure and the pull-down tubes are respectively controlled by different feedback, the dual nodes can still be restored to their initial state when data flipping occurs simultaneously.

[0010] Preferably, a first storage node Q is provided on a line where the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7 are electrically connected.

[0011] Preferably, a second storage node QB is provided on a line where the drain of the NMOS transistor N4 , the drain of the NMOS transistor N2 , the source of the PMOS transistor P4 , and the gate of the PMOS transistor P8 are electrically connected.

[0012] Preferably, a first redundant node S0 is provided on a line where the gate of the NMOS transistor N6, the gate of the PMOS transistor P6, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4 are electrically connected.

[0013] Preferably, a second redundant node S1 is provided on a line where the gate of the NMOS transistor N3, the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5 are electrically connected.

[0014] A 14T radiation-resistant SRAM memory cell circuit operating method, during the data writing phase:

[0015] The first word line WL is at a high level, the NMOS transistor N1 and the NMOS transistor N2 are turned on, and the second word line WWL is at a low level, the PMOS transistor P1 and the PMOS transistor P2 are turned on;

[0016] If the first bit line BL is at a high level and the second bit line BLB is at a low level, then "1" is written to the first storage node Q through the NMOS transistor N1, "1" is written to the first redundant node S0 through the PMOS transistor P1, "0" is written to the second storage node QB through the NMOS transistor N2, and "0" is written to the second redundant node S1 through the PMOS transistor P2;

[0017] On the contrary, if the first bit line BL is at a low level and the second bit line BLB is at a high level, then "0" is written to the first storage node Q through the NMOS transistor N1, "0" is written to the first redundant node S0 through the PMOS transistor P1, "1" is written to the second storage node QB through the NMOS transistor N2, and "1" is written to the second redundant node S1 through the PMOS transistor P2.

[0018] In the data holding stage: the first word line WL is at a low level, and the second word line WWL is at a high level.

[0019] During the data reading phase:

[0020] The first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a high level, and the NMOS transistor N1 and the NMOS transistor N2 are turned on;

[0021] If the data stored in the unit circuit is "0" at this time, then "Q=S0=0, QB=S1=1", then the first bit line BL is discharged through discharge path 1: NMOS transistor N3 and NMOS transistor N6, and discharge path 2: PMOS transistor P7 and NMOS transistor N5, the voltage of the second bit line BLB does not change, and a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier.

[0022] If the data stored in the unit circuit is "1" at this time, then "Q=S0=1, QB=S1=0", then the second bit line BLB discharges to the ground through discharge path 1: NMOS transistor N4 and NMOS transistor N5, and discharge path 2: PMOS transistor P8 and NMOS transistor N6, generating a voltage difference between the first bit line BL and the second bit line BLB, and then the data is read out through the sensitive amplifier.

[0023] An electronic device includes a memory and a processor, wherein the memory is used to store a program that supports the processor to execute the above-mentioned 14T radiation-resistant SRAM storage unit circuit operating method, and the processor is configured to execute the program stored in the memory.

[0024] A storage medium stores a computer program, which, when executed by a processor, executes the steps of the above-mentioned method for operating a 14T radiation-resistant SRAM storage unit circuit.

[0025] The advantages of the present invention are:

[0026] The 14T radiation-resistant SRAM memory cell circuit and operating method described in the present invention electrically connects the gate of PMOS transistor P5 to the drain of PMOS transistor P6, and the drain of PMOS transistor P5 to the gate of PMOS transistor P6, forming a cross-coupling structure to completely resist data flipping at a single node. At the same time, because the first redundant node and the second redundant node adopt a dual pull-down tube structure and the pull-down tubes are respectively controlled by different feedback, the dual nodes can still be restored to their initial state when data flipping occurs simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a circuit structure diagram of a 14T radiation-resistant SRAM memory cell circuit and operating method according to a first embodiment of the present invention;

[0028] Figure 2 This is a timing waveform diagram of a 14T radiation-resistant SRAM memory cell circuit and operating method according to the first embodiment of the present invention;

[0029] Figure 3This is a transient waveform simulation diagram of a single node of a 14T radiation-resistant SRAM memory cell circuit and working method according to embodiment 1 of the present invention being injected with a double-exponential current pulse at different times. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] The technical solution of the present invention is further described below with reference to the accompanying drawings and specific embodiments:

[0032] Example 1

[0033] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0034] like Figure 1 As shown, this embodiment provides a 14T radiation-resistant SRAM memory cell circuit, including: 8 PMOS transistors and 6 NMOS transistors, the 8 PMOS transistors are sequentially denoted as P1-P8, and the 6 NMOS transistors are sequentially denoted as N1-N6, wherein:

[0035] The first bit line BL is electrically connected to the source of the NMOS transistor N1 and the source of the PMOS transistor P1;

[0036] The second bit line BLB is electrically connected to the source of the NMOS transistor N2 and the source of the PMOS transistor P2;

[0037] A first word line WL is electrically connected to the gates of the NMOS transistors N1 and N2;

[0038] A second word line WWL is electrically connected to the gates of the PMOS transistors P1 and P2;

[0039] The drain of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N3, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7;

[0040] The drain of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N4, the source of the PMOS transistor P4, and the gate of the PMOS transistor P8;

[0041] The drain of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N1, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7; the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5; and the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6 and the source of the PMOS transistor P8;

[0042] The drain of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N2, the source of the PMOS transistor P4, and the gate of the PMOS transistor P8; and the gate of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the gate of the PMOS transistor P6, and the gate of the NMOS transistor N6; and the source of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N5 and the source of the PMOS transistor P7;

[0043] The drain of the NMOS transistor N5 is electrically connected to the source of the PMOS transistor P7 and the source of the NMOS transistor N4; the gate of the NMOS transistor N5 is electrically connected to the gate of the PMOS transistor P5, the source of the PMOS transistor P6, the drain of the PMOS transistor P8, the drain of the PMOS transistor P2, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N3; and the source of the NMOS transistor N5 is electrically connected to the source of the NMOS transistor N6 and GND;

[0044] The drain of the NMOS transistor N6 is electrically connected to the source of the PMOS transistor P8 and the source of the NMOS transistor N3; the gate of the NMOS transistor N6 is electrically connected to the gate of the PMOS transistor P6, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4; and the source of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N5 and GND;

[0045] The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P5, the source of the PMOS transistor P7, the gate of the PMOS transistor P6, the gate of the PMOS transistor P4, the gate of the NMOS transistor N6, and the gate of the NMOS transistor N4; the gate of the PMOS transistor P1 is electrically connected to the second word line WWL and the gate of the PMOS transistor P2; and the source of the PMOS transistor P1 is electrically connected to the first bit line BL and the source of the NMOS transistor N1;

[0046] The drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P6, the source of the PMOS transistor P8, the gate of the PMOS transistor P5, the gate of the PMOS transistor P3, the gate of the NMOS transistor N5, and the gate of the NMOS transistor N3; the gate of the PMOS transistor P2 is electrically connected to the second word line WWL and the gate of the PMOS transistor P1; and the source of the PMOS transistor P2 is electrically connected to the second bit line BLB and the source of the NMOS transistor N2;

[0047] The drain of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P4, the drain of the PMOS transistor P5, and the drain of the PMOS transistor P6, and is connected to VDD; the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N3, the gate of the NMOS transistor N5, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, and the gate of the PMOS transistor P5; and the source of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, and the gate of the PMOS transistor P7;

[0048] The drain of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P3, the drain of the PMOS transistor P6, and the drain of the PMOS transistor P5, and is connected to VDD; the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N4, the gate of the NMOS transistor N6, the drain of the PMOS transistor P1, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, and the gate of the PMOS transistor P6; and the source of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, and the gate of the PMOS transistor P8;

[0049] The drain of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P3, the drain of the PMOS transistor P4, and the drain of the PMOS transistor P6, and is electrically connected to VDD; and the gate of the PMOS transistor P5 is electrically connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P8, the gate of the PMOS transistor P3, the drain of the PMOS transistor P2, the gate of the NMOS transistor N3, and the gate of the NMOS transistor N5; and the source of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P7, the gate of the PMOS transistor P6, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, the gate of the NMOS transistor N4, and the gate of the NMOS transistor N6;

[0050] The drain of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P3, the drain of the PMOS transistor P4, and the drain of the PMOS transistor P5, and is electrically connected to VDD; and the gate of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the gate of the PMOS transistor P4, the drain of the PMOS transistor P1, the gate of the NMOS transistor N4, and the gate of the NMOS transistor N6; and the source of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, the drain of the PMOS transistor P2, the gate of the PMOS transistor P3, the gate of the NMOS transistor N3, and the gate of the NMOS transistor N5;

[0051] The drain of the PMOS transistor P7 is electrically connected to the source of the PMOS transistor P5, the drain of the PMOS transistor P1, the gate of the PMOS transistor P6, the gate of the PMOS transistor P4, the gate of the NMOS transistor N6, and the gate of the NMOS transistor N4; and the gate of the PMOS transistor P7 is electrically connected to the source of the PMOS transistor P3, the drain of the NMOS transistor N1, and the drain of the NMOS transistor N3; and the source of the PMOS transistor P7 is electrically connected to the source of the NMOS transistor N4 and the drain of the NMOS transistor N5;

[0052] The drain of the PMOS transistor P8 is electrically connected to the gate of the NMOS transistor N3, the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5; and the gate of the PMOS transistor P8 is electrically connected to the source of the PMOS transistor P4, the drain of the NMOS transistor N2, and the drain of the NMOS transistor N4; and the source of the PMOS transistor P8 is electrically connected to the source of the NMOS transistor N3 and the drain of the NMOS transistor N6.

[0053] The first storage node Q is located in the middle of the line where the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7 are electrically connected; the second storage node QB is located in the middle of the line where the drain of the NMOS transistor N4, the drain of the NMOS transistor N2, the source of the PMOS transistor P4, and the gate of the PMOS transistor P8 are electrically connected; the first redundant node S0 is located in the line where the gate of the NMOS transistor N6, the gate of the PMOS transistor P6, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4 are electrically connected The second redundant node S1 is located at the middle connection point of the line where the gate of the NMOS transistor N3, the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5 are electrically connected; at the same time, the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P6, and the drain of the PMOS transistor P5 is electrically connected to the gate of the PMOS transistor P6, forming a cross-coupling structure to completely resist data flipping at a single node; the first redundant node S1 and the second redundant node S2 adopt a dual pull-down tube structure, and the pull-down tubes are respectively controlled by different feedback.

[0054] The dual pull-down tube design can reduce the leakage current of the circuit during the data retention phase, further reducing the power consumption of the circuit. When the data is impacted, the dual pull-down tube design can ensure that high-level data is not easily lost. The dual pull-down tubes can ensure that data is not lost due to the sudden conduction of one of the pull-down tubes. The dual pull-down structure can also increase the static noise tolerance of the structure and enhance the circuit structure's ability to cope with noise.

[0055] The working principle of the present invention is:

[0056] During the data retention phase:

[0057] The first word line WL is at a low level, and the second word line WWL is at a high level.

[0058] During the data writing phase:

[0059] The first word line WL is at a high level, and the NMOS transistors N1 and N2 are turned on. The second word line WWL is at a low level, and the PMOS transistors P1 and P2 are turned on.

[0060] If the first bit line BL is at a high level and the second bit line BLB is at a low level, then "1" is written to the first storage node Q through the NMOS transistor N1, "1" is written to the first redundant node S0 through the PMOS transistor P1, "0" is written to the second storage node QB through the NMOS transistor N2, and "0" is written to the second redundant node S1 through the PMOS transistor P2.

[0061] On the contrary, if the first bit line BL is at a low level and the second bit line BLB is at a high level, then "0" is written to the first storage node Q through the NMOS transistor N1, "0" is written to the first redundant node S0 through the PMOS transistor P1, "1" is written to the second storage node QB through the NMOS transistor N2, and "1" is written to the second redundant node S1 through the PMOS transistor P2.

[0062] During the data reading phase:

[0063] The first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a high level, and the NMOS transistors N1 and N2 are turned on.

[0064] If the data stored in the unit circuit is "0", then "Q=S0=0, QB=S1=1", then the first bit line BL is discharged through discharge path 1: NMOS transistors N3 and N6, and discharge path 2: PMOS transistor P7 and NMOS transistor N5, and the voltage of the second bit line BLB does not change, so that a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier.

[0065] If the data stored in the unit circuit is "1", then "Q=S0=1, QB=S1=0", then the second bit line BLB is discharged to the ground through discharge path 1: NMOS transistors N4 and N5, and discharge path 2: PMOS transistor P8 and NMOS transistor N6, so that a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sensitive amplifier.

[0066] like Figure 2 As shown in FIG, the timing waveform diagram of the 14T radiation-resistant SRAM memory cell circuit provided by the embodiment of the present invention, the specific simulation conditions are: Corner: TT, Temperature: 25°C, VDD: 1.2V. Figure 2 It can be seen that the data "1" is written in 50-100ns, the data "1" is read out in 200-250ns, the data "0" is written in 350-400ns, and the data "0" is read out in 500-550ns. It can be seen that the 14T radiation-resistant SRAM storage unit circuit provided by the present invention can realize the operations of writing "1", reading "1", writing "0", and reading "0" on the storage node.

[0067] like Figure 3 As shown in FIG, a transient waveform simulation diagram of a single node of a 14T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention being injected with a double exponential current pulse at different times. Figure 3 As can be seen, at 100ns, the first storage node Q was struck by a single event, causing the data to flip from "0" to "1." Through the circuit feedback structure, the data was quickly restored. At 200ns, the first redundant node S0 was struck by a single event, causing the data to flip from "0" to "1." Through the circuit feedback structure, the data was quickly restored. At 300ns, the first redundant node QB was struck by a single event, causing the data to flip from "1" to "0." Through the circuit feedback structure, the data was quickly restored.

[0068] Taking the storage state of "0" (i.e., Q="0", QB="1", S0="0", S1="1") as an example, since the second redundant node S1 is surrounded only by PMOS transistors and its state is "1", the second redundant node S1 is not a sensitive node (a sensitive node refers to a node that can cause data flipping (logical value change) after a single event effect occurs, and the sensitive nodes are different in different storage states). Therefore, the sensitive nodes are the first storage node Q, the second storage node QB, and the first redundant node S0.

[0069] When the data of the first storage node Q deflects from state "0" to state "1", P7 is temporarily turned off. Since the pull-up transistor P5 of the first storage node S0 is controlled by the second redundant node S1 and remains closed, the temporary closure of P7 does not affect the data of the first redundant node S0. The pull-down transistor N4 of the second storage node QB remains closed due to the unchanged data of the first redundant node S0 and does not affect the data of the storage node QB. The first storage node Q is connected to GND through the open N3 and N6, thereby restoring to the logic value "0".

[0070] When the first redundant node S0 experiences a data transition, from state "0" to state "1," N4 and N6 are temporarily turned on, while P4 and P6 are temporarily turned off. Because pull-down transistor N5 on the second storage node QB is controlled by S1 and remains off, the temporary turn-on of N4 does not affect the data on storage node QB. Pull-down transistor P8 on the second redundant node S1 remains off because the data on QB remains unchanged, so the data on PB remains unchanged. The first redundant node S0 is connected to GND via the turned-on P7 and N5, thereby restoring its logic value to "0."

[0071] When the data on the second storage node QB changes from state "1" to state "0," P8 is temporarily turned on. Because the pull-down transistor N6 of the second redundant node S1 is controlled by the data node S1 and remains off, the brief turn-on of P8 does not affect the data on the second redundant node S1. The pull-up transistor P3 of the first storage node Q remains off due to the unchanged state of the second redundant node S1 and does not affect its data. The second storage node QB is connected to the power supply VDD through the turned-on P4, thereby restoring its logic value to "1."

[0072] It should be noted that when the storage state is "1", the principle of combating SEU is similar and will not be repeated here.

[0073] In the 14T radiation-resistant SRAM storage cell circuit of the present invention, the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P6, and the drain of the PMOS transistor P5 is electrically connected to the gate of the PMOS transistor P6, forming a cross-coupling structure to completely resist data flipping at a single node; at the same time, because the first redundant node and the second redundant node adopt a dual pull-down tube structure and the pull-down tubes are respectively controlled by different feedback, the dual nodes can still be restored to the initial state when data flipping occurs at the same time. Compared with the traditional SRAM radiation-resistant reinforcement circuit, the present invention places two redundant storage nodes between the same type of MOS transistors through the polarity reinforcement method, and is insensitive to such storage nodes. For nodes surrounded only by the same type of MOS transistors, only current pulses of the same polarity will be generated when a single particle effect occurs, thereby reducing the possibility of node data flipping.

[0074] At the same time, all data nodes of the present invention have two transistors between them and the ground, which can greatly reduce leakage current; all data branches are powered by power, which increases the data driving capability; and all nodes adopt a dual pull-down tube design; non-polar reinforced data nodes are used as data output to ensure stable output data.

[0075] Example 2

[0076] An electronic device includes a memory and a processor, wherein the memory is used to store a program that supports the processor to execute the above-mentioned 14T radiation-resistant SRAM storage unit circuit operating method, and the processor is configured to execute the program stored in the memory.

[0077] Example 3

[0078] A storage medium stores a computer program, which, when executed by a processor, executes the steps of the above-mentioned method for operating a 14T radiation-resistant SRAM storage unit circuit.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A 14T radiation-resistant SRAM memory cell circuit, characterized in that: include: 8 PMOS transistors and 6 NMOS transistors, the 8 PMOS transistors are sequentially denoted as P1-P8, and the 6 NMOS transistors are sequentially denoted as N1-N6, wherein: The source of the NMOS transistor N1 is electrically connected to the first bit line BL; the drain of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N3, the source of the PMOS transistor P3, and the gate of the PMOS transistor P7; the gate of the NMOS transistor N1 is electrically connected to the first word line WL; the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5; the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6 and the source of the PMOS transistor P8; the drain of the NMOS transistor N5 is electrically connected to the source of the PMOS transistor P7 and the source of the NMOS transistor N4; the source of the NMOS transistor N5 is connected to GND; the gate of the NMOS transistor N6 is electrically connected to the gate of the PMOS transistor P6 and the source of the PMOS transistor P5 The source of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4 are electrically connected; the source of the NMOS transistor N6 is connected to GND; the drain of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N2, the source of the PMOS transistor P4, and the gate of the PMOS transistor P8; the source of the NMOS transistor N2 is electrically connected to the second bit line BLB; the gate of the NMOS transistor N2 is electrically connected to the first word line WL; the source of the PMOS transistor P1 is electrically connected to the first bit line BL; the gate of the PMOS transistor P1 is electrically connected to the second word line WWL; the drain of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, and the drain of the PMOS transistor P4 are connected to VDD; the gate of the PMOS transistor P2 is electrically connected to the second word line WWL; the source of the PMOS transistor P2 is electrically connected to the second bit line BLB.

2. The 14T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that: A first storage node Q is provided on a line to which the drain of the NMOS transistor N1 , the drain of the NMOS transistor N3 , the source of the PMOS transistor P3 , and the gate of the PMOS transistor P7 are electrically connected.

3. The 14T radiation-resistant SRAM memory cell circuit according to claim 2, characterized in that: A second storage node QB is provided on a line to which the drain of the NMOS transistor N4 , the drain of the NMOS transistor N2 , the source of the PMOS transistor P4 , and the gate of the PMOS transistor P8 are electrically connected.

4. The 14T radiation-resistant SRAM memory cell circuit according to claim 3, wherein: A first redundant node S0 is provided on a line where the gate of the NMOS transistor N6, the gate of the PMOS transistor P6, the source of the PMOS transistor P5, the drain of the PMOS transistor P7, the drain of the PMOS transistor P1, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4 are electrically connected.

5. The 14T radiation-resistant SRAM memory cell circuit according to claim 4, characterized in that: A second redundant node S1 is provided on a line where the gate of the NMOS transistor N3, the gate of the PMOS transistor P3, the source of the PMOS transistor P6, the drain of the PMOS transistor P2, the drain of the PMOS transistor P8, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N5 are electrically connected.

6. A method for operating a 14T radiation-hardened SRAM memory cell circuit, characterized in that: The 14T radiation-resistant SRAM memory cell circuit according to claim 5 is applied, during the data writing stage: The first word line WL is at a high level, the NMOS transistor N1 and the NMOS transistor N2 are turned on, and the second word line WWL is at a low level, the PMOS transistor P1 and the PMOS transistor P2 are turned on; If the first bit line BL is at a high level and the second bit line BLB is at a low level, then "1" is written to the first storage node Q through the NMOS transistor N1, "1" is written to the first redundancy node S0 through the PMOS transistor P1, "0" is written to the second storage node QB through the NMOS transistor N2, and "0" is written to the second redundancy node S1 through the PMOS transistor P2; On the contrary, if the first bit line BL is at a low level and the second bit line BLB is at a high level, then "0" is written to the first storage node Q through the NMOS transistor N1, "0" is written to the first redundant node S0 through the PMOS transistor P1, "1" is written to the second storage node QB through the NMOS transistor N2, and "1" is written to the second redundant node S1 through the PMOS transistor P2.

7. The operating method of a 14T radiation-resistant SRAM memory cell circuit according to claim 6, characterized in that: In the data holding stage: the first word line WL is at a low level, and the second word line WWL is at a high level.

8. The operating method of a 14T radiation-resistant SRAM memory cell circuit according to claim 7, characterized in that: During the data reading phase: The first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a high level, and the NMOS transistor N1 and the NMOS transistor N2 are turned on; If the data stored in the unit circuit is "0" at this time, then "Q = S0 = 0, QB = S1 = 1", then the first bit line BL is discharged through discharge path 1: NMOS transistor N3 and NMOS transistor N6, and discharge path 2: PMOS transistor P7 and NMOS transistor N5, the voltage of the second bit line BLB does not change, and a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier; If the data stored in the unit circuit is "1" at this time, then "Q=S0=1, QB=S1=0", then the second bit line BLB is discharged to ground through discharge path 1: NMOS transistor N4 and NMOS transistor N5, and discharge path 2: PMOS transistor P8 and NMOS transistor N6. A voltage difference is generated between the first bit line BL and the second bit line BLB, and the data is then read out through the sense amplifier.

9. An electronic device comprising a memory and a processor, characterized in that: The memory is used to store a program that supports the processor to execute the 14T radiation-resistant SRAM memory cell circuit operating method according to any one of claims 6 to 8, and the processor is configured to execute the program stored in the memory.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the 14T radiation-resistant SRAM memory cell circuit operating method according to any one of claims 6 to 8 are executed.

Images