Method for getting impurities on silicon wafer and silicon wafer

Abstract

The present invention discloses a method for getting impurities on a silicon wafer and a silicon wafer, and relates to the field of silicon wafer manufacturing. The method comprises: performing corrosion treatment on the surface of an initial silicon wafer to obtain a first silicon wafer with a surface microstructure; the specific surface area of ​​the first silicon wafer is 10m 2 / g~500m 2 / g; covering the surface of the first silicon wafer with a phosphorus source, wherein the phosphorus source is a phosphorus-containing compound; heating the first silicon wafer with the phosphorus source on the surface to a set temperature and maintaining it for a set time, so that the phosphorus source reacts with the first silicon wafer and forms a phosphorus gettering layer on the surface of the first silicon wafer; removing the phosphorus gettering layer on the surface of the first silicon wafer after the heating treatment, to obtain a gettering silicon wafer. The present invention has the advantage of reducing the metal impurity content of the silicon wafer.

Description

Technical Field

[0001] The invention relates to the technical field of silicon wafer manufacturing, and in particular to a method for getting impurities on a silicon wafer and the silicon wafer. Background Art

[0002] Silicon is the raw material of solar cells. In the silicon wafer manufacturing process, due to the presence of certain metal impurities in the silicon material, the diffusion, adsorption, penetration and movement of impurity atoms in the crystal, or in the process of quantum drive effect, it is easy to cause deep energy level defects in the silicon wafer, affecting the minority carrier lifetime of the silicon wafer, which is directly related to the photoelectric conversion efficiency of solar cells. Therefore, in the process of silicon wafer preparation, effectively controlling and reducing the content of metal impurities is crucial to improving the efficiency of solar cells. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art to a certain extent. To this end, the present invention provides a method for performing gettering on a silicon wafer and a silicon wafer, which has the advantage of reducing the metal impurity content of the silicon wafer.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] A method for gettering a silicon wafer, comprising:

[0006] The surface of the initial silicon wafer is subjected to etching treatment to obtain a first silicon wafer having a surface microstructure; the specific surface area of ​​the first silicon wafer is 10 m2 / g to 500 m2 / g;

[0007] Covering a phosphorus source on the surface of the first silicon wafer, wherein the phosphorus source is a phosphorus-containing compound;

[0008] The first silicon wafer with the phosphorus source on the surface thereof is heated to a set temperature and maintained for a set time, so that the phosphorus source reacts with the first silicon wafer and forms a phosphorus gettering layer on the surface of the first silicon wafer;

[0009] The phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment is removed to obtain a gettering silicon wafer.

[0010] Optionally, the etching process is performed on the surface of the initial silicon wafer to obtain the first silicon wafer having a surface microstructure, comprising:

[0011] Adding a microstructure corrosion additive to an alkaline solution and mixing the mixture evenly to obtain a surface microstructure corrosion solution; the microstructure corrosion additive comprises at least one of a polyhydroxy organic compound, a polycarboxyl organic compound, a polyphenolic hydroxy organic compound, and a polyamino organic compound, and the volume ratio of the microstructure corrosion additive to the alkaline solution is 1:1000 to 1:100;

[0012] The surface microstructure etching solution is heated to a preset temperature, an initial silicon wafer is immersed in the surface microstructure etching solution, and microstructure etching is performed on the initial silicon wafer until the reaction time reaches a preset time, thereby obtaining a first silicon wafer with a surface microstructure.

[0013] Optionally, the step of covering the surface of the first silicon wafer with a phosphorus source, and heating the first silicon wafer with the surface covered with the phosphorus source to a set temperature and maintaining the temperature for a set time comprises:

[0014] Applying a phosphorus source on the surface of the first silicon wafer after cleaning and drying, and drying the surface of the first silicon wafer; the phosphorus source includes an aqueous solution of a phosphorus-containing compound;

[0015] Placing the first silicon wafer with the phosphorus source coated on the surface on a ceramic roller conveyor belt of a tunnel annealing furnace, and conveying the first silicon wafer into the tunnel annealing furnace through the ceramic roller conveyor belt at a conveying speed of 1 m / min to 6 m / min;

[0016] A protective atmosphere is introduced into the tunnel annealing furnace; the protective atmosphere comprises at least one of oxygen, argon, and nitrogen;

[0017] The first silicon wafer is heated to a set temperature and maintained for a set time.

[0018] Optionally, the set temperature is 600° C. to 900° C., and the set time is 1 min to 3 min.

[0019] Optionally, the total coating amount of the phosphorus source on both sides of the first silicon wafer is 0.02 mg / cm2~1 mg / cm2.

[0020] Optionally, the phosphorus source includes phosphorus oxychloride, and the phosphorus source is covered on the surface of the first silicon wafer, and the first silicon wafer with the phosphorus source on the surface is heated to a set temperature and maintained for a set time, comprising:

[0021] placing the cleaned and dried first silicon wafer into a tube furnace;

[0022] Phosphorus oxychloride is introduced into the tubular furnace through a carrier gas at a set temperature, wherein the carrier gas is oxygen or nitrogen;

[0023] The first silicon wafer is heated to a set temperature and maintained for a set time.

[0024] Optionally, the set temperature is 600° C. to 900° C., and the set time is 10 min to 60 min.

[0025] Optionally, the set temperature includes a first stage temperature and a second stage temperature, the first stage temperature is greater than the second stage temperature, the first stage temperature is 700°C to 900°C, and the second stage temperature is 600°C to 800°C.

[0026] Optionally, the removing the phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment to obtain a gettering silicon wafer comprises:

[0027] The phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment is rinsed with a hydrofluoric acid solution to obtain a gettering silicon wafer; the concentration of the hydrofluoric acid solution is 1% to 10%.

[0028] In addition, the present invention also provides a silicon wafer, which is prepared by any of the above methods. The reasoning process of the beneficial effects of the silicon wafer provided by the present invention and the above methods is similar, and will not be repeated here.

[0029] These features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. The best embodiments or means of the present invention will be described in detail in conjunction with the drawings, but they are not intended to limit the technical solutions of the present invention. In addition, there are multiple features, elements, and components that appear in each of the following texts and drawings, and different symbols or numbers are marked for convenience, but they all represent components with the same or similar structures or functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below in conjunction with the accompanying drawings:

[0031] Figure 1 A schematic flow chart of a method for gettering a silicon wafer according to an embodiment of the present invention;

[0032] Figure 2 Schematic diagram of minority carrier lifetime of silicon wafers after being processed in different ways according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments in the implementation manner are intended to be used to explain the present invention and should not be construed as limiting the present invention.

[0034] References in this specification to "one embodiment" or "an example" or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment itself may be included in at least one embodiment of the present patent disclosure. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment.

[0035] This embodiment provides a method for performing gettering on a silicon wafer, such as Figure 1 As shown, the said includes:

[0036] In step S110, the surface of the initial silicon wafer is subjected to etching treatment to obtain a first silicon wafer having a surface microstructure; the specific surface area of ​​the first silicon wafer is 10 m2 / g to 500 m2 / g;

[0037] In step S120, a phosphorus source is covered on the surface of the first silicon wafer, wherein the phosphorus source is a phosphorus-containing compound;

[0038] In step S130, the first silicon wafer with the surface covered with the phosphorus source is heated to a set temperature and maintained for a set time, so that the phosphorus source reacts with the first silicon wafer and forms a phosphorus gettering layer on the surface of the first silicon wafer;

[0039] In step S140, the phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment is removed.

[0040] In silicon wafers, metal impurities generally exist in the form of metal precipitates or metal ions. During the process of heating to high temperature, the metal precipitates continuously dissolve and release metal ions. The phosphorus source on the surface of the first silicon wafer reacts with the first silicon wafer at high temperature, and a phosphorus gettering layer is continuously formed on the surface of the first silicon wafer. The change in the Fermi level in the phosphorus gettering layer causes the solubility of impurities to increase, and electrostatic attraction will also occur between the phosphorus doped ions and the metal impurities, thereby increasing the solubility of the metal impurities in the phosphorus gettering layer. At the same time, the phosphorus-vacancy complex formed in the heavily phosphorus-doped area improves the impurity capture capability.

[0041] It should be noted that the heating treatment here is to place the first silicon wafer in an annealing furnace or a tubular furnace for annealing. Before the first silicon wafer with the phosphorus source on the surface is annealed, the silicon wafer is etched to form a surface microstructure on the surface of the silicon wafer, thereby increasing the surface area of ​​the silicon wafer, so that the subsequent generated surface diffusion impurity layer has a larger effective area, which helps to absorb more metal impurities, thereby improving the impurity gettering effect.

[0042] In the present invention, the specific shape of the surface microstructure is not particularly limited. For example, the shape of the surface microstructure is any one of irregular pits, irregular holes, irregular protrusions, pyramid-shaped protrusions, inverted pyramid-shaped pits, irregular linear pits or protrusions. Preferably, the surface microstructure unit size is 0.2um~5um.

[0043] Optionally, step S110 includes:

[0044] Adding a microstructure corrosion additive to an alkaline solution and mixing the mixture evenly to obtain a surface microstructure corrosion solution; the microstructure corrosion additive comprises at least one of a polyhydroxy organic compound, a polycarboxyl organic compound, a polyphenolic hydroxy organic compound, and a polyamino organic compound, and the volume ratio of the microstructure corrosion additive to the alkaline solution is 1:1000 to 1:100;

[0045] The surface microstructure etching solution is heated to a preset temperature, and the initial silicon wafer is immersed in the surface microstructure etching solution to perform microstructure etching on the initial silicon wafer until the reaction time reaches a preset time, thereby obtaining a first silicon wafer with a surface microstructure. Figure 2 As shown, the minority carrier lifetime values ​​corresponding to the untreated initial silicon wafer (original silicon wafer), the initial silicon wafer after annealing (normal impurity absorption), and the silicon wafer after corrosion and annealing (surface microstructure enhanced impurity absorption) are respectively shown.

[0046] By selecting a suitable microstructure etching additive and controlling the concentration, reaction temperature and reaction time of the surface microstructure etching solution, a surface microstructure within a specified size range is etched on the surface of the first silicon wafer, and the thinning amount of the silicon wafer during the etching process is effectively controlled while ensuring the gettering effect of the subsequent phosphorus gettering layer. The microstructure etching additive includes a combination of one or more of the following substances: carboxymethyl hydroxyethyl co-modified cellulose and its salts, lignin sulfonate, formaldehyde condensate of sodium methyl naphthalene sulfonate, methylene bis naphthalene sulfonate, polyquaternary ammonium salt, 12-16 carbon alkyl ammonium salt, 12-16 carbon alkyl ammonium halide, and polyglycerol.

[0047] In an optional embodiment, the step of covering the surface of the first silicon wafer with a phosphorus source, and heating the first silicon wafer with the surface covered with the phosphorus source to a set temperature and maintaining the temperature for a set time comprises:

[0048] Applying a phosphorus source on the surface of the first silicon wafer after cleaning and drying, and drying the surface of the first silicon wafer; the phosphorus source includes an aqueous solution of a phosphorus-containing compound;

[0049] Placing the first silicon wafer with the phosphorus source coated on the surface on a ceramic roller conveyor belt of a tunnel annealing furnace, and conveying the first silicon wafer into the tunnel annealing furnace through the ceramic roller conveyor belt at a conveying speed of 1 m / min to 6 m / min;

[0050] A protective atmosphere is introduced into the tunnel annealing furnace; the protective atmosphere comprises at least one of oxygen, argon, and nitrogen;

[0051] The first silicon wafer is heated to a set temperature and maintained for a set time.

[0052] For example, the phosphorus source is a phosphoric acid aqueous solution. The phosphoric acid aqueous solution is applied to the surface of the first silicon wafer, and the phosphoric acid aqueous solution is decomposed at high temperature in a tunnel annealing furnace to generate pyrophosphoric acid, phosphorus pentoxide, etc. The phosphorus pentoxide reacts with silicon to finally generate silicon dioxide and phosphorus element, forming a layer of phosphorus silicon glass (silicon dioxide containing phosphorus element) on the surface of the first silicon wafer, that is, a phosphorus gettering layer. In a high temperature environment, the metal elements in the first silicon wafer continuously converge into the phosphorus gettering layer. Finally, by cleaning the phosphorus gettering layer after gettering, the impurity content of the first silicon wafer is effectively reduced.

[0053] By placing the first silicon wafer on a ceramic roller conveyor, it can be placed in the tunnel annealing furnace without the need for robot transfer, which reduces the fragmentation rate of the first silicon wafer and is suitable for the impurity treatment of ultra-thin silicon wafers. In addition, a protective atmosphere is introduced into the tunnel annealing furnace to ensure that the phosphoric acid aqueous solution fully reacts on the surface of the first silicon wafer and avoids corrosion of the surface of the first silicon wafer by the intermediate product.

[0054] Preferably, the set temperature is 600° C. to 900° C., and the set time is 1 min to 3 min.

[0055] By controlling and setting the annealing gettering temperature and annealing gettering time, it is beneficial to form a highly doped phosphorus gettering layer, increase the solubility of metal impurities in the phosphorus gettering layer, and thus improve the gettering effect.

[0056] In the present invention, there is no particular limitation on the coating method of the phosphorus source. Optionally, the method of coating the phosphorus source on the surface of the first silicon wafer includes any one of roller coating, spray coating or dip coating. Preferably, the total coating amount of the phosphorus source on both sides of the first silicon wafer is 0.02 mg / cm2 to 1 mg / cm2.

[0057] Optionally, the phosphorus source includes phosphorus oxychloride, and the phosphorus source is covered on the surface of the first silicon wafer, and the first silicon wafer with the phosphorus source on the surface is heated to a set temperature and maintained for a set time, comprising:

[0058] placing the cleaned and dried first silicon wafer into a tube furnace;

[0059] Phosphorus oxychloride is introduced into the tubular furnace through a carrier gas at a set temperature, wherein the carrier gas is oxygen or nitrogen;

[0060] The first silicon wafer is heated to a set temperature and maintained for a set time.

[0061] Phosphorus oxychloride decomposes at high temperature (>600℃) to generate phosphorus pentachloride and phosphorus pentoxide. If there is no external oxygen involved, the decomposition is insufficient. The generated phosphorus pentachloride is not easy to decompose and has a corrosive effect on silicon, thereby destroying the surface state of the silicon wafer. Therefore, when phosphorus oxychloride is introduced, a certain amount of oxygen can be introduced so that phosphorus pentachloride will further decompose into phosphorus pentoxide and release chlorine. Phosphorus pentoxide is deposited on the surface of the silicon wafer, and phosphorus pentoxide reacts with silicon to generate silicon dioxide and phosphorus atoms, thereby forming a phosphorus gettering layer on the surface of the first silicon wafer.

[0062] Preferably, the set temperature is 600° C. to 900° C., and the set time is 10 min to 60 min.

[0063] In an optional embodiment, the set temperature includes a first stage temperature and a second stage temperature, the first stage temperature is greater than the second stage temperature, the first stage temperature is 700°C to 900°C, and the second stage temperature is 600°C to 800°C.

[0064] Under the variable temperature gettering condition, the first stage temperature assists in forming a highly doped phosphorus gettering layer, and the second stage temperature increases the solubility of impurities in the diffusion layer.

[0065] Optionally, step S130 includes:

[0066] The phosphorus gettering layer on the surface of the first silicon wafer after annealing is rinsed with a hydrofluoric acid solution to obtain a gettering silicon wafer; the concentration of the hydrofluoric acid solution is 1% to 10%.

[0067] By immersing the first silicon wafer after annealing in a hydrofluoric acid solution, the phosphorus gettering layer that absorbs metal impurities is removed, thereby reducing the content of metal impurities in the silicon wafer.

[0068] The present invention also provides a silicon wafer, which is manufactured by any of the methods described above.

[0069] By corroding the surface of the initial silicon wafer before annealing the initial silicon wafer, the area of ​​the phosphorus gettering layer is increased, and a variety of phosphorus diffusion gettering methods are combined, and the temperature and time during the reaction process are controlled, the adsorption effect of the phosphorus gettering layer is effectively improved, and the impurity content of the silicon wafer is reduced. The silicon wafer prepared in this embodiment can be used for solar cell manufacturing.

[0070] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present invention will be included in the scope of the claims.

Claims

1. A method for gettering a silicon wafer, characterized in that: include: The surface of the initial silicon wafer is subjected to etching treatment to obtain a first silicon wafer having a surface microstructure; the specific surface area of ​​the first silicon wafer is 10m 2 / g~500m 2 / g; Covering a phosphorus source on the surface of the first silicon wafer, wherein the phosphorus source is a phosphorus-containing compound; The first silicon wafer with the phosphorus source on the surface thereof is heated to a set temperature and maintained for a set time, so that the phosphorus source reacts with the first silicon wafer and forms a phosphorus gettering layer on the surface of the first silicon wafer; removing the phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment to obtain a gettering silicon wafer; The process of etching the surface of the initial silicon wafer to obtain a first silicon wafer having a surface microstructure comprises: Adding a microstructure corrosion additive to an alkaline solution and mixing the mixture evenly to obtain a surface microstructure corrosion solution; the microstructure corrosion additive comprises at least one of a polyhydroxy organic compound, a polycarboxyl organic compound, a polyphenolic hydroxy organic compound, and a polyamino organic compound, and the volume ratio of the microstructure corrosion additive to the alkaline solution is 1:1000 to 1:100; The surface microstructure etching solution is heated to a preset temperature, an initial silicon wafer is immersed in the surface microstructure etching solution, and microstructure etching is performed on the initial silicon wafer until the reaction time reaches a preset time, thereby obtaining a first silicon wafer with a surface microstructure.

2. The method according to claim 1, characterized in that The step of covering the surface of the first silicon wafer with a phosphorus source, and heating the first silicon wafer with the surface covered with the phosphorus source to a set temperature and maintaining the temperature for a set time comprises: Applying a phosphorus source on the surface of the first silicon wafer after cleaning and drying, and drying the surface of the first silicon wafer; the phosphorus source includes an aqueous solution of a phosphorus-containing compound; Placing the first silicon wafer with the phosphorus source coated on the surface on a ceramic roller conveyor belt of a tunnel annealing furnace, and conveying the first silicon wafer into the tunnel annealing furnace through the ceramic roller conveyor belt at a conveying speed of 1 m / min to 6 m / min; A protective atmosphere is introduced into the tunnel annealing furnace; the protective atmosphere comprises at least one of oxygen, argon, and nitrogen; The first silicon wafer is heated to a set temperature and maintained for a set time.

3. The method according to claim 2, characterized in that The set temperature is 600° C. to 900° C., and the set time is 1 min to 3 min.

4. The method according to claim 2, characterized in that: The total coating amount of the phosphorus source on both sides of the first silicon wafer is 0.02 mg / cm 2 ~1mg / cm 2 .

5. The method according to claim 1, characterized in that The phosphorus source includes phosphorus oxychloride, and the surface of the first silicon wafer is covered with the phosphorus source. The first silicon wafer with the surface covered with the phosphorus source is heated to a set temperature and maintained for a set time, comprising: placing the cleaned and dried first silicon wafer into a tube furnace; Phosphorus oxychloride is introduced into the tubular furnace through a carrier gas at a set temperature, wherein the carrier gas is oxygen or nitrogen; The first silicon wafer is heated to a set temperature and maintained for a set time.

6. The method according to claim 5, characterized in that The set temperature is 600° C. to 900° C., and the set time is 10 min to 60 min.

7. The method according to claim 4 or 6, characterized in that: The set temperature includes a first stage temperature and a second stage temperature, the first stage temperature is greater than the second stage temperature, the first stage temperature is 700°C to 900°C, and the second stage temperature is 600°C to 800°C.

8. The method according to any one of claims 1 to 6, characterized in that: The step of removing the phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment to obtain a gettering silicon wafer comprises: The phosphorus gettering layer on the surface of the first silicon wafer after the heat treatment is rinsed with a hydrofluoric acid solution to obtain a gettering silicon wafer; the concentration of the hydrofluoric acid solution is 1% to 10%.

9. A silicon wafer, characterized in that: The silicon wafer is produced by the method according to any one of claims 1 to 8.

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