Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first chip, the first chip being provided with a first pad; a second chip, the second chip being provided with a second pad and a metal bump, the metal bump being located on a surface of the second pad away from the second chip and being bonded with the first pad; and an insulating layer, the insulating layer being located between the first chip and the second chip, the insulating layer having a first cavity and a second cavity, the first cavity being located at the periphery of the first pad, the second cavity being located at the periphery of the metal bump, and the first cavity and the second cavity being communicated to jointly form a cavity; wherein the metal bump fills the cavity. The semiconductor structure can avoid the short circuit phenomenon between adjacent metal bumps and can also avoid the local collapse of the metal bump.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As people's demands for electronic products develop towards miniaturization and multifunctionality, packaging technology is also developing towards high density and high integration. For example, at least two chips (dies) are packaged in a three-dimensional stack (3DS) based on bumps.

[0003] However, with the increase in interconnect density, short circuits between chip bumps become more likely. Therefore, how to prevent short circuits between bumps is a technical problem that urgently needs to be solved at this stage. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its manufacturing method to address the shortcomings of existing technologies.

[0005] On one hand, this application provides a semiconductor structure, including:

[0006] First chip; the first chip is provided with a first pad;

[0007] The second chip; the second chip is provided with a second pad and a metal bump; the metal bump is located on the surface of the second pad away from the second chip and is bonded to the first pad;

[0008] An insulating layer is located between the first chip and the second chip; the insulating layer has a first cavity and a second cavity, the first cavity is located around the first pad, the second cavity is located around the metal bump, and the first cavity and the second cavity are connected to each other to form a cavity together;

[0009] The metal bumps fill the cavity.

[0010] In some embodiments, the bottom surface of the first cavity is higher than the contact surface between the first pad and the first chip.

[0011] In some embodiments, the distance between the bottom surface of the second cavity and the surface of the metal bump away from the second pad is less than the height of the metal bump.

[0012] In some embodiments, the insulating layer includes:

[0013] A first insulating layer is located on the first chip, and the first pad and the first cavity are located within the first insulating layer;

[0014] A second insulating layer is located on the second chip, and the second pad and the second cavity are located within the second insulating layer.

[0015] In some embodiments, an air-absorbing material layer is further disposed between the first insulating layer and the second insulating layer; the hardness of the air-absorbing material layer is less than the hardness of the insulating layer.

[0016] In some embodiments, the hardness of the insulating layer is less than that of the inorganic insulating layer, and the material of the insulating layer includes polymers.

[0017] In some embodiments, the insulating layer includes:

[0018] A first insulating layer is located on the first chip, and the first pad and the first cavity are located within the first insulating layer;

[0019] The second insulating layer is located on the sidewall of the second pad, and the second cavity surrounds the second pad, the metal bump, and the second insulating layer.

[0020] In some embodiments, the second cavity includes:

[0021] The first sub-cavity, wherein the metal bump protrudes from the first sub-cavity;

[0022] The second sub-cavity is located between the first sub-cavity and the second chip, and the second insulating layer is located between the second sub-cavity and the second pad;

[0023] The width of the first sub-cavity is greater than the width of the second sub-cavity.

[0024] In some embodiments, the second insulating layer contacts the metal bump.

[0025] In some embodiments, the first insulating layer extends through the second sub-cavity into the first sub-cavity to contact the second insulating layer.

[0026] In some embodiments, the metal bumps fill the first cavity and a portion of the first sub-cavity.

[0027] In some embodiments, the metal bump is made of tin; the first pad is made of copper and / or nickel.

[0028] On the other hand, this application also provides a method for manufacturing a semiconductor structure, comprising:

[0029] A first chip and a second chip are provided; the first chip has a first pad, and the second chip has a second pad and metal bumps located on the second pad;

[0030] A first insulating layer is formed on the first chip; a first cavity is provided in the first insulating layer, and the first cavity is located around the first pad;

[0031] A second insulating layer is formed on the second chip; a second cavity is provided in the second insulating layer, and the second cavity is located around the metal bump;

[0032] The metal bumps are bonded to the first pad so that the first cavity and the second cavity are connected to form a cavity, and the metal bumps fill the cavity.

[0033] In some embodiments, forming a first insulating layer on the first chip includes:

[0034] A first insulating material layer is formed to fill the gap between adjacent first pads and cover the first pads;

[0035] The first insulating material layer is etched to form the first cavity; the remaining first insulating material layer serves as the first insulating layer.

[0036] The first cavity protrudes from the first pad and exposes the first pad.

[0037] In some embodiments, forming a second insulating layer on the second chip includes:

[0038] A second insulating material layer is formed to fill the gap between adjacent second pads;

[0039] The second insulating material layer is etched to form the second cavity; the remaining second insulating material layer serves as the second insulating layer.

[0040] The second cavity exposes a portion of the sidewall of the metal bump.

[0041] In some embodiments, etching the second insulating material layer to form the second cavity includes:

[0042] The second insulating material layer is subjected to a first etching process to form a first sub-cavity;

[0043] A second etching process is performed on the remaining second insulating material layer through the first sub-cavity to form a second sub-cavity; the first sub-cavity exposes part of the sidewall of the metal bump, and a portion of the second insulating material layer is retained between the second sub-cavity and the second pad.

[0044] In some embodiments, the method of manufacturing the semiconductor structure further includes, prior to bonding the metal bumps to the first pad:

[0045] Air-absorbing material layers are formed on the first insulating layer and the second insulating layer, respectively;

[0046] The hardness of the air-absorbing material layer is less than that of the first insulating layer and the second insulating layer.

[0047] In some embodiments, the material of the first insulating layer is the same as the material of the second insulating layer, and the hardness of the first insulating layer is less than the hardness of the inorganic insulating layer.

[0048] The semiconductor structure and its manufacturing method provided in this application can have at least the following beneficial effects:

[0049] The semiconductor structure and manufacturing method provided in this application involve an insulating layer disposed between a first chip and a second chip. This insulating layer contains a first cavity surrounding a first pad and a second cavity surrounding a metal bump, such that the first and second cavities are interconnected and together form a cavity. In subsequent processes, the molten metal bumps can only flow within this cavity, thus preventing short circuits between adjacent metal bumps and effectively improving the production yield and reliability of the semiconductor structure. Furthermore, the molten metal bumps flowing within the cavity eventually fill it, preventing localized collapse of the metal bumps and resulting in high structural stability of the semiconductor structure. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this application;

[0052] Figure 2 A schematic flowchart of step S200 in a method for manufacturing a semiconductor structure provided in some embodiments of this application;

[0053] Figure 3 A schematic flowchart of step S300 in a method for manufacturing a semiconductor structure provided in some embodiments of this application;

[0054] Figure 4A schematic flowchart of step S320 in a method for manufacturing a semiconductor structure provided in some embodiments of this application;

[0055] Figure 5 Figure (a) is a schematic cross-sectional view of the second chip in step S100 of the semiconductor structure manufacturing method provided in some embodiments of this application; Figure 5 Figure (b) is a schematic cross-sectional view of the first chip in step S100 of the method for manufacturing a semiconductor structure provided in some embodiments of this application;

[0056] Figure 6 Figure (a) is a schematic cross-sectional view of the structure obtained in step S310 of the semiconductor structure manufacturing method provided in some embodiments of this application; Figure 6 Figure (b) is a schematic cross-sectional view of the structure obtained in step S210 of the semiconductor structure manufacturing method provided in some embodiments of this application;

[0057] Figure 7 A schematic cross-sectional view of the structure obtained in step S220 of the semiconductor structure manufacturing method provided in some embodiments of this application;

[0058] Figure 8 A schematic cross-sectional view of the structure obtained after forming an initial second cavity in a method for manufacturing a semiconductor structure according to some embodiments of this application;

[0059] Figure 9 A schematic cross-sectional view of the structure obtained in step S320 of the semiconductor structure manufacturing method provided in some embodiments of this application;

[0060] Figure 10 A schematic cross-sectional view of the structure obtained before bonding the metal bumps to the first pad in the manufacturing method of the semiconductor structure provided in some embodiments of this application;

[0061] Figure 11 A schematic cross-sectional view of the structure obtained in step S400 of the semiconductor structure manufacturing method provided in some embodiments of this application; Figure 11 This is also a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this application;

[0062] Figure 12 A schematic cross-sectional view of the structure obtained in step S220 of the method for manufacturing a semiconductor structure provided in other embodiments of this application;

[0063] Figure 13 A schematic cross-sectional view of the structure obtained in step S321 of the semiconductor structure manufacturing method provided in some embodiments of this application;

[0064] Figure 14A schematic cross-sectional view of the structure obtained in step S322 of the semiconductor structure manufacturing method provided in some embodiments of this application; Figure 14 This is also a schematic diagram of the cross-sectional structure of the second chip in the semiconductor structure provided in some embodiments of this application;

[0065] Figure 15 A schematic cross-sectional view of the structure obtained before bonding the metal bumps to the first pad in a method for manufacturing a semiconductor structure provided in other embodiments of this application;

[0066] Figure 16 A schematic cross-sectional view of the structure obtained in step S400 of the method for manufacturing a semiconductor structure provided in other embodiments of this application; Figure 16 This is also a cross-sectional schematic diagram of the semiconductor structure provided in some other embodiments of this application;

[0067] Figure 17 A schematic cross-sectional view of the structure obtained after forming a gas-getting material layer in the manufacturing method of a semiconductor structure provided in some embodiments of this application;

[0068] Figure 18 A schematic cross-sectional view of the structure obtained in step S400 after forming a getter material layer in a method for manufacturing a semiconductor structure according to some embodiments of this application; Figure 18 This is also a cross-sectional schematic diagram of the semiconductor structure provided in some other embodiments of this application;

[0069] Figure 19 A schematic cross-sectional view of the structure obtained in step S400 after forming the getter material layer in a method for manufacturing a semiconductor structure provided in other embodiments of this application; Figure 19 This is also a cross-sectional schematic diagram of the semiconductor structure provided in some other embodiments of this application.

[0070] Explanation of reference numerals in the attached figures:

[0071] 1. First chip; 11. First pad; 2. Second chip; 21. Second pad; 22. Metal bump; 3. Insulating layer; 31. First insulating layer; 310. First insulating material layer; C1. First cavity; 32. Second insulating layer; 320. Second insulating material layer; C2. Second cavity; C21. First sub-cavity; C22. Second sub-cavity; C. Cavity; 4. Getter material layer. Detailed Implementation

[0072] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0074] It should be understood that when an element or layer is referred to as "on" or "adjacent to," it may be directly on or adjacent to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms "first" and "second" may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first chip may be referred to as a second chip, and similarly, a second chip may be referred to as a first chip; the first chip and the second chip are different chips.

[0075] Spatial relation terms such as "above" or "on top of" are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that spatial relation terms include not only the orientation shown in the figure, but also different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "above" will be oriented "below" other elements or features. Therefore, the exemplary term "above" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0076] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0077] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Furthermore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0078] This application provides a method for manufacturing a semiconductor structure according to some embodiments.

[0079] Please see Figure 1 In some embodiments, the method for manufacturing the semiconductor structure may specifically include the following steps:

[0080] S100: Provides a first chip and a second chip. The first chip has a first pad, and the second chip has a second pad and metal bumps on the second pad.

[0081] S200: A first insulating layer is formed on the first chip. A first cavity is provided within the first insulating layer, and the first cavity is located around the first pad.

[0082] S300: A second insulating layer is formed on the second chip. A second cavity is provided within the second insulating layer, and the second cavity is located around the metal bump.

[0083] S400: Bond metal bumps to the first pad so that the first cavity and the second cavity are connected to form a cavity, and the metal bumps fill the cavity.

[0084] In the semiconductor structure manufacturing method provided in the above embodiments, a first insulating layer is formed on a first chip, and the first insulating layer has a first cavity disposed around a first pad. A second insulating layer is formed on a second chip, and the second insulating layer has a second cavity disposed around a metal bump. When the metal bump is bonded to the first pad, the first cavity and the second cavity are connected and can jointly form a cavity. Thus, during the bonding of the metal bump to the first pad, the melted metal bump can only flow within this cavity, thereby avoiding short circuits between adjacent metal bumps and effectively improving the production yield and reliability of the prepared semiconductor structure. Furthermore, the melted metal bump flows within the cavity and eventually fills it, thus avoiding the problem of local collapse of the metal bump and giving the prepared semiconductor structure high structural stability.

[0085] Please see Figure 2 In some embodiments, step S200, which involves forming a first insulating layer on the first chip, may specifically include the following steps:

[0086] S210: Form a first insulating material layer that fills the gap between adjacent first pads and covers the first pads.

[0087] S220: The first insulating material layer is etched to form a first cavity, and the retained first insulating material layer is used as the first insulating layer.

[0088] In the semiconductor structure manufacturing method provided in the above embodiments, the first cavity protrudes from the first pad and exposes the first pad.

[0089] Please see Figure 3 In some embodiments, step S300, which involves forming a second insulating layer on the second chip, may specifically include the following steps:

[0090] S310: Form a second insulating material layer that fills the gap between adjacent second pads.

[0091] S320: The second insulating material layer is etched to form a second cavity, and the remaining second insulating material layer is used as the second insulating layer.

[0092] In the semiconductor structure manufacturing method provided in the above embodiments, the second cavity exposes a portion of the sidewall of the metal bump.

[0093] Please see Figure 4 In some embodiments, step S320 involves etching the second insulating material layer to form the second cavity, which may specifically include the following steps:

[0094] S321: Perform a first etching process on the second insulating material layer to form a first sub-cavity.

[0095] S322: The remaining second insulating material layer is etched through the first sub-cavity to form the second sub-cavity.

[0096] In the semiconductor structure manufacturing method provided in the above embodiments, the first sub-cavity exposes part of the sidewall of the metal bump, and a part of the second insulating material layer is retained between the second sub-cavity and the second pad.

[0097] It should be understood that, although Figures 1 to 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1 to 4At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0098] To more clearly illustrate the manufacturing methods in some of the above embodiments, please refer to the following... Figures 5 to 19 Understand some embodiments of this application.

[0099] Please see Figure 5 Figure (a) and Figure 5 In Figure (b), in step S100, a first chip 1 and a second chip 2 are provided.

[0100] Specifically, such as Figure 5 As shown in Figure (b), a first pad 11 may be provided on the first chip 1; as Figure 5 As shown in Figure (a), the second chip 2 may have a second pad 21 and a metal bump 22 located on the second pad 21.

[0101] This application does not specifically limit the method of forming the metal bump 22 on the second pad 21. As an example, the metal bump 22 can be formed in the following way, such as by electroplating.

[0102] This application does not specifically limit the material of the metal bump 22. As an example, the material of the metal bump 22 may include, but is not limited to, tin (Sn).

[0103] In some embodiments, the metal bump 22 is made of tin.

[0104] In the semiconductor structure manufacturing method provided in the above embodiments, since the metal bump 22 is made of tin, tin will not form spherical shapes during the process of forming the metal bump 22 (for example, forming the metal bump 22 on the second pad 21 by electroplating). Furthermore, since the metal bump is made of pure tin, the tin content can be increased without changing the height of the metal bump 22, thereby increasing redundancy against factors such as warpage and surface unevenness, and ultimately improving the product structure stability and reliability.

[0105] In some embodiments, a vacuum can be evacuated within the process chamber to reduce gas pressure during the formation of the metal bump 22. This reduces the generation of voids in the resulting structure, thereby further improving the production yield and reliability of the fabricated semiconductor structure.

[0106] It should be noted that the number of second pads 21 on the second chip 2 can be multiple, and these pads 21 are arranged at intervals on the second chip 2. The interval between adjacent second pads 21 can be adjusted adaptively according to actual needs. Metal bumps 22 are correspondingly provided with the second pads 21; therefore, the number of metal bumps 22 can also be multiple, and these bumps 22 are arranged at intervals. It can be understood that the interval between adjacent metal bumps 22 can be adjusted by adjusting the interval between adjacent second pads 21.

[0107] In some embodiments, the pitch between adjacent second pads 21 is less than or equal to 10 μm.

[0108] In the semiconductor structure manufacturing method provided in the above embodiments, on the second chip 2, the interval between adjacent second pads 21 is less than or equal to 10 μm, so the interval between adjacent metal bumps 22 is also less than or equal to 10 μm. The arrangement of metal bumps 22 has a high density, which can effectively utilize the space on the second chip 2, thereby improving the space utilization rate of the structure obtained by the manufacturing method.

[0109] Please see Figure 6 Figure (b) in the middle and Figure 7 In step S200, a first insulating layer 31 is formed on the first chip 1.

[0110] like Figure 7 As shown, a first cavity C1 may be provided in the first insulating layer 31, and the first cavity C1 may be located on the periphery of the first pad 11.

[0111] In some embodiments, step S200 forms a first insulating layer 31 on the first chip 1, which can specifically be manifested as steps S210 to S220.

[0112] In step S210, as Figure 6 As shown in Figure (b), a first insulating material layer 310 is formed to fill the gap between adjacent first pads 11 and cover the first pads 11.

[0113] In step S220, as Figure 7 As shown, the first insulating material layer 310 is etched to form the first cavity C1.

[0114] In the semiconductor structure manufacturing method provided in the above embodiments, the retained first insulating material layer 310 can be used as the first insulating layer 31. At this time, the first cavity C1 protrudes from the first pad 11, that is, the first insulating layer 31 is higher than the first pad 11, and the first cavity C1 can be used to expose the first pad 11.

[0115] This application does not specifically limit the method of etching the first insulating material layer 310 in step S220. As an example, the first insulating material layer 310 can be etched in the following ways: for example, a patterned photoresist layer is formed on the first insulating material layer 310, and the patterned photoresist layer is used as a mask to perform dry etching, reactive ion etching (RIE) or other etching processes on the first insulating material layer 310 to form the first cavity C1.

[0116] Please see Figure 6 Figure (a) in the middle and Figures 8 to 9 In step S300, a second insulating layer 32 is formed on the second chip 2.

[0117] like Figure 9 As shown, a second cavity C2 may be provided in the second insulating layer 323, and the second cavity C2 may be located on the periphery of the metal bump 22.

[0118] In some embodiments, step S300 forms a second insulating layer 32 on the second chip 2, which may specifically include the following steps S310 to S320.

[0119] In step S310, as Figure 6 As shown in Figure (a), a second insulating material layer 320 is formed to fill the gap between adjacent second pads 21.

[0120] In step S320, as Figures 8 to 9 As shown, the second insulating material layer 320 is etched to form the second cavity C2.

[0121] In the semiconductor structure manufacturing method provided in the above embodiments, the retained second insulating material layer 320 can be used as the second insulating layer 32. At this time, the second cavity C2 can be used to expose part of the sidewall of the metal bump 22, that is, the second insulating layer 32 also contacts part of the metal bump 22, preventing the molten metal bump 22 from flowing upward during bonding, which would reduce the contact amount between the metal bump 22 and the first pad 11.

[0122] This application does not specifically limit the method of etching the second insulating material layer 320 in step S320 to form the second cavity C2.

[0123] Please continue reading. Figures 8 to 9 In some embodiments, the second insulating material layer 320 may be etched in the following manner to form the second cavity C2.

[0124] like Figure 8As shown, the second insulating material layer 320 is etched to form an initial second cavity C2'; the initial second cavity C2' protrudes from the metal bump 22, and the initial second cavity C2' can be used to expose part of the sidewall of the metal bump 22. Figure 9 As shown, the second insulating material layer 320 is etched to remove a portion of its thickness to form the second cavity C2; the remaining thickness of the second insulating material layer 320 away from the second chip 2 is greater than the thickness of the second pad 21, but less than the sum of the thickness of the second pad 21 and the thickness of the metal bump 22.

[0125] This application does not specifically limit the form of etching the second insulating material layer 320 or the form of continuing to etch the second insulating material layer 320. As an example, the form of etching the second insulating material layer 320 and the form of continuing to etch the second insulating material layer 320 may include, but are not limited to, dry etching processes or reactive ion etching processes, etc.

[0126] Please see Figures 10 to 11 In step S400, the metal bump 22 is bonded to the first pad 11 so that the first cavity C1 and the second cavity C2 are connected to form cavity C, and the metal bump 22 fills cavity C.

[0127] Combination Figure 11 It is understood that in the embodiments of this application, the metal bump 22 filling the cavity C means that the metal bump 22 melts and flows in the cavity C, eventually filling the cavity C.

[0128] This application does not specifically limit the method of bonding the metal bump 22 to the first pad 11 in step S400. As an example, thermal compression bonding (TCB) can be used to make the metal of the metal bump 22 atomically bonded to the first pad 11, so as to bond the metal bump 22 to the first pad 11 and realize the three-dimensional stacking of the first chip 1 and the second chip 2.

[0129] It should be noted that the first cavity C1 may expose part of the sidewall of the first pad 11; or the first cavity C1 may expose all the sidewalls of the first pad 11, both are permissible.

[0130] Please see Figure 12 In other embodiments, in step S220, the first insulating material layer 310 may be etched until the top surface of the first chip 1 is exposed, so that the first cavity C1 can expose all the sidewalls of the first pad 11.

[0131] Please see Figures 13 to 14In some other embodiments, the second insulating material layer 320 is etched in step S320 to form the second cavity C2, which may specifically include the following steps S321 to S322.

[0132] In step S321, as Figure 13 As shown, a first etching process is performed on the second insulating material layer 320 to form the first sub-cavity C21.

[0133] In step S322, as Figure 14 As shown, the remaining second insulating material layer 320 is etched through the first sub-cavity C21 to form the second sub-cavity C22.

[0134] In the semiconductor structure manufacturing method provided in the above embodiments, the first sub-cavity C21 can expose part of the sidewall of the metal bump 22, and a portion of the second insulating material layer 320 can be retained between the second sub-cavity C22 and the second pad 21.

[0135] This application does not specifically limit the form of the first etching process or the second etching process. As an example, the first etching process and the second etching process can be, but are not limited to, dry etching processes or reactive ion etching processes, etc.

[0136] Please see Figures 15 to 16 In the semiconductor structure manufacturing method provided in the above embodiments, metal bumps 22 are bonded to the first pad 11 so that the first cavity C1 and the second cavity C2 are connected to form cavity C.

[0137] As an example, the method for manufacturing the semiconductor structure may also include the step of forming a getter material layer.

[0138] Please see Figures 17 to 18 In some embodiments, the air-absorbing material layer 4 may be formed on the first insulating layer 31 and / or the second insulating layer 32, that is: the air-absorbing material layer 4 may be formed on the first insulating layer 31, or the air-absorbing material layer 4 may be formed on the second insulating layer 32, or the air-absorbing material layer 4 may be formed on both the first insulating layer 31 and the second insulating layer 32.

[0139] Please see Figure 19 In other embodiments, the air-absorbing material layer 4 may also be formed on the first chip 1 and / or the second chip 2, that is: the air-absorbing material layer 4 may be formed on the first chip 1, or the air-absorbing material layer 4 may be formed on the second chip 2, or the air-absorbing material layer 4 may be formed on both the first chip 1 and the second chip 2.

[0140] It should be noted that in the semiconductor structure manufacturing method provided in the above embodiments, the getter material layer 4 may have an opening to ensure good contact between the first pad 11 and the first chip 1, and good contact between the second pad 21 and the second chip 2.

[0141] In possible embodiments of this application, the step of forming the air-absorbing material layer 4 is not restricted in order with other steps and can be selected according to actual needs. For example, as shown... Figure 17 As shown, the getter material layer 4 disposed on the first insulating layer 31 and / or the second insulating layer 32 can be formed before the metal bump 22 is bonded to the first pad 11 in step S400.

[0142] This application does not specifically limit the material of the air-absorbing material layer 4. In some embodiments, the hardness of the air-absorbing material layer 4 may be less than the hardness of the first insulating layer 31 and the hardness of the second insulating layer 32.

[0143] In the semiconductor structure manufacturing method provided in the above embodiments, since the hardness of the getter material layer 4 is less than the hardness of the first insulating layer 31 and the second insulating layer 32, the deformation of the getter material layer 4 is smaller than the deformation of the first insulating layer 31 and the second insulating layer 32. This makes the getter material layer 4 have a smaller impact on the overall deformation of the semiconductor structure, thereby further improving the structural stability of the prepared semiconductor structure.

[0144] It should be noted that the semiconductor structure manufacturing method provided in this application can be applied, but is not limited to, the process of producing three-dimensional stacked products using three-dimensional stacking (3DS) technology. Three-dimensional stacked products can be, for example, high-bandwidth memory (HBM).

[0145] It should be noted that this application does not specifically limit the types of the first chip 121 and the second chip 122 provided in step S100. As an example, the first chip 121 and the second chip 122 can be, but are not limited to, logic processing chips, power management integrated circuits (PMICs), memory chips, etc. Among them, logic processing chips can include, but are not limited to, graphics processing unit (GPU) chips, central processing unit (CPU) chips, system-on-chips (SOCs), etc.; memory chips can include, but are not limited to, random access memory (RAM), and RAM can include, but are not limited to, dynamic random access memory (DRAM) or static random access memory (SRAM), etc.

[0146] On the other hand, this application also provides a semiconductor structure according to some embodiments.

[0147] Please continue reading. Figure 11 In some embodiments, the semiconductor structure may include a first chip 1, a second chip 2, and an insulating layer 3.

[0148] The first chip 1 has a first pad 11. The second chip 2 has a second pad 21 and a metal bump 22; wherein the metal bump 22 is located on the surface of the second pad 21 away from the second chip 2 and is bonded to the first pad 11. An insulating layer 3 is located between the first chip 1 and the second chip 2, and the insulating layer 3 has a first cavity C1 and a second cavity C2; wherein the first cavity C1 is located around the first pad 11, and the second cavity C2 is located around the metal bump 22, and the first cavity C1 and the second cavity C2 are connected to form cavity C. The metal bump 22 can fill cavity C.

[0149] In the semiconductor structure provided in the above embodiments, an insulating layer 3 is disposed between the first chip 1 and the second chip 2. This insulating layer 3 has a first cavity C1 disposed around the first pad 11 and a second cavity C2 disposed around the metal bump 22, such that the first cavity C1 and the second cavity C2 are connected and together form cavity C. Thus, in subsequent processes, after the metal bump 22 melts, it can only flow within this cavity C, thereby avoiding short circuits between adjacent metal bumps 22 and effectively improving the production yield and reliability of the semiconductor structure. Furthermore, after the metal bump 22 melts and flows within the cavity C, it eventually fills the cavity C, thereby avoiding the problem of local collapse of the metal bump 22 and giving the semiconductor structure high structural stability.

[0150] This application does not specifically limit the type of the first chip 121 and the second chip 122. As an example, the first chip 121 and the second chip 122 may include, but are not limited to, logic processing chips, power management integrated circuits (PMICs), memory chips, etc.

[0151] It should be noted that the number of second pads 21 on the second chip 2 can be multiple, and these pads 21 are arranged at intervals on the second chip 2. The interval between adjacent second pads 21 can be adjusted adaptively according to actual needs. Metal bumps 22 are correspondingly provided with the second pads 21; therefore, the number of metal bumps 22 can also be multiple, and these bumps 22 are arranged at intervals. It can be understood that the interval between adjacent metal bumps 22 can be adjusted by adjusting the interval between adjacent second pads 21.

[0152] In some embodiments, the pitch between adjacent second pads 21 is less than or equal to 10 μm.

[0153] In the semiconductor structure provided in the above embodiments, the spacing between adjacent second pads 21 on the second chip 2 is less than or equal to 10 μm, and therefore the spacing between adjacent metal bumps 22 is also less than or equal to 10 μm. The arrangement of the metal bumps 22 has a high density, which can effectively utilize the space on the second chip 2, thereby improving the space utilization rate of the structure obtained by the manufacturing method.

[0154] Please continue reading. Figure 11 In some embodiments, the bottom surface of the first cavity C1 is higher than the contact surface between the first pad 11 and the first chip 1. That is, during bonding, the metal bump 22 will not directly contact the first chip 1, thus preventing the metal bump 22 from affecting the first chip 1.

[0155] In some embodiments, the bottom surface of the first cavity C1 is higher than the contact surface between the first pad 11 and the first chip 1, and the bottom surface of the first cavity C1 is lower than the surface of the first pad 11 that is away from the first chip 1.

[0156] Please continue reading. Figure 11 In some embodiments, the distance between the bottom surface of the second cavity C2 and the surface of the metal bump 22 away from the second pad 21 can be less than the height of the metal bump 22. That is, during bonding, when the metal bump 22 fills the second cavity C2, the metal bump 22 will not contact the second chip 2, thus preventing the metal bump 22 from affecting the second chip 2.

[0157] Please continue reading. Figure 11 In some embodiments, the insulating layer 3 may specifically include a first insulating layer 31 located on the first chip 1 and a second insulating layer 32 located on the second chip 2.

[0158] In some embodiments, such as Figure 11 As shown, the first pad 11 and the first cavity C1 are located within the first insulating layer 31, while the second pad 21 and the second cavity C2 are located within the second insulating layer 32.

[0159] Please continue reading. Figures 18 to 19 In some embodiments, the semiconductor structure may also include a getter material layer 4.

[0160] In the semiconductor structure provided in the above embodiments, a gas-absorbing material layer 4 is provided. The gas-absorbing material layer 4 can adsorb impurities such as undischarged gas and water vapor, thereby further improving the production yield and reliability of the prepared semiconductor structure.

[0161] As an example, such as Figure 18 As shown, the air-absorbing material layer 4 can be disposed between the first insulating layer 31 and the second insulating layer 32; or, as shown... Figure 19 As shown, the air-absorbing material layer 4 can also be disposed on the first chip 1 and / or the second chip 2.

[0162] It should be noted that the suction material layer 4 can be disposed on the first chip 1 and / or the second chip 2, meaning that the suction material layer 4 can be disposed on the first chip 1, or the suction material layer 4 can be disposed on the second chip 2, or the suction material layer 4 can be disposed on both the first chip 1 and the second chip 2. It should also be noted that, as... Figure 19 As shown, in the semiconductor structure provided in the above embodiment, the getter material layer 4 may have an opening to ensure good contact between the first pad 11 and the first chip 1, and good contact between the second pad 21 and the second chip 2.

[0163] This application does not specifically limit the material of the air-absorbing material layer 4. In some embodiments, the hardness of the air-absorbing material layer 4 may be less than the hardness of the insulating layer 3.

[0164] In the semiconductor structure provided in the above embodiments, since the hardness of the getter material layer 4 is less than that of the insulating layer 3, the deformation of the getter material layer 4 is larger than that of the insulating layer 3. However, since the volume of the getter material layer 4 is smaller than that of the insulating layer 3, the deformation of the getter material layer 4 has a smaller impact on the shape of the overall structure. This makes the influence of the getter material layer 4 on the overall deformation of the semiconductor structure smaller, thereby further improving the structural stability of the prepared semiconductor structure.

[0165] In some embodiments, the material of the air-absorbing material layer 4 may include parylene.

[0166] This application does not specifically limit the material of the insulating layer 3. In some embodiments, the hardness of the insulating layer 3 may be less than that of the inorganic insulating layer.

[0167] It should be noted that in this application, the inorganic insulating layer includes, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), etc.

[0168] As an example, the material of the insulating layer 3 may include, but is not limited to, polymers.

[0169] This application does not specify the specific type of polymer, as long as it is suitable for dry etching; polymers such as polyimide (PI) and benzocyclobutene (BCB) are acceptable.

[0170] In this embodiment, during bonding, a certain pressure needs to be applied to the second chip 2. Then, during the heating process, the metal bumps 22 melt, thereby surrounding the first pad 11. As a result, the height of the metal bumps 22 is reduced. Therefore, this embodiment selects a polymer insulating layer 3, which has a lower hardness than the inorganic insulating layer and is more prone to deformation, thus adapting to the reduced metal bumps 22. If an inorganic insulating layer is selected, its slightly higher hardness and smaller deformation would prevent the metal bumps from filling the entire cavity, resulting in voids and affecting bonding performance.

[0171] Please continue reading. Figure 16 In other embodiments, the second insulating layer 32 may also be located on the sidewall of the second pad 21.

[0172] In the semiconductor structure provided in the above embodiments, the first pad 11 and the first cavity C1 are located within the first insulating layer 31, while the second cavity C2 surrounds the second pad 21, the metal bump 22 and the second insulating layer 32.

[0173] Please combine Figure 14 It is understood that in some embodiments, the second cavity C2 may specifically include a first sub-cavity C21 and a second sub-cavity C22.

[0174] In the semiconductor structure provided in the above embodiments, the metal bump 22 protrudes from the first sub-cavity C21; the second sub-cavity C22 is located between the first sub-cavity C21 and the second chip 2, and the second insulating layer 32 is located between the second sub-cavity C22 and the second pad 21.

[0175] As an example, the width of the first sub-cavity C21 can be greater than the width of the second sub-cavity C22 (the width referred to here can be the dimension in the direction parallel to the first chip 1).

[0176] Please continue reading. Figure 14 In some embodiments, the second insulating layer 32 may contact a portion of the metal bump 22.

[0177] Please continue reading. Figure 16 In some embodiments, the first insulating layer 31 can extend into the first sub-cavity C21 through the second sub-cavity C22 to contact the second insulating layer 32, so as to jointly form the insulating layer 3 located between the first chip 1 and the second chip 2.

[0178] Please continue reading. Figure 16 In some embodiments, the metal bump 22 may fill the first cavity C1 and part of the first sub-cavity C21.

[0179] This application does not specifically limit the material of the first pad 11. As an example, the material of the first pad 11 may include, but is not limited to, copper (Cu), nickel (Ni), etc., or combinations thereof. This application also does not specifically limit the material of the second pad 21. As an example, the material of the second pad 21 may be the same as or similar to the material of the first pad 11.

[0180] This application does not specifically limit the material of the metal bump 22. As an example, the material of the metal bump 22 may include, but is not limited to, tin (Sn).

[0181] In some embodiments, the metal bump 22 is made of tin.

[0182] In the semiconductor structure provided in the above embodiments, since the metal bump 22 is made of tin, the tin will not form spherical shapes during the process of forming the metal bump 22 (for example, forming the metal bump 22 on the second pad 21 by electroplating). Furthermore, since the metal bump is made of pure tin, the tin content can be increased without changing the height of the metal bump 22, thereby increasing redundancy against factors such as warpage and surface unevenness, and ultimately improving the product's structural stability and reliability.

[0183] It should be noted that the semiconductor structure provided in this application may include, but is not limited to, three-dimensional stacked products fabricated using three-dimensional stacking (3DS) technology, such as high-bandwidth memory (HBM). Furthermore, the types of the first chip 121 and the second chip 122 in the semiconductor structure provided in this application are not specifically limited. As an example, both the first chip 121 and the second chip 122 may include, but are not limited to, logic processing chips, power management integrated circuits (PMICs), memory chips, etc. Among them, logic processing chips may include, but are not limited to, graphics processing unit (GPU) chips, central processing unit (CPU) chips, system-on-chip (SOC) chips, etc.; memory chips may include, but are not limited to, random access memory (RAM), and RAM may include, but is not limited to, dynamic random access memory (DRAM) or static random access memory (SRAM), etc.

[0184] It should also be noted that the semiconductor structure manufacturing methods in the embodiments of this application can all be used to prepare the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can learn about the technical content of the present invention.

[0185] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: First chip; the first chip is provided with a first solder pad; The second chip; the second chip is provided with a second pad and a metal bump; the metal bump is located on the surface of the second pad away from the second chip and is bonded to the first pad; An insulating layer is located between the first chip and the second chip; the insulating layer has a first cavity and a second cavity, the first cavity is located around the first pad, the second cavity is located around the metal bump, and the first cavity and the second cavity are connected to each other to form a cavity together; The metal bumps fill the cavity; The insulating layer includes: A first insulating layer is located on the first chip, and the first pad and the first cavity are located within the first insulating layer; the bottom surface of the first cavity is higher than the contact surface between the first pad and the first chip. The second insulating layer is located on the sidewall of the second pad, and the second cavity surrounds the second pad, the metal bump and the second insulating layer; The second cavity includes: A first sub-cavity, wherein the metal bump protrudes from the first sub-cavity, and the first sub-cavity exposes a portion of the sidewall of the metal bump; The second sub-cavity is located between the first sub-cavity and the second chip, and the second insulating layer is located between the second sub-cavity and the second pad; The width of the first sub-cavity is greater than the width of the second sub-cavity.

2. The semiconductor structure according to claim 1, characterized in that, The distance between the bottom surface of the second cavity and the surface of the metal bump away from the second pad is less than the height of the metal bump.

3. The semiconductor structure according to claim 1, characterized in that, The hardness of the insulating layer is less than that of the inorganic insulating layer, and the material of the insulating layer includes polymers.

4. The semiconductor structure according to claim 3, characterized in that, A gas-absorbing material layer is further disposed between the first insulating layer and the second insulating layer; the hardness of the gas-absorbing material layer is less than the hardness of the insulating layer.

5. The semiconductor structure according to claim 1, characterized in that, The first insulating layer extends through the second sub-cavity into the first sub-cavity to contact the second insulating layer.

6. The semiconductor structure according to claim 1, characterized in that, The metal bumps fill the first cavity and part of the first sub-cavity.

7. A method for manufacturing a semiconductor structure, characterized in that, include: A first chip and a second chip are provided; the first chip has a first pad, and the second chip has a second pad and metal bumps located on the second pad; A first insulating layer is formed on the first chip; a first cavity is provided in the first insulating layer, and the first cavity is located around the first pad; A second insulating layer is formed on the second chip; a second cavity is provided in the second insulating layer, and the second cavity is located around the metal bump; The metal bumps are bonded to the first pads so that the first cavity and the second cavity are connected to form a cavity, and the metal bumps fill the cavity. The first insulating layer is formed on the first chip, including: A first insulating material layer is formed to fill the gap between adjacent first pads and cover the first pads; The first insulating material layer is etched to form the first cavity; the remaining first insulating material layer serves as the first insulating layer. Wherein, the first cavity protrudes beyond the first pad and exposes the first pad; the bottom surface of the first cavity is higher than the contact surface between the first pad and the first chip; The second insulating layer is formed on the second chip, including: A second insulating material layer is formed to fill the gap between adjacent second pads; The second insulating material layer is etched to form the second cavity, and the remaining second insulating material layer is used as the second insulating layer. The process of etching the second insulating material layer to form the second cavity includes: The second insulating material layer is subjected to a first etching process to form a first sub-cavity; A second etching process is performed on the remaining second insulating material layer through the first sub-cavity to form a second sub-cavity; the first sub-cavity exposes part of the sidewall of the metal bump, and a portion of the second insulating material layer is retained between the second sub-cavity and the second pad.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, Before bonding the metal bumps to the first pad, the method of manufacturing the semiconductor structure further includes: Air-absorbing material layers are formed on the first insulating layer and the second insulating layer, respectively; The hardness of the air-absorbing material layer is less than that of the first insulating layer and the second insulating layer.

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