A power-on reset circuit based on LDO

Abstract

The present invention discloses a power-on reset circuit based on LDO, which belongs to the field of integrated circuits, including an operational amplifier AMP, a logic module, resistors R1-R6, switches SW1-SW2, PMOS tubes M0-M2, PMOS tube M4, NMOS tube M3, and a comparator CMP; in the present invention, the addition of NMOS tube M3 not only overcomes the shortcomings of the traditional capacitive POR circuit that the power-on speed is slow and the reset signal cannot be correctly generated when the power is quickly lost, but also avoids the phenomenon of erroneous triggering when the voltage is too low. The use of two-way switches provides a hysteresis voltage in the voltage rising and falling sections, so that the circuit will not generate an erroneous reset signal when it is disturbed, greatly improving the stability of the circuit. The use of LDO avoids the use of triodes in the bandgap POR circuit and reduces the circuit area. The overall structure uses a simple LDO, two switches and a comparator to generate a reliable reset signal, and the circuit structure is simple and practical.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a power-on reset circuit based on LDO. Background Art

[0002] The POR (power-on reset) circuit is used to provide a power-on reset signal to the chip. Before the power supply is stable, the POR outputs a reset signal to put the chip in a reset state. After the power supply is stable, the reset signal is released and the chip can enter the normal working mode. LDO is a low dropout linear regulator that can convert a fluctuating voltage into an accurate, stable voltage that is independent of load changes.

[0003] The traditional POR circuit uses capacitors to sample the change of power supply voltage. When the power supply rise time is long, the reset pulse may not be generated; when the power supply is quickly powered off, the charge stored on the capacitor cannot be released quickly, which will cause the secondary reset to fail and the circuit to not work properly. Another traditional POR circuit that uses Bandgap to provide a reference level for the reset signal has a simple structure, but uses a transistor, resulting in a large circuit area. Therefore, a reliable and low-cost POR circuit must be designed to enable the chip to enter the correct working state. Summary of the invention

[0004] The purpose of the present invention is to provide a power-on reset circuit based on LDO to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a power-on reset circuit based on LDO, including an operational amplifier AMP, a logic module, resistors R1-R6, switches SW1-SW2, PMOS tubes M0-M2, PMOS tube M4, NMOS tube M3, and a comparator CMP;

[0006] The source terminals of the PMOS tubes M0, M1, M2, and M4 are all connected to the power supply voltage VDD, and the gate terminals of the PMOS tubes M0, M1, M2, and NMOS tube M3 are interconnected;

[0007] The drain and gate of the PMOS tube M0 are connected to the first end of the resistor R6, and the second end of the resistor R6 is grounded; the drain of the PMOS tube M1 is grounded through the resistor R4 and the resistor R5 in sequence;

[0008] The drain end of the PMOS tube M2 is connected to the drain end of the NMOS tube M3, the source end of the NMOS tube M3 is connected to the negative input end of the operational amplifier AMP and the first end of the resistor R1, and the second end of the resistor R1 is grounded;

[0009] The output terminal of the operational amplifier AMP is connected to the gate terminal of the PMOS tube M4, and the drain terminal of the PMOS tube M4 is grounded through the resistor R2 and the resistor R3 in sequence; the positive input terminal of the operational amplifier AMP is connected between the resistor R2 and the resistor R3;

[0010] The positive input terminal of the comparator CMP is connected to the drain terminal of the PMOS tube M4, the negative input terminal is connected to the two ends of the resistor R4 through switches SW1 and SW2, and the output terminal is connected to the logic module;

[0011] The logic module generates a switch switching logic to control switches SW1 and SW2 according to the output result of the comparator CMP, and outputs a power-on reset signal.

[0012] The present invention provides a power-on reset circuit based on LDO, which utilizes the characteristics of LDO such as fast voltage regulation and fast response speed, and provides a power-on reset signal to the chip according to the specific conditions of the LDO output voltage. In the present invention, the addition of NMOS tube M3 not only overcomes the shortcomings of the traditional capacitive POR circuit that the power-on speed is slow and the reset signal cannot be correctly generated when the power is quickly lost, but also avoids the phenomenon of erroneous triggering when the voltage is too low. The use of two-way switches provides hysteresis voltage in the voltage rise and fall sections, so that the circuit will not generate erroneous reset signals when it is disturbed, greatly improving the stability of the circuit. The use of LDO avoids the use of triodes in the bandgap POR circuit and reduces the circuit area. The overall structure uses a simple LDO, two switches and a comparator to generate a reliable reset signal, and the circuit structure is simple and practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention provides a schematic diagram of the structure of a power-on reset circuit based on LDO.

[0014] Figure 2 The present invention provides a schematic diagram of power-on and power-off simulation of a power-on reset circuit based on LDO. DETAILED DESCRIPTION

[0015] The following is a further detailed description of a power-on reset circuit based on LDO proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0016] The present invention provides a power-on reset circuit based on LDO, the structure of which is as follows Figure 1 As shown, it includes an operational amplifier AMP, a logic module (LOGIC), resistors R1-R6, switches SW1-SW2, PMOS tubes M0-M2, a PMOS tube M4, an NMOS tube M3, and a comparator CMP.

[0017] VDD is the power supply voltage, and the operational amplifier AMP, resistors R2, R3 and PMOS tube M4 form the LDO circuit. PMOS tube M1, resistors R4, R5 and switches SW1, SW2 are used to generate the comparison level compared with VREF when the power supply voltage is powered on and powered off. At the same time, the two different comparison voltages generated by the switch switching play a hysteresis effect to avoid false triggering caused by glitches. The comparator CMP is used to compare the size of VREF and VCMPH and VCMPL. The logic module generates the switch switching logic and the power-on reset signal LDO_OK according to the output result of the comparator CMP, where VCMPH is the comparison level when powered on, and VCMPL is the comparison level when powered off. PMOS tube M0 and resistor R6 sense the change of the power supply voltage VDD and generate the bias voltage and current of PMOS tube M2 and NMOS tube M3. PMOS tube M2, NMOS tube M3 and resistor R1 generate the input reference voltage of LDO, which is fed back to generate VREF after input into LDO.

[0018] When the power supply voltage VDD is normal, the LDO output voltage and switch output voltage are:

[0019]

[0020] V CMPH =I M1 ×(R 4 +R 5 ),SW 2 _EN=1,SW 1 _EN=0(2)

[0021] V CMPL =I M1 ×R 5 ,SW 2 _EN=0,SW 1 _EN=1(3)

[0022] Among them, SW1_EN is the enable control signal of switch SW1. When SW1_EN=1, switch SW1 is turned on, and when SW1_EN=0, switch SW1 is turned off; SW2_EN is the enable control signal of switch SW2. When SW2_EN=1, switch SW2 is turned on, and when SW2_EN=0, switch SW2 is turned off.

[0023] The working process of the circuit is described as follows:

[0024] (1) During the power-on process of VDD:

[0025] (1.1) When VDD < |Vth(M0)|, where Vth(M0) is the threshold voltage of PMOS transistor M0, there is no current in the entire circuit, VREF = VCMP = 0V, and LDO_OK = 0;

[0026] (1.2) When VDD < |Vth(M0)| + Vth(M3), where Vth(M3) is the threshold voltage of NMOS transistor M3, switch SW2 is turned on and SW1 is turned off. At this time, NMOS transistor M3 is cut off, VREF = 0V, VCMP = VCMPH, SW2_EN = 1, SW1_EN = 0, and LDO_OK = 0;

[0027] (1.3) When VDD > |Vth(M0)| + Vth(M3), NMOS transistor M3 is turned on, current is generated, a voltage drop starts to occur across resistor R1, and VREF starts to be generated and gradually rises. When VREF rises and VREF < VCMPH, SW2_EN = 1, SW1_EN = 0, and LDO_OK = 0. When VDD continues to rise until VREF > VCMPH, SW2_EN = 0, SW1_EN = 1, VCMP = VCMPL, and LDO_OK = 1.

[0028] (2) During the power-down process of VDD:

[0029] (2.1) When VREF < VCMPL, SW2_EN = 1, SW1_EN = 0, and LDO_OK = 0;

[0030] The power-on and power-down simulation results of this circuit are as follows Figure 2 as shown.

[0031] The present invention utilizes the voltage regulation characteristics and fast response speed of the LDO to quickly and accurately generate the reference level required for the generation of the reset signal. At the same time, in the circuit structure proposed by the present invention, NMOS transistor M3 ensures that when the power supply is powered on too slowly or the power supply voltage is too low, the output of the power-on reset circuit is always at a low level, avoiding the incorrect generation of the reset signal. Switches SW1 and SW2 switch different comparison levels during power-on and power-down, which can provide a hysteresis voltage, avoiding the possible false triggering caused by sudden spikes when the output voltage of the LDO is normal and generating an incorrect reset signal, thus ensuring the correct generation of the POR signal. Compared with the traditional structure, the circuit structure proposed by the present invention is simple, has a small area and high stability.

[0032] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A power-on reset circuit based on LDO, characterized in that: It includes an operational amplifier AMP, a logic module, resistors R1-R6, switches SW1-SW2, PMOS tubes M0-M2, PMOS tube M4, NMOS tube M3, and a comparator CMP; The source terminals of the PMOS tubes M0, M1, M2, and M4 are all connected to the power supply voltage VDD, and the gate terminals of the PMOS tubes M0, M1, M2, and NMOS tube M3 are interconnected; The drain and gate of the PMOS tube M0 are connected to the first end of the resistor R6, and the second end of the resistor R6 is grounded; the drain of the PMOS tube M1 is grounded through the resistor R4 and the resistor R5 in sequence; The drain end of the PMOS tube M2 is connected to the drain end of the NMOS tube M3, the source end of the NMOS tube M3 is connected to the negative input end of the operational amplifier AMP and the first end of the resistor R1, and the second end of the resistor R1 is grounded; The output terminal of the operational amplifier AMP is connected to the gate terminal of the PMOS tube M4, and the drain terminal of the PMOS tube M4 is grounded through the resistor R2 and the resistor R3 in sequence; the positive input terminal of the operational amplifier AMP is connected between the resistor R2 and the resistor R3; The positive input terminal of the comparator CMP is connected to the drain terminal of the PMOS tube M4, the negative input terminal is connected to the two ends of the resistor R4 through switches SW1 and SW2, and the output terminal is connected to the logic module; The logic module generates a switch switching logic to control switches SW1 and SW2 according to the output result of the comparator CMP, and outputs a power-on reset signal.

Images