Bus controller module verification method, system, program product, device and medium

Abstract

The present invention discloses a bus controller module verification method, system, program product, device and medium, relates to the field of embedded industrial control technology, and is used to realize the verification of module-level CAN bus controller. In view of the problems of traditional scheme verification and high learning cost, a bus controller module verification method is provided, which can directly capture the bus signal value from the CAN bus based on the CAN protocol and organize it into a complete data frame. Based on this, the transmission frame information sent by the sending node, the bus frame information captured from the CAN bus during the data frame transmission process, and the receiving frame information obtained from the receiving node can be determined by pre-configured parameters, and a three-party full match can be achieved, and the verification of two bus controller modules can be realized at the same time, and the verification accuracy is higher than that of the two-party verification. In addition, in this method, there is no need to use the VIP of the CAN bus controller, which greatly reduces the verification and learning costs.

Description

Technical Field

[0001] The present invention relates to the field of embedded industrial control, and in particular to a bus controller module verification method, system, program product, device and medium. Background Art

[0002] The Controller Area Network (CAN) bus is a serial data communication bus that is widely used in the field of embedded industrial control, providing a stable and high-speed data exchange channel for data exchange between terminal controllers, sensors and other IoT devices. Considering the high commercial value of the CAN bus and the considerations of chip manufacturers based on scenarios such as industrial control edge computing, the integration of CAN bus controller modules in commercial system-on-chips (SoCs) has become a mainstream choice.

[0003] The traditional CAN bus controller module verification solution uses a preconfigured CAN bus controller VIP (Verfication IP, verification IP; IP stands for Intellectual Property) as a verification reference model. The verification platform implements a CAN communication network that includes at least two nodes: a CAN bus controller module and a CAN bus controller VIP. The verification platform sends a test stimulus to the CAN bus controller module, and the CAN bus controller module node is controlled to broadcast frames to the above CAN communication network. The CAN bus controller VIP node listens to and normally receives the broadcast frames in the CAN communication network, and parses out the relevant information of the frame. The verification platform compares the configuration information in the test stimulus with the frame-related information parsed in the verification reference model to complete the entire verification process.

[0004] Verification of the CAN bus controller module based on the above traditional method requires the use of a dedicated CAN bus controller VIP, which results in excessively high actual verification costs. In addition, it is necessary to clarify the configuration and usage procedures of the VIPs provided by different manufacturers, which results in high learning costs for verification personnel and a long chip development cycle.

[0005] Therefore, technicians in this field are in urgent need of a bus controller module verification method to solve the problems of high verification cost, high learning cost, and long chip development cycle in traditional solutions that rely on CAN bus controller VIP implementation. Summary of the invention

[0006] The purpose of the present invention is to provide a bus controller module verification method, system, program product, device and medium to solve the problems of high verification cost, high learning cost, long chip development cycle, etc. in traditional solutions that rely on CAN bus controller VIP implementation.

[0007] In order to solve the above technical problems, the present invention provides a bus controller module verification method, which is applied to a bus verification platform, wherein the bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected via a controller area network bus; wherein one of the bus controller modules to be tested is used as a sending node, and the other bus controller module to be tested is used as a receiving node;

[0008] Methods include:

[0009] Generate pre-configuration parameters through random constraints; wherein the pre-configuration parameters include: baud rate, bit timing parameters and transmission frame information;

[0010] Writing the pre-configuration parameters to the sending node and enabling the sending node to start frame transmission, so that the sending node sends data frames to the receiving node through the controller area network bus according to the pre-configuration parameters;

[0011] Synchronously capturing bus signal values ​​from the controller area network bus according to the baud rate and bit timing parameters;

[0012] Determining bus frame information according to the bus signal value;

[0013] After the data frame is sent, reading the received frame information from the receiving node;

[0014] The transmission frame information, the bus frame information and the reception frame information are fully matched, and a verification result is determined according to the full matching result.

[0015] In a possible embodiment, synchronously capturing bus signal values ​​from the controller area network bus according to the baud rate and bit timing parameters includes:

[0016] Determining a sampling pulse according to the baud rate and the bit timing parameters;

[0017] Performing bit timing synchronization between the sampling pulse and a transmission bus signal in the controller area network bus;

[0018] The bus signal value transmitted in the controller area network bus is sampled according to the sampling pulse after bit timing synchronization.

[0019] In a possible embodiment, the bit timing parameters include: a synchronization segment parameter, a propagation time segment parameter, a first phase buffer segment parameter, and a second phase buffer segment parameter;

[0020] Determining the sampling pulse according to the baud rate and the bit timing parameter includes:

[0021] Determine a pre-scaling coefficient according to the baud rate and the bit timing parameter; wherein the pre-scaling coefficient is the number of clock cycle counts required for the duration corresponding to the minimum time unit in the clock domain determined by the baud rate and the bit timing parameter;

[0022] Using the pre-scaling coefficient as a cyclic count value of a pre-established bit timing counting unit, and using a bus clock signal determined by the baud rate and the bit timing parameter to drive the counting of the bit timing counting unit;

[0023] Whenever the bit timing counting unit completes a cycle, a timing counting plus one signal is sent out to obtain a counting pulse;

[0024] By means of the counting pulse, the counting of the pre-established minimum unit counting unit is promoted;

[0025] When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time segment parameter and the first phase buffer segment parameter, the bus sampling signal is set to obtain the sampling pulse;

[0026] When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time period parameter, the first phase buffer segment parameter and the second phase buffer segment parameter, the count value of the minimum unit counting unit is cleared.

[0027] In a possible embodiment, performing bit timing synchronization between the counting pulse and a transmission bus signal in the controller area network bus includes:

[0028] In the bit timing counting unit, assigning the bus signal value to the 0th bit of a predefined first merging array; wherein the width of the first merging array is 2;

[0029] By using a shift operator, the first merged array is logically shifted left by 1 bit;

[0030] When the bus clock signal is pushed by a rising edge, the bus signal value is assigned to the 0th bit of the first merging array;

[0031] Comparing the value of the first bit of the first merging array with the inverted value of the 0th bit of the first merging array to determine whether a falling edge occurs in the bus waveform of the controller area network bus;

[0032] If a falling edge occurs, the bus falling edge flag signal is set;

[0033] When the bus falling edge flag signal is set, the count value of the minimum unit counting unit is cleared, and then the bus falling edge flag signal is cleared.

[0034] In a possible embodiment, sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after bit timing synchronization includes:

[0035] Whenever the bus sampling signal is set, sampling the bus signal value transmitted in the controller area network bus;

[0036] When it is detected that the interrupt signal of the receiving node is set, the sampling of the bus signal value is stopped;

[0037] The interrupt signal is set by the receiving node after the data frame is transmitted.

[0038] In a possible embodiment, determining the bus frame information according to the bus signal value includes:

[0039] According to the bit filling mechanism in the controller area network bus protocol, the bus signal value obtained by sampling is subjected to a de-bit filling process to obtain a de-bit filled fixed format frame information queue; wherein the format of the de-bit filled fixed format frame information queue conforms to the data frame format specified by the controller area network bus protocol;

[0040] Extracting data on a specified data bit in the fixed format frame information queue without bit filling according to the data frame format specified by the controller area network bus protocol to determine the bus frame information;

[0041] The bus frame information includes: special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value.

[0042] In a possible embodiment, performing a de-stuffing process on the sampled bus signal value according to a bit stuffing mechanism in a controller area network bus protocol to obtain a fixed format frame information queue after de-stuffing includes:

[0043] When the bus signal value is obtained by sampling, the bus signal value is assigned to the 0th bit of a predefined second merge array; wherein the width of the second merge array is 12;

[0044] Determine whether the values ​​of the first to fifth bits of the second merged array are the same;

[0045] If they are the same, determine whether the values ​​of the first to 11th bits of the second merged array are all "1";

[0046] If all are "1", determine whether the bus signal value obtained by this sampling is "0";

[0047] If it is "0", fill the bus signal value into the 0th bit in the fixed format frame information queue, set the start acquisition frame signal, and reassign the value of the 1st bit to the 5th bit of the second merge array to "11101"; and use the shift operator to logically shift the second merge array left by 1 bit;

[0048] If not all are "1", the second merged array is logically shifted left by 1 bit using a shift operator;

[0049] If they are different, determining whether the start acquisition frame signal is set;

[0050] If the start acquisition frame signal is set, the bus signal value obtained by this sampling is filled into the fixed format frame information queue, and the second merge array is logically shifted left by 1 bit through a shift operator;

[0051] If the start acquisition frame signal is not set, the second merge array is logically shifted left by 1 bit through a shift operator.

[0052] In a possible embodiment, the special identification bit information includes: an extended identifier bit value, a remote transmission request bit value, an alternative remote request bit value, and a reserved bit value;

[0053] According to the data frame format specified by the controller area network bus protocol, extract the data on the specified data bit in the fixed format frame information queue without bit filling to determine that the bus frame information includes:

[0054] Determine whether the format of the data frame to be transmitted this time is a standard format frame or an extended format frame according to the extended identifier bit value on the designated data bit in the fixed format frame information queue;

[0055] Based on the data frame format of this transmission, other special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value are extracted.

[0056] In a possible embodiment, the bus frame information further includes: a cyclic redundancy check value reference sequence;

[0057] Wherein, after determining that the format of the data frame to be transmitted is a standard format frame or an extended format frame, the method further includes:

[0058] Based on the data frame format of this transmission, the frame data starting from the frame start bit to before the cyclic redundancy check value sequence is intercepted as the partial frame information queue to be checked;

[0059] Processing the to-be-checked partial frame information queue through a cyclic redundancy check unit to obtain the cyclic redundancy check value reference sequence;

[0060] The cyclic redundancy check algorithm adopted by the cyclic redundancy check unit is the cyclic redundancy check algorithm specified by the controller area network bus protocol.

[0061] In a possible embodiment, performing full matching on the transmission frame information, the bus frame information, and the reception frame information, and determining the verification result according to the full matching result includes:

[0062] According to the response field slot value in the bus frame information, determine whether the data frame transmitted this time is normally received by the receiving node; if so, perform subsequent verification; if not, return verification failure information and exit this method;

[0063] Fully matching the first special identification bit information in the bus frame information, the sending frame information and the receiving frame information, and outputting a first matching result;

[0064] Check whether the second special identification bit information in the bus frame information complies with the controller area network bus protocol, and output the inspection result; wherein the set of the first special identification bit information and the second special identification bit information is the special identification bit information, and the second special identification bit information includes: an alternative remote request bit value and a reserved bit value;

[0065] Fully matching the frame data lengths and frame data information in the bus frame information, the transmission frame information, and the reception frame information, and outputting a second matching result;

[0066] Matching the cyclic redundancy check value sequence in the bus frame information with the cyclic redundancy check value reference sequence, and outputting a third matching result;

[0067] The verification result is determined according to the first matching result, the inspection result, the second matching result and the third matching result.

[0068] In a possible embodiment, after determining the verification result according to the first matching result, the second matching result, the inspection result and the third matching result, the method further includes:

[0069] If any of the first matching result, the inspection result, the second matching result and the third matching result is a failure, determining an abnormal position item according to the failure result item; wherein the abnormal position item represents a possible position of the abnormality that caused the failure of this verification;

[0070] The verification failure information including the failed result item and the abnormal position item is returned.

[0071] In order to solve the above technical problems, the present invention also provides a bus controller module verification system, comprising: a bus verification platform and two bus controller modules to be tested;

[0072] The bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected via a controller area network bus; wherein one of the bus controller modules to be tested serves as a sending node, and the other bus controller module to be tested serves as a receiving node;

[0073] The bus verification platform includes: a bus controller reference model, a driver and a receiver;

[0074] Among them, the bus controller reference model is connected to the register of the sending node through the driver; the bus controller reference model is connected to the register of the receiving node through the receiver; the bus controller reference model is used to implement the steps of the bus controller module verification method as described above.

[0075] In order to solve the above technical problem, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the bus controller module verification method as described above when executed by a processor.

[0076] In order to solve the above technical problems, the present invention also provides a bus controller module verification device, comprising:

[0077] Memory for storing computer programs;

[0078] A processor is used to implement the steps of the bus controller module verification method as described above when executing the computer program.

[0079] In order to solve the above technical problem, the present invention also provides a non-volatile storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the bus controller module verification method as described above are implemented.

[0080] The present invention provides a bus controller module verification method, which pregenerates a set of preconfiguration parameters in a random constraint manner, and the preconfiguration parameters contain all parameter data required to complete a data frame transmission process in a CAN bus. Afterwards, the preconfiguration parameters are written into the bus control module to be tested as a sending node to drive the sending node to complete a data frame transmission according to the preconfiguration parameters, and the data frame is sent to the receiving node through the CAN bus. During the data frame transmission process, since the preconfiguration parameters are generated by the bus verification platform and are known to the bus verification platform, the bus verification platform can directly capture the bus signal value from the CAN bus based on the CAN protocol, and organize the bus signal value into a complete data frame transmitted in the CAN bus this time based on the CAN bus protocol and the preconfiguration parameters. In addition, after the data frame transmission is completed, the data frame information obtained by the receiving node is also obtained from the receiving node as the receiving frame information. Based on this, the pre-configured parameters can determine the sending frame information sent by the sending node, the bus frame information captured from the CAN bus during the data frame transmission process, and the receiving frame information obtained from the receiving node, so as to achieve full three-party matching and realize the verification of the two bus controller modules at the same time, and the verification accuracy is higher than that of the two-party verification.

[0081] In addition, in this verification method, the information required for subsequent matching verification can be directly captured from the CAN bus without using the VIP of the CAN bus controller, which greatly reduces the verification and learning costs. Moreover, in this method, one data frame transmission can realize the verification of two CAN bus controller modules. Compared with the traditional solution of verifying one CAN bus controller module through two CAN bus controller VIP nodes, the verification efficiency is higher, which is conducive to further shortening the chip development cycle.

[0082] The bus controller module verification system, program product, device, and non-volatile storage medium provided by the present invention correspond to the above method and have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0084] FIG1 is a structural diagram of a bus controller module verification system provided by the present invention;

[0085] FIG2 is a flow chart of a bus controller module verification method provided by the present invention;

[0086] Figure 3 is a schematic diagram of a data frame format under the CAN bus protocol;

[0087] FIG4 is a flow chart of another bus controller module verification method provided by the present invention;

[0088] FIG5 is a structural diagram of another bus controller module verification system provided by the present invention;

[0089] FIG. 6 is a structural diagram of a bus controller module verification device provided by the present invention. DETAILED DESCRIPTION

[0090] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0091] The core of the present invention is to provide a bus controller module verification method, system, program product, device and medium.

[0092] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0093] In the related art, if one wants to implement module-level verification of a Controller Area Network (CAN) bus controller, a verification environment consisting of two CAN bus controller VIP (Verification IP; IP stands for Intellectual Property) nodes and a CAN bus controller module node to be tested is constructed based on the Universal Verification Methodology (UVM); then, through a preset test sequence, a CAN bus controller VIP node and a CAN bus controller module node to be tested are made to send frames simultaneously, and another CAN bus controller VIP node receives broadcast frames on the bus in succession; and then, the frame information is parsed within the verification platform and compared with the preset test sequence information to complete the entire verification process.

[0094] That is, in the above scheme, the verification of a CAN bus controller module to be tested requires the use of the VIPs of two CAN bus controllers, which serve as nodes of the CAN communication network in the verification environment. The VIP nodes are used to receive frames and parse information to determine whether the functions of the CAN bus controller to be tested are normal. On the one hand, this scheme uses a dedicated CAN bus controller VIP, which will cause the actual verification cost to be too high, and it is necessary to clarify the configuration and use process of the VIP provided by different manufacturers, which makes the learning cost of the verification personnel high and the chip development cycle too long. On the other hand, in order to realize the verification of a CAN bus controller module to be tested, this scheme needs to construct two verification sub-environments for the two CAN bus controller VIPs respectively, which are used to separately configure the VIP nodes of the CAN bus controller, which increases the difficulty of verification and reduces the efficiency of verification.

[0095] Therefore, based on the above problems, the present invention provides a bus controller module verification method, which is applied to a bus verification platform as shown in Figure 1. The bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected through a controller area network bus; one bus controller module to be tested is used as a sending node, and the other bus controller module to be tested is used as a receiving node.

[0096] Furthermore, the method as shown in FIG2 includes:

[0097] S10: Generate pre-configured parameters through random constraints.

[0098] The pre-configured parameters include but are not limited to: baud rate, bit timing parameters and transmission frame information.

[0099] S20: writing the pre-configuration parameters to the sending node, and enabling the sending node to start frame transmission, so that the sending node sends data frames to the receiving node through the controller area network bus according to the pre-configuration parameters.

[0100] S30: Synchronously capture bus signal values ​​from the controller area network bus according to the baud rate and bit timing parameters.

[0101] S40: Determine bus frame information according to the bus signal value.

[0102] S50: After the data frame is sent, the receiving frame information is read from the receiving node.

[0103] S60: Perform full matching on the transmission frame information, the bus frame information and the reception frame information, and determine the verification result according to the full matching result.

[0104] Among them, in step S10, the pre-configuration parameters are generated by random constraints, that is, the parameter configuration of the data frame transmitted between the two bus controller modules to be tested is generated as the basis for this verification. Specifically, the baud rate included in the pre-configuration parameters represents the number of bits sent or received by the CAN bus controller module within 1 second during the data frame transmission process. The bit timing parameters included in the pre-configuration parameters are the corresponding parameters of the CAN bus protocol that divides each transmission bit into 4 timing segments on a time scale, that is, the bit timing parameters include the parameters of the four timing segments of synchronization segment (SS), propagation time segment (PTS), phase buffer segment 1 (PBS1), and phase buffer segment 2 (PBS2).

[0105] Based on the baud rate and bit timing parameters, the following formula can be obtained:

[0106] ;

[0107] Among them, CAN_Baud is the baud rate; SS, PTS, PBS1, and PBS2 are the corresponding parameters of the synchronization segment (SS), propagation time segment (PTS), phase buffer segment 1 (PBS1), and phase buffer segment 2 (PBS2); Tq is the minimum time unit.

[0108] In the above formula, (SS+PTS+PBS1+PBS2)×Tq is the time required for the CAN bus to transmit one bit under the current pre-configured parameters. In addition, let the clock frequency of the clock domain of the CAN bus be f CAN_clk (usually 24MHz), the CAN bus controller can obtain the above Tq time by dividing the clock frequency to achieve the bit timing transmission under the specified baud rate. The division formula is as follows:

[0109] ;

[0110] Wherein, BRP is the pre-division coefficient, which can be used to divide the CAN bus clock to obtain a clock signal that meets the Tq time requirement; T CAN_clk is the clock period of the CAN bus.

[0111] It is not difficult to see from the above formula that the clock domain for transmitting data frames in the CAN bus during this verification process can be determined by the baud rate and bit timing parameters in the pre-configured parameters. In addition, the sending frame information, that is, the specific frame information of the data frame transmitted in the CAN bus during this verification process, can be freely set according to the actual verification requirements, and this embodiment does not limit this.

[0112] Based on the above, it is not difficult to see that step S20 is to drive the sending node to send a specific data frame for the pre-configured parameters determined above for subsequent comparison and verification. When various parameters are known, how to drive the CAN bus controller module to send a specific data frame is well known to those skilled in the art and will not be described in detail in this embodiment.

[0113] For step S30, as described above, when the parameters of the data frame are known and the clock domain of the CAN bus is known, the bus signal value being transmitted can be directly captured from the CAN bus based on the CAN bus protocol to achieve the acquisition of the data frame transmitted in the CAN bus. In order to distinguish the different acquisition methods of this data frame, the data frame captured from the CAN bus is called a bus frame, the data frame sent by the sending node is called a sending frame, and the receiving frame received by the receiving node is called a receiving frame. But in fact, in a verification process, the bus frame, the sending frame and the receiving frame all refer to the same data frame.

[0114] Specifically, this embodiment also provides a possible implementation scheme of step S30, including:

[0115] S31: Determine the sampling pulse according to the baud rate and bit timing parameters;

[0116] S32: Performing bit timing synchronization between the sampling pulse and the transmission bus signal in the controller area network bus;

[0117] S33: sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after bit timing synchronization.

[0118] As for step S31, it is not difficult to see from the above that the duration of transmitting one bit in the CAN bus can be determined according to the baud rate and the bit timing parameters. Based on this, the corresponding sampling frequency can be obtained to capture each bit of the data frame transmitted in the CAN bus, that is, to obtain the corresponding sampling pulse.

[0119] Exemplarily, this embodiment also provides a specific implementation scheme of a sampling pulse, and the above step S31 specifically includes:

[0120] S311: Determine the pre-scaling coefficient according to the baud rate and bit timing parameters.

[0121] The pre-scaling coefficient is the number of clock cycle counts required for the duration corresponding to the minimum time unit in the clock domain determined by the baud rate and bit timing parameters, ie, the BRP mentioned in the formula of the above embodiment.

[0122] S312: Using the pre-scaling coefficient as the cyclic count value of the pre-established bit timing counting unit, and using the bus clock signal determined by the baud rate and the bit timing parameters to drive the counting of the bit timing counting unit.

[0123] S313: Whenever the bit timing counting unit completes a cycle, a timing counting plus one signal is sent out to obtain a counting pulse.

[0124] S314: Pushing the counting of the pre-established minimum unit counting unit through counting pulses.

[0125] S315: When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time segment parameter and the first phase buffer segment parameter, the bus sampling signal is set to obtain a sampling pulse.

[0126] S316: When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time segment parameter, the first phase buffer segment parameter and the second phase buffer segment parameter, the count value of the minimum unit counting unit is cleared.

[0127] In which, for step S311, the pre-frequency division coefficient can be determined according to the formula in the above embodiment, which will not be described in detail in this embodiment.

[0128] As for step S312, it can be known from the above embodiment that the pre-division coefficient indicates the number of times a minimum time unit Tq duration needs to be counted in the clock cycle under the CAN clock domain. That is, if counting is performed through a counter under the CAN clock domain, then each time the counter counts to BRP, it indicates that a minimum time unit Tq duration has passed. Therefore, step S312 is a counting loop body driven by a bus clock signal determined by the baud rate and the bit timing parameters, and its loop value is set to the pre-division coefficient BRP. Then, each time the counting loop body completes a cycle, it indicates that a simulation time of a minimum time unit Tq has passed. Corresponding to step S313, that is, after each cycle is completed by the in-bit timing counting unit, a timing plus one signal is sent to indicate the simulation time of a minimum time unit Tq, and a counting pulse for counting the number of minimum time units currently passed is obtained.

[0129] For step S314, the counting of the minimum time unit is also realized by a counting loop body. To distinguish the counting loop body in the above step S312, the counting loop body in this step is called the minimum unit counting unit, and the counting loop body in step S312 is called the bit timing counting unit.

[0130] As for step S315, it can be known from the above embodiment that in the CAN bus protocol, each transmission bit is divided into 4 timing segments on a time scale. Moreover, when the data bit is sampled, sampling is generally performed at the end of the third timing segment (i.e., the first phase buffer segment PBS1) and the beginning of the fourth timing segment (i.e., the second phase buffer segment PBS2). Therefore, in step S315, based on SS, PTS, and PBS1 in the bit timing parameters, when the count value of the minimum time counting unit reaches the sum of the first three timing segments, sampling can be performed, which is achieved by setting the bus sampling signal to obtain a sampling pulse generated by the set bus sampling signal.

[0131] As for step S316, it can be seen from the above that one transmission bit includes four timing segments, so when the count value of the minimum time unit reaches the sum of the four timing segments, it indicates that the transmission bit is finished and the next transmission bit needs to be sampled. Therefore, step S316 clears the count value of the minimum time counting unit and clears the set bus sampling signal to prepare for the sampling of the next transmission bit.

[0132] In addition, for step S32, since the sending unit does not start data frame transmission at the moment when the pre-configured parameters are written or the verification simulation starts, in order to achieve more accurate bus signal value capture, the sampling pulse needs to be synchronized with the timing of the sampling pulse and the CAN bus. This bit timing synchronization can be implemented according to the bit timing synchronization function specified in the CAN bus protocol, which will not be described in detail in this embodiment. However, this embodiment provides a possible bit timing synchronization scheme, and the above-mentioned step S32 specifically includes:

[0133] S321: In the bit timing counting unit, assign the bus signal value to the 0th bit of the predefined first merging array.

[0134] The width of the first merged array is 2.

[0135] S322: Using the shift operator, the first merge array is logically shifted left by 1 bit.

[0136] S323: Wait for the bus clock signal to rise and assign the bus signal value to the 0th bit of the first merge array.

[0137] S324: Compare the value of the first bit of the first merging array with the inverted value of the 0th bit of the first merging array to determine whether a falling edge occurs in the bus waveform of the CAN bus.

[0138] S325: If a falling edge occurs, the bus falling edge flag signal is set.

[0139] When the bus falling edge flag signal is set, the count value of the minimum unit counting unit is cleared, and then the bus falling edge flag signal is cleared.

[0140] That is, this embodiment uses a merged array with a width of 2 (i.e., the first merged array) to solve the implementation of the bit synchronization function. The specific technical solution is as follows: define a merged array bus_status with a width of 2, which has two bits bus_status[0] and bus_status[1]; assign the bus value to bus_status[0] in the above-mentioned bit timing counting unit; after the assignment, use the shift operator to logically shift the bus_status array left by 1 bit; then wait for the CAN bus clock rising edge clock to push; then assign the bus value to bus_status[0]; finally, compare the value of bus_status[1] with the inverted value of bus_status[0] to determine whether the bus waveform has a falling edge; if a falling edge occurs, set the bus falling edge flag signal, which indicates that the bit timing minimum unit count should be cleared to achieve bit timing synchronization. Among them, the occurrence of the frame start (SOF) bit is called hard synchronization, and the occurrence of bits other than the SOF bit is called resynchronization.

[0141] Afterwards, step S33 is a step of sampling the bus signal value (i.e., transmission bit) transmitted in the CAN bus using the sampling pulse determined and synchronized with the bit timing according to the above steps. Similarly, although this embodiment does not limit the specific sampling steps, it provides a possible implementation scheme, and the above step S33 specifically includes:

[0142] S331: Whenever the bus sampling signal is set, sampling the bus signal value transmitted in the controller area network bus;

[0143] S332: When the interrupt signal of the receiving node is detected to be set, the sampling of the bus signal value is stopped;

[0144] Among them, the interrupt signal is set by the receiving node after the data frame transmission is completed.

[0145] That is, this embodiment samples the bus signal value transmitted in the CAN bus based on the sampling pulse determined in the above embodiment, thereby capturing the bus signal value of each bit transmitted in the CAN bus. In addition, when the receiving unit receives the last bit of the data frame, it will set the completion interrupt to indicate that the frame reception is complete. Therefore, this embodiment uses the interrupt as a sign of the end of sampling. When the interrupt signal of the receiving node is detected to be set, the sampling of the bus signal value is stopped to achieve accurate sampling of a bus frame.

[0146] On the other hand, for step S40 in this method, the verification data used for subsequent comparison and inspection to verify the CAN bus controller module is determined based on the captured bus frame. Among them, it can be seen from the above that the pre-configured parameters can be used as verification data involved in the verification, which is used to characterize the timing characteristics in the frame transmission. In addition, it should also include data characteristics in frame transmission, that is, verify whether the specific data of the data frames sent, captured during the transmission process, and received are consistent.

[0147] It should be noted that this embodiment does not limit the capture scheme of the bus frame information, and a suitable extraction scheme can be selected according to the needs of the bus frame information actually involved in the subsequent verification. However, on this basis, this embodiment also provides a bus frame information extraction scheme, and step S40 specifically includes:

[0148] S41: According to the bit filling mechanism in the controller area network bus protocol, the sampled bus signal value is subjected to a de-bit filling process to obtain a de-bit filled fixed format frame information queue.

[0149] The format of the fixed format frame information queue with the bit filling conforms to the data frame format specified by the controller area network bus protocol.

[0150] S42: extracting data on designated data bits in the fixed format frame information queue without bit filling according to the data frame format specified by the controller area network bus protocol to determine the bus frame information.

[0151] The bus frame information includes: special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value.

[0152] It should be noted that, as stipulated in the CAN bus protocol, in the frame format, between the SOF bit and the cyclic redundancy check (CRC) sequence segment (including the CRC sequence segment), a bit with opposite polarity should be filled after five consecutive bits of the same level, which is bit filling to ensure the timeliness of bit synchronization and distinguish it from the error frame format. Therefore, the bus frame captured in this method also needs to be de-stuffed to remove the useless data of the bit filling in the captured bus frame. Step S41 in this embodiment is the step of implementing the de-stuffing.

[0153] This embodiment does not limit the specific implementation of the bit filling function in step S41, but provides a possible implementation scheme. Step S41 specifically includes:

[0154] S411: When a bus signal value is obtained by sampling, the bus signal value is assigned to the 0th bit of a predefined second merging array.

[0155] The width of the second merged array is 12.

[0156] S412: Determine whether the values ​​of the first to fifth bits of the second merge array are the same.

[0157] S413: If they are the same, determine whether the values ​​of the first to 11th bits of the second merge array are all "1".

[0158] S414: If all are "1", determine whether the bus signal value obtained by this sampling is "0".

[0159] S415: If it is "0", fill the bus signal value into the 0th bit in the fixed format frame information queue, set the start bit to obtain the frame signal, and reassign the values ​​of the 1st and 5th bits of the second merged array to "11101"; and use the shift operator to logically shift the second merged array left by 1 bit.

[0160] S416: If not all are "1", the second merge array is logically shifted left by 1 bit using a shift operator.

[0161] S417: If different, determine whether the start acquisition frame signal is set.

[0162] S418: If the start acquisition frame signal is set, the bus signal value obtained by this sampling is filled into the fixed format frame information queue, and the second merge array is logically shifted left by 1 bit through the shift operator.

[0163] S419: If the start acquisition frame signal is not set, the second merge array is logically shifted left by 1 bit through the shift operator.

[0164] It should be noted that the above-mentioned “0”, “1” and “11101” are all binary data, corresponding to the binary data at a specific bit of the bus frame.

[0165] That is, this embodiment uses a merge array with a width of 12 as a de-stuffing window array, the lower six bits of the array are the de-stuffing window, and a queue as a de-stuffing frame information queue to solve the implementation of the de-stuffing logic. The specific scheme is as follows:

[0166] Define a merge array bit_destuff_check (i.e., the second merge array) with a width of 12, and initialize it to 12'b0. When the bus sampling signal is received, assign the captured bus signal value to bit_destuff_check[0]. Since the CAN bus controller sends 11 bits of 1 to the bus at the beginning of the simulation, it ensures that the bus is idle before sending the frame. Therefore, the logic of de-stuffing is as follows: when receiving the bus sampling signal, determine whether the de-stuffing window bit_destuff_check[5:1] is 5'b11111 or 5'b00000; if yes, continue to determine whether bit_destuff_check[11:1] is 11'b1111_1111_111; if yes, it indicates that bit_destuff_check has been written with 11 bits 1 and is ready to enter the bus frame transmission process, and continue to determine whether the bus value bit_destuff_check[0] obtained this time is 0; if it is 0, indicating that this value is the transmission frame SOF bit, then the bus value is added to the queue, the start acquisition frame signal is set, and bit_destuff_check[5:1] is modified and reassigned to 5'b11101; finally, use the shift operator to logically shift the bit_destuff_check array left by 1 bit.

[0167] If the above judgment bit_destuff_check[11:1] is not 11'b1111_1111_111, it indicates that the current CAN bus controller is still in the process of sending 11 bits 1 and waiting for the bus to be idle. Or the current CAN bus controller is sending a frame, and the current captured bus value is a fill bit, then only the bit_destuff_check array is logically shifted left by 1 bit.

[0168] If the initial judgment bit_destuff_check[5:1] is not 5'b11111 or 5'b00000, then continue to judge whether the start acquisition frame signal is set; if it is, it indicates that the current bus is in the transmission frame state, and there are not five consecutive bits of the same level, then the bus value bit_destuff_check[0] acquired this time is added to the queue; then the bit_destuff_check array is logically shifted left by 1 bit.

[0169] If the above judgment starts to obtain the frame signal is not set, indicating that the current bus is not in the frame transmission state, then the bit_destuff_check array is only logically shifted left by 1 bit.

[0170] After the bus frame transmission is completed, the receiving node will set the completion interrupt to indicate that the frame reception is complete. The bus value capture and processing unit in the verification platform monitors the interrupt signal setting and stops the capture and processing of the bus signal to obtain a complete fixed-format frame information queue without bit filling.

[0171] Based on the above obtained fixed format frame information queue without bit filling, step S42 can extract any required frame information according to the frame format specified by the CAN bus protocol. Before describing the specific embodiment of this step, the implementation principle of this step is described first:

[0172] As shown in Figure 3, the frame format specified by the CAN bus protocol includes two transmission function frames (data frame, remote control frame) and two formats (standard format, extended format). Based on this, the four main frame formats shown in Figure 3 can be obtained by combining them in pairs: standard remote control frame, standard data frame, extended remote control frame and extended data frame.

[0173] Among them, the extended identifier (IDE) bit value of the standard frame is 0, which is located at the 13th bit in the standard frame format (counting from left to right, the SOF bit is the starting bit 0); the IDE bit value of the extended frame is 1, which is also located at the 13th bit in the extended frame format. The remote transmission request (RTR) bit value of the data frame is 0; the RTR bit value of the remote control frame is 1; the RTR bit is located at the 12th bit in the standard frame format; and at the 32nd bit in the extended frame format. In the extended frame format, the substitute remote request (SRR) bit occupies the original RTR position, and the SRR value is always 1, which is located at the 12th bit in the extended frame format. The value of r0 in the reserved bits (r0 and r1) is 0; it is located at the 14th bit in the standard frame format and at the 34th bit in the extended frame format; the value of r1 in the reserved bits is 0, which only exists in the extended frame and is located at the 34th bit in the extended frame format. The frame data length (DLC) is a 4-bit binary number, indicating the frame data length in bytes. It is located at bits 15-18 (high to low) in the standard frame format and at bits 35-38 in the extended frame format.

[0174] It can be seen that based on the provisions of the frame format in the CAN bus protocol, the frame format of the bus frame can be determined by a specific identification bit in the bus frame, and then any required bus frame information can be extracted based on the frame format. Based on this, this embodiment also provides a possible implementation plan:

[0175] The above-mentioned special identification bit information includes: extended identifier (IDE) bit value, remote transmission request (RTR) bit value, substitute remote request (SRR) bit value and reserved bit value (r0 and r1).

[0176] Step S42 specifically includes:

[0177] S421: Determine whether the format of the data frame to be transmitted this time is a standard format frame or an extended format frame according to the extended identifier bit value on the designated data bit in the fixed format frame information queue.

[0178] S422: Based on the data frame format of this transmission, extract other special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value.

[0179] Specifically, after obtaining the fixed format frame information queue without bit filling, this embodiment extracts the 13th IDE parameter value in the queue to determine whether the current frame is a standard format frame or an extended format frame. Then, according to the frame format type, other special identification bit values ​​are extracted according to the fixed bits specified by the CAN bus protocol, such as RTR, SRR, r0, r1, frame data length (DLC) and frame data information (frame data on other bits), as well as the CRC check value sequence and the response field slot value (the response field is ACK, which consists of an ACK slot and an ACK delimiter, a total of two bits).

[0180] After obtaining the above bus frame information and obtaining the received frame information in step S50, the subsequent step S60 of full matching of the sending frame information, the bus frame information and the received frame information can be performed. However, further, this embodiment also provides a possible implementation scheme, wherein the above bus frame information also includes: a cyclic redundancy check value reference sequence.

[0181] Wherein, after step S421: determining whether the format of the data frame to be transmitted is a standard format frame or an extended format frame, the method further includes:

[0182] S423: Based on the data frame format of this transmission, the frame data from the frame start bit to before the cyclic redundancy check value sequence is intercepted as the partial frame information queue to be checked.

[0183] S424: Process the part of the frame information queue to be checked through a cyclic redundancy check unit to obtain a cyclic redundancy check value reference sequence.

[0184] The cyclic redundancy check algorithm adopted by the cyclic redundancy check unit is the cyclic redundancy check algorithm specified by the controller area network bus protocol.

[0185] That is, in this embodiment, a verification process of performing CRC check on the captured bus frame is also added. Specifically, according to the partial data bits in the captured bus frame (i.e., the partial frame information queue to be checked), a corresponding check value (i.e., a cyclic redundancy check value reference sequence) is generated through a CRC check algorithm, and compared with the CRC check value sequence transmitted by the bus frame to complete the CRC check of the bus frame.

[0186] It should be noted that the CAN bus protocol stipulates that the CRC-15 algorithm is used to implement the CRC check of the data frame, so the CRC-15 algorithm used by the CRC check unit in this embodiment is the CRC-15 algorithm.

[0187] On the other hand, for the full match of the three-party frame information implemented in step S60, it is easy to know whether the corresponding data items in the three-party frame information are completely consistent; if so, it means that the two CAN bus controller modules as the sending node and the receiving node are normal and the verification passes; if it fails, it can be considered that the verification has failed or further verification is performed, and this embodiment does not limit this.

[0188] However, based on the bus frame information determined in the above embodiment, this embodiment also provides a possible full match verification solution, and the above step S60 specifically includes:

[0189] S61: According to the response field slot value in the bus frame information, determine whether the data frame transmitted this time is normally received by the receiving node; if so, perform subsequent verification (i.e., steps S62 to S66); if not, return verification failure information and exit this method.

[0190] S62: Fully match the first special identification bit information in the bus frame information, the sending frame information and the receiving frame information, and output a first matching result.

[0191] S63: Check whether the second special identification bit information in the bus frame information complies with the controller area network bus protocol, and output the check result.

[0192] Among them, the set of the first special identification bit information and the second special identification bit information is the special identification bit information, and the second special identification bit information includes: an alternative remote request bit value and a reserved bit value.

[0193] S64: Fully match the frame data lengths and frame data information in the bus frame information, the transmission frame information, and the reception frame information, and output a second matching result.

[0194] S65: Match the cyclic redundancy check value sequence in the bus frame information with the cyclic redundancy check value reference sequence, and output a third matching result.

[0195] S66: Determine a verification result according to the first matching result, the second matching result, the inspection result and the third matching result.

[0196] That is, this embodiment first determines whether the ACK slot value in the bus frame information is 0 to determine whether the current frame is received normally by the receiving node; if it is 0, it indicates that the frame reception is normal and the subsequent three-party frame information parameter full matching continues; if it is 1, it indicates that the frame reception is abnormal. At this time, the bus frame information capture is abnormal and the verification has failed, so the parameter comparison is stopped and the reception is normal or failed information is output.

[0197] For the three-way full match of the sent frame information, bus frame information and received frame information: first, the extracted special identification bit value is fully matched with the relevant parameter value in the pre-configured parameters of the verification platform, and the relevant parameter value in the received frame information of the receiving node, and the matching success or failure information is output as the first matching result; wherein, for some special identification bit values ​​(SRR, r0, r1), since these parameters are automatically generated and filled by the CAN bus controller according to the set frame format type, after determining the frame format type, the value can be directly checked to determine whether it complies with the generation and filling rules specified in the CAN bus protocol, and the check pass or fail information is output as the check result. The extracted frame data length and frame data information are fully matched with the relevant parameter value in the pre-configured parameters (i.e., the sent frame information), and the relevant parameter value in the received frame information of the receiving node, and the matching success or failure information is output as the second matching result. In addition, for the CRC check of the bus frame information in the above embodiment, the CRC check value sequence in the match bus frame is consistent with the CRC check value reference sequence returned by the CRC-15 calculation unit, and the matching success or failure information is output as the third matching result. Based on the results of the above four verification items, the final verification result can be determined.

[0198] Further, based on the above embodiment, this embodiment also provides a possible implementation scheme. After the above step S66, the method further includes:

[0199] S67: If any of the first matching result, the inspection result, the second matching result and the third matching result is failed, determine the abnormal position item according to the failed result item.

[0200] Among them, the abnormal location item represents the possible location of the abnormality that caused the failure of this verification.

[0201] S68: Return verification failure information including failed result items and abnormal position items.

[0202] It is not difficult to understand that in the simplest solution for locating the abnormal position of the failed verification, it can be realized based on whether the erroneous data item belongs to any one of the sending frame information, bus frame information or receiving frame information. Since the matching of this method is a three-party full match, if one party has a different data item corresponding to the other two parties, while the other two parties are the same, it can be determined as an abnormal data item, which assists relevant personnel in locating and verifying the abnormal position. In addition, other abnormal positioning solutions can also be used, and this embodiment does not limit this.

[0203] Exemplarily, based on the abnormality location ideas provided above, this embodiment provides a possible implementation scheme, and the above step S67 specifically includes:

[0204] S671: If the first matching result is failed, it is determined that the abnormal data item in the first matching result belongs to the sending frame information, the bus frame information or the receiving frame information; if the abnormal data item belongs to the sending frame information, the abnormal position item is determined to be the sending node; if the abnormal data item belongs to the bus frame information, the abnormal position item is determined to be the CAN bus; if the abnormal data item belongs to the receiving frame information, the abnormal position item is determined to be the receiving node.

[0205] S672: If the check result is failed, determine that the abnormal location item is the CAN bus.

[0206] S673: If the second matching result is failed, it is determined that the abnormal data item in the second matching result belongs to the sending frame information, the bus frame information or the receiving frame information; if the abnormal data item belongs to the sending frame information, the abnormal position item is determined to be the sending node; if the abnormal data item belongs to the bus frame information, the abnormal position item is determined to be the CAN bus; if the abnormal data item belongs to the receiving frame information, the abnormal position item is determined to be the receiving node.

[0207] S674: If the third matching result is failed, it is determined that the abnormal location item is the CAN bus.

[0208] It is particularly important to note that when it is determined that the abnormal position item is the CAN bus, it means that the bus frame information is abnormal. Further judgment is required at this time. There may be a problem in the process of sampling the bus signal value from the CAN bus, or there may be a problem when the sending node sends the data frame, which requires further judgment. This embodiment does not limit the further judgment scheme, and a suitable further judgment scheme can be selected according to actual needs. This embodiment can locate the abnormal position to a certain extent by analyzing the abnormal data item, thereby assisting relevant personnel to realize the verification of the CAN bus controller module.

[0209] Based on the implementation scheme provided by the above embodiment, the complete process of a bus controller module verification method provided by the present invention is shown in Figure 4. It is not difficult to see that the bus controller module verification method provided by the present invention can directly capture the bus signal value from the CAN bus based on the CAN protocol, and organize the bus signal value into a complete data frame transmitted in the CAN bus this time based on the CAN bus protocol and pre-configured parameters. Based on this, the pre-configured parameters can determine the sending frame information sent by the sending node, the bus frame information captured from the CAN bus during the data frame transmission process, and the receiving frame information obtained from the receiving node, so that a three-party full match can be achieved, and the verification of two bus controller modules can be achieved at the same time, and the verification accuracy is higher than that of the two-party verification. In addition, in this method, the information that needs to be matched and verified later can be directly captured from the CAN bus, without using the VIP of the CAN bus controller, which greatly reduces the verification and learning costs. Moreover, in this method, one data frame transmission can realize the verification of two CAN bus controller modules, which is more efficient than the traditional solution of realizing the verification of a CAN bus controller module through two CAN bus controller VIP nodes, which is conducive to further shortening the development cycle of the chip.

[0210] In the above embodiment, a bus controller module verification method is described in detail, and the present invention also provides a corresponding embodiment of a bus controller module verification system. As shown in FIG1 , a bus controller module verification system provided in this embodiment includes: a bus verification platform and two bus controller modules to be tested;

[0211] The bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected through a controller area network bus; wherein one bus controller module to be tested serves as a sending node, and the other bus controller module to be tested serves as a receiving node;

[0212] The bus verification platform includes: bus controller reference model, driver and receiver;

[0213] Among them, the bus controller reference model is connected to the register of the sending node through the driver; the bus controller reference model is connected to the register of the receiving node through the receiver; the bus controller reference model is used to implement the steps of the bus controller module verification method as described in the above embodiment.

[0214] It should be noted that the above-mentioned bus controller reference model can be written in System Verilog (a high-level hardware design verification language) to realize the construction of a bus verification platform. In addition, the bus controller module verification method provided by the above-mentioned method embodiment can essentially be regarded as a data stream processing method, and its execution subject in this embodiment is the above-mentioned bus controller reference model. That is, the core of the present invention is that the bus controller reference model processes pre-configured parameters, bus signal values, and data such as received frame information through a bus controller module verification method provided by the above-mentioned method embodiment to obtain the final verification result of the CAN bus controller module and bring about the technical effect described in the above-mentioned method embodiment.

[0215] In addition, in a possible embodiment, the above-mentioned bus controller reference model is divided into multiple functional modules to implement different steps of the above-mentioned bus controller module verification method. As shown in Figure 5, the bus controller reference model also includes: a bit timing counting unit, a sampling signal flag generation unit, a bus value capture and processing unit, a parameter comparison unit and a cyclic redundancy check calculation unit.

[0216] Among them, the bit timing counting unit is used to realize the generation of counting pulses and the process of the bit timing synchronization part in the above method embodiment; the sampling signal flag generation unit is used to realize the partial process of sampling pulse generation; the bus value capture and processing unit is used to realize the sampling of bus signal values ​​and the process of de-bit filling part; the parameter comparison unit is used to realize the partial process of full matching of sending frame information, bus frame information and receiving frame information; the cyclic redundancy check calculation unit is used to realize the calculation of the above cyclic redundancy check value reference sequence based on the CRC-15 algorithm.

[0217] Since the embodiments of the system part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the system part, which will not be repeated here.

[0218] In addition to the embodiments of the bus controller module verification method and system provided in the above embodiments, the present invention also provides an embodiment corresponding to a computer program product. A computer program product includes a computer program / instruction, and when the computer program / instruction is executed by a processor, the steps of the bus controller module verification method described in any of the above embodiments can be implemented.

[0219] Since the embodiments of the computer program product part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the computer program product part, which will not be repeated here.

[0220] FIG6 is a structural diagram of a bus controller module verification device provided by another embodiment of the present invention. As shown in FIG6 , a bus controller module verification device includes: a memory 10 for storing a computer program;

[0221] The processor 11 is used to implement the steps of a bus controller module verification method in the above embodiment when executing a computer program.

[0222] The bus controller module verification device provided in this embodiment may include but is not limited to a mobile terminal, a personal computer, a workstation, etc.

[0223] Among them, the processor 11 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 11 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 11 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 11 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 11 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0224] The memory 10 may include one or more computer-readable storage media, which may be non-transitory. The memory 10 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 10 is at least used to store the following computer program 101, wherein, after the computer program is loaded and executed by the processor 11, it can implement the relevant steps of a bus controller module verification method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 10 may also include an operating system 102 and data 103, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 102 may include Windows, Unix, Linux, etc. Data 103 may include but is not limited to a bus controller module verification method, etc.

[0225] In some embodiments, a bus controller module verification device may further include a display screen 12 , an input / output interface 13 , a communication interface 14 , a power supply 15 , and a communication bus 16 .

[0226] Those skilled in the art will appreciate that the structure shown in FIG. 6 does not constitute a limitation on a bus controller module verification device, and may include more or fewer components than those shown in the figure.

[0227] A bus controller module verification device provided by an embodiment of the present invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a bus controller module verification method.

[0228] Finally, the present invention also provides an embodiment corresponding to a non-volatile storage medium. The non-volatile storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

[0229] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.

[0230] The above is a detailed introduction to a bus controller module verification method, system, program product, device and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0231] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A bus controller module verification method, characterized in that: Applied to a bus verification platform, the bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected via a controller area network bus; wherein one of the bus controller modules to be tested serves as a sending node, and the other bus controller module to be tested serves as a receiving node; Methods include: Generate pre-configuration parameters through random constraints; wherein the pre-configuration parameters include: baud rate, bit timing parameters and transmission frame information; Writing the pre-configuration parameters to the sending node and enabling the sending node to start frame transmission, so that the sending node sends data frames to the receiving node through the controller area network bus according to the pre-configuration parameters; Synchronously capturing bus signal values ​​from the controller area network bus according to the baud rate and bit timing parameters; Determining bus frame information according to the bus signal value; After the data frame is sent, reading the received frame information from the receiving node; Performing full matching on the sending frame information, the bus frame information and the receiving frame information, and determining a verification result according to the full matching result; Wherein, synchronously capturing bus signal values ​​from the controller area network bus according to the baud rate and bit timing parameters includes: Determining a sampling pulse according to the baud rate and the bit timing parameters; Performing bit timing synchronization between the sampling pulse and a transmission bus signal in the controller area network bus; Sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after bit timing synchronization; The bit timing parameters include: synchronization segment parameters, propagation time segment parameters, first phase buffer segment parameters and second phase buffer segment parameters; Determining the sampling pulse according to the baud rate and the bit timing parameter includes: Determine a pre-scaling coefficient according to the baud rate and the bit timing parameter; wherein the pre-scaling coefficient is the number of clock cycle counts required for the duration corresponding to the minimum time unit in the clock domain determined by the baud rate and the bit timing parameter; Using the pre-scaling coefficient as a cyclic count value of a pre-established bit timing counting unit, and using a bus clock signal determined by the baud rate and the bit timing parameter to drive the counting of the bit timing counting unit; Whenever the bit timing counting unit completes a cycle, a timing counting plus one signal is sent out to obtain a counting pulse; By means of the counting pulse, the counting of the pre-established minimum unit counting unit is promoted; When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time segment parameter and the first phase buffer segment parameter, setting the bus sampling signal to obtain the sampling pulse; When the count value of the minimum unit counting unit reaches the sum of the synchronization segment parameter, the propagation time period parameter, the first phase buffer segment parameter and the second phase buffer segment parameter, the count value of the minimum unit counting unit is cleared.

2. The bus controller module verification method according to claim 1, characterized in that: Performing bit timing synchronization between the sampling pulse and the transmission bus signal in the controller area network bus includes: In the bit timing counting unit, assigning the bus signal value to the 0th bit of a predefined first merging array; wherein the width of the first merging array is 2; By using a shift operator, the first merged array is logically shifted left by 1 bit; When the bus clock signal is pushed by a rising edge, the bus signal value is assigned to the 0th bit of the first merging array; Comparing the value of the first bit of the first merging array with the inverted value of the 0th bit of the first merging array to determine whether a falling edge occurs in the bus waveform of the controller area network bus; If a falling edge occurs, the bus falling edge flag signal is set; When the bus falling edge flag signal is set, the count value of the minimum unit counting unit is cleared, and then the bus falling edge flag signal is cleared.

3. The bus controller module verification method according to claim 2, characterized in that: Sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after bit timing synchronization includes: Whenever the bus sampling signal is set, sampling the bus signal value transmitted in the controller area network bus; When it is detected that the interrupt signal of the receiving node is set, the sampling of the bus signal value is stopped; The interrupt signal is set by the receiving node after the data frame is transmitted.

4. The bus controller module verification method according to any one of claims 1 to 3, characterized in that: Determining bus frame information according to the bus signal value includes: According to the bit filling mechanism in the controller area network bus protocol, the bus signal value obtained by sampling is subjected to a de-bit filling process to obtain a de-bit filled fixed format frame information queue; wherein the format of the de-bit filled fixed format frame information queue conforms to the data frame format specified by the controller area network bus protocol; Extracting data on a specified data bit in the fixed format frame information queue without bit filling according to the data frame format specified by the controller area network bus protocol to determine the bus frame information; The bus frame information includes: special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value.

5. The bus controller module verification method according to claim 4, characterized in that: The step of performing a bit filling process on the bus signal value obtained by sampling according to the bit filling mechanism in the controller area network bus protocol to obtain a fixed format frame information queue after the bit filling is removed includes: When the bus signal value is obtained by sampling, the bus signal value is assigned to the 0th bit of a predefined second merge array; wherein the width of the second merge array is 12; Determine whether the values ​​of the first to fifth bits of the second merged array are the same; If they are the same, determine whether the values ​​of the first to 11th bits of the second merged array are all "1"; If all are "1", determine whether the bus signal value obtained by this sampling is "0"; If it is "0", fill the bus signal value into the 0th bit in the fixed format frame information queue, set the start acquisition frame signal, and reassign the value of the 1st bit to the 5th bit of the second merge array to "11101"; and use the shift operator to logically shift the second merge array left by 1 bit; If not all are "1", the second merged array is logically shifted left by 1 bit using a shift operator; If they are different, determining whether the start acquisition frame signal is set; If the start acquisition frame signal is set, the bus signal value obtained by this sampling is filled into the fixed format frame information queue, and the second merge array is logically shifted left by 1 bit through a shift operator; If the start acquisition frame signal is not set, the second merge array is logically shifted left by 1 bit through a shift operator.

6. The bus controller module verification method according to claim 4, characterized in that: The special identification bit information includes: an extended identifier bit value, a remote transmission request bit value, an alternative remote request bit value and a reserved bit value; According to the data frame format specified by the controller area network bus protocol, extract the data on the specified data bit in the fixed format frame information queue without bit filling to determine that the bus frame information includes: Determining whether the format of the data frame to be transmitted this time is a standard format frame or an extended format frame according to the extended identifier bit value on the designated data bit in the fixed format frame information queue of the bit-removed filling; Based on the data frame format of this transmission, other special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot value are extracted.

7. The bus controller module verification method according to claim 6, characterized in that: The bus frame information also includes: a cyclic redundancy check value reference sequence; Wherein, after determining that the format of the data frame to be transmitted is a standard format frame or an extended format frame, the method further includes: Based on the data frame format of this transmission, the frame data starting from the frame start bit to before the cyclic redundancy check value sequence is intercepted as the partial frame information queue to be checked; Processing the to-be-checked partial frame information queue through a cyclic redundancy check unit to obtain the cyclic redundancy check value reference sequence; The cyclic redundancy check algorithm adopted by the cyclic redundancy check unit is the cyclic redundancy check algorithm specified by the controller area network bus protocol.

8. The bus controller module verification method according to claim 7, characterized in that: Performing full matching on the transmission frame information, the bus frame information and the reception frame information, and determining the verification result according to the full matching result includes: According to the response field slot value in the bus frame information, determine whether the data frame transmitted this time is normally received by the receiving node; if so, perform subsequent verification; if not, return verification failure information and exit this method; Fully matching the first special identification bit information in the bus frame information, the sending frame information and the receiving frame information, and outputting a first matching result; Check whether the second special identification bit information in the bus frame information complies with the controller area network bus protocol, and output the inspection result; wherein the set of the first special identification bit information and the second special identification bit information is the special identification bit information, and the second special identification bit information includes: an alternative remote request bit value and a reserved bit value; Fully matching the frame data lengths and frame data information in the bus frame information, the transmission frame information, and the reception frame information, and outputting a second matching result; Matching the cyclic redundancy check value sequence in the bus frame information with the cyclic redundancy check value reference sequence, and outputting a third matching result; The verification result is determined according to the first matching result, the inspection result, the second matching result and the third matching result.

9. The bus controller module verification method according to claim 8, characterized in that: After determining the verification result according to the first matching result, the second matching result, the inspection result and the third matching result, the method further includes: If any of the first matching result, the inspection result, the second matching result and the third matching result is a failure, determining an abnormal position item according to the failure result item; wherein the abnormal position item represents a possible position of the abnormality that caused the failure of this verification; The verification failure information including the failed result item and the abnormal position item is returned.

10. A bus controller module verification system, characterized in that: include: Bus verification platform and two bus controller modules to be tested; The bus verification platform is connected to two bus controller modules to be tested, and the two bus controller modules to be tested are connected via a controller area network bus; wherein one bus controller module to be tested serves as a sending node, and the other bus controller module to be tested serves as a receiving node; The bus verification platform includes: a bus controller reference model, a driver and a receiver; Wherein, the bus controller reference model is connected to the register of the sending node through the driver; the bus controller reference model is connected to the register of the receiving node through the receiver; the bus controller reference model is used to implement the steps of the bus controller module verification method as described in any one of claims 1 to 9.

11. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the bus controller module verification method according to any one of claims 1 to 9 are implemented.

12. A bus controller module verification device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bus controller module verification method as claimed in any one of claims 1 to 9 when executing the computer program.

13. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the bus controller module verification method according to any one of claims 1 to 9 are implemented.

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