A transient response enhancement circuit for LDO power supply and LDO power supply

Abstract

This application discloses a transient response enhancement circuit for an LDO power supply and an LDO power supply. The transient response enhancement circuit is located between the error amplifier circuit and the regulating transistor circuit of the LDO power supply, and includes a switching circuit, a voltage monitoring circuit, and an energy storage circuit. When the voltage monitoring circuit detects that the output voltage of the LDO power supply is not within the output control threshold range, the switching circuit applies a preset voltage enhancement voltage from the energy storage circuit to the gate of the MOS transistor in the regulating transistor circuit of the LDO power supply, thereby controlling the output voltage of the LDO power supply to quickly recover to the output control threshold range. By directly replacing the gate voltage of the MOS transistor in the regulating transistor circuit, the recovery speed of the LDO power supply output voltage is instantly increased, thereby improving the PSRR characteristics of the LDO power supply.

Description

Technical Field

[0001] This application relates to the field of DC power supply technology, specifically to a transient response enhancement circuit for an LDO power supply and an LDO power supply. Background Technology

[0002] LDO power supplies refer to Low Dropout Regulators, which are electronic components used to regulate voltage. They operate by using transistors or field-effect transistors (FETs) within their linear region to subtract unwanted voltage from the input voltage, producing a controlled and relatively stable output voltage. This type of regulator maintains output voltage stability with a low dropout rate (typically below 1V). Compared to traditional linear regulators, LDO power supplies have a lower dropout rate, thus improving power efficiency. Please refer to [reference needed]. Figure 1 This is a circuit diagram of an LDO power supply. An LDO power supply typically consists of an error amplifier circuit 1, a regulating transistor circuit 2, a feedback circuit 3, and an output load circuit 4. The feedback circuit monitors and adjusts the output voltage to maintain a stable set voltage value. They are widely used in various electronic devices, especially in applications requiring precise and stable power supply voltages, such as integrated circuits (ICs) and other microelectronic devices.

[0003] In high-precision system design, the power supply is required not only to have high initial accuracy but also to effectively suppress load changes. Poor transient response, leading to excessively long voltage dips / overshoots, can cause numerous problems. This is especially true for rapidly changing loads, such as those found in mobile phones and wireless sensors, where the rate of change may exceed the power supply's transient response capability. This can prevent the power supply voltage from reaching its set value and may even cause the device under test to automatically shut down or repeatedly restart. Therefore, implementing an LDO design with fast transient response characteristics is crucial. Summary of the Invention

[0004] The main technical problem this invention addresses is how to improve the transient response characteristics of an LDO power supply.

[0005] According to a first aspect, one embodiment provides a transient response enhancement circuit for an LDO power supply, the LDO power supply being used to enhance the transient response of a first DC power supply V. REF Convert to a second DC power supply V OUT The output is as follows: The LDO power supply includes an error amplifier circuit, a regulating transistor circuit, and a feedback circuit; the feedback circuit is used to sample the second DC power supply V through a voltage divider circuit. OUT Perform voltage divider sampling to obtain the sampling voltage V FBThe error amplifier circuit includes a first amplifier EA, used to adjust the first DC power supply V. REF and sampling voltage V REF Perform differential amplification, and then obtain the driving voltage V after differential amplification. T The output is supplied to the regulating transistor circuit; the regulating transistor circuit includes a MOS transistor Q. MP Used to convert the driving voltage V T Loaded to the MOS transistor Q MP The gate of the MOS transistor Q is used to control the gate of the MOS transistor. MP The voltage value of the gate is used to control the second DC power supply V. OUT The voltage value is maintained within a preset output control threshold range;

[0006] The transient response enhancement circuit is disposed between the error amplifier circuit and the adjustment transistor circuit, and the transient response enhancement circuit is used to monitor the second DC power supply V. OUT The voltage value, and when the second DC power supply V OUT When the voltage value is not within the output control threshold range, the connection between the error amplifier circuit and the regulating transistor circuit is disconnected by the switching circuit, and an enhanced voltage V of a preset voltage value is applied. C Replace the driving voltage V T Loaded to the MOS transistor Q MP The gate of the second DC power supply V is used to control the second DC power supply V. OUT The voltage value recovers to the output control threshold range more quickly.

[0007] In one embodiment, the transient response enhancement circuit includes a switching circuit, a voltage monitoring circuit, and an energy storage circuit;

[0008] The voltage monitoring circuit is connected to the feedback circuit and the switching circuit, and the voltage monitoring circuit is used to monitor the sampled voltage V. FB and / or the second DC power supply V OUT When the monitoring voltage V is obtained O When the voltage is not within a preset monitoring threshold range, a switching gate voltage signal SWITCH is output to the switching circuit; wherein, the preset monitoring threshold range is related to the output control threshold range, and when the monitoring voltage V... O When the voltage is not within a preset monitoring threshold range, the second DC power supply V OUT The voltage value is also not within the output control threshold range;

[0009] The switching circuit is connected to the error amplifier circuit, the energy storage circuit, and the adjustment transistor circuit respectively; when the switching circuit does not receive the switching gate voltage signal SWITCH, it connects the error amplifier circuit and the adjustment transistor circuit to drive the voltage V output by the error amplifier circuit. T The MOS transistor Q is loaded into the regulating transistor circuit. MP The gate; when the switching circuit receives the switching gate voltage signal SWITCH, it disconnects the error amplifier circuit and the adjustment tube circuit, and electrically connects the energy storage circuit to the adjustment tube circuit;

[0010] The energy storage circuit is used to supply energy to the MOS transistor Q in the adjustment transistor circuit after being electrically connected to the switching circuit via the switching circuit. MP The gate is loaded with the enhanced voltage V C To replace the driving voltage V T ;

[0011] Wherein, the monitoring voltage V O The greater the difference between the voltage value and the preset monitoring threshold range, the greater the increase in the enhanced voltage V. C The higher the voltage value.

[0012] In one embodiment, the energy storage circuit includes an energy storage capacitor C. m The transient response enhancement circuit further includes a charging circuit; the charging circuit is used to charge the energy storage capacitor C in the energy storage circuit through the switching circuit. m Charge;

[0013] When the energy storage circuit is electrically connected to the regulating tube circuit through the switching circuit, the switching circuit charges the energy storage capacitor C in the energy storage circuit. m Connected between the error amplifier circuit and the adjustment transistor circuit to charge the energy storage capacitor C. m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate.

[0014] In one embodiment, the energy storage circuit includes at least two energy storage capacitors C. m The charging circuit is used to charge each energy storage capacitor C in the energy storage circuit through the switching circuit. m Charging is performed, and each of the energy storage capacitors C m The voltage values ​​after charging are all different;

[0015] When the energy storage circuit is electrically connected to the regulating tube circuit through the switching circuit, the switching circuit will charge one of the energy storage capacitors C in the energy storage circuit. m Connected between the error amplifier circuit and the adjustment transistor circuit to charge the energy storage capacitor C. m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate;

[0016] The switching circuit is based on the energy storage capacitor C after charging. m The voltage value is selected by choosing the capacitor, and the selected capacitor voltage value is the same as the monitored voltage V. O The voltage value is related to the difference between the preset monitoring threshold range and the voltage value.

[0017] In one embodiment, the charging circuit includes a first charging input terminal, a second charging input terminal, a first discharging output terminal, a second discharging output terminal, a second amplifier EB, a first switch K1, a second switch K2, and a switched capacitor C. S ;

[0018] The first charging input terminal is used for a preset charging voltage V RECT Input;

[0019] The second charging input terminal is used for the sampling voltage V FB Input;

[0020] The first discharge output terminal and the second discharge output terminal are respectively connected to the energy storage circuit to provide charging power to the energy storage circuit;

[0021] The positive input terminal of the second amplifier EB is connected to the first charging input terminal, the negative input terminal of the second amplifier EB is connected to the second discharging output terminal, and the output terminal of the second amplifier EB is connected to the first discharging output terminal.

[0022] One end of the first switch K1 is connected to the second charging input terminal, and the other end is connected to the switched capacitor C. S The positive connection terminal is connected, and the switched capacitor C S The negative connection terminal is grounded;

[0023] One end of the second switch K2 is connected to the second discharge output terminal, and the other end is connected to the switched capacitor C. S Connect the positive connection terminal;

[0024] The switching on and off of the first switch K1 and the second switch K2 are controlled by the switching circuit.

[0025] In one embodiment, the energy storage circuit includes at least two energy storage units, each energy storage unit including a first connection terminal, a second connection terminal, a third switch K3, a fourth switch K4, and an energy storage capacitor C. m ;

[0026] The first connection terminal of the energy storage unit is used to control the connection to the first discharge output terminal of the charging circuit or the error amplifier circuit through the switching circuit.

[0027] The second connection terminal of the energy storage unit is used to control the connection to the second discharge output terminal of the charging circuit or to the regulating tube circuit via the switching circuit.

[0028] One end of the third switch K3 is connected to the first connection terminal of the energy storage unit, and the other end is connected to the energy storage capacitor C. m The positive connection terminal is connected, one end of the fourth switch K4 is connected to the second connection terminal of the energy storage unit, and the other end is connected to the energy storage capacitor C. m Connect the negative terminal;

[0029] When the switching circuit controls the first connection terminal of the energy storage unit to connect to the first discharge output terminal of the charging circuit, and connects the second connection terminal of the energy storage unit to the second discharge output terminal of the charging circuit, the charging circuit supplies power to the energy storage capacitor C. m Charge;

[0030] When the switching circuit controls the first connection terminal of the energy storage unit to be connected to the error amplifier circuit, and connects the second connection terminal of the energy storage unit to the adjustment tube circuit, the energy storage capacitor C m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate.

[0031] In one embodiment, the voltage monitoring circuit includes a third amplifier EC, a fourth amplifier ED, a logic OR gate TA, and a D flip-flop;

[0032] The positive input terminal of the third amplifier EC is used to input a preset first comparison voltage V. A The negative input terminal of the third amplifier EC is used to input the monitoring voltage V. O The positive input terminal of the fourth amplifier ED is used to input a preset second comparison voltage V. B The negative input terminal of the fourth amplifier ED is used to input the monitoring voltage V. O Among them, the first comparison voltage V A Second comparison voltage V BThe voltage values ​​are the two endpoints of the preset monitoring threshold range;

[0033] The two input terminals of the OR gate TA are connected to the output terminals of the third amplifier EC and the fourth amplifier ED, respectively, and the output terminal of the OR gate TA is connected to the input terminal of the D flip-flop.

[0034] The output of the D flip-flop is connected to the switching circuit and is used to output the switching gate voltage signal SWITCH to the switching circuit.

[0035] In one embodiment, the voltage monitoring circuit further includes a logic NAND gate circuit TB and a delay module;

[0036] The output of the D flip-flop is connected to one input of the delay module and the NAND gate TB, respectively. The other input of the NAND gate TB is connected to the delay module. The output of the NAND gate TB is connected to the reset terminal of the D flip-flop.

[0037] According to a second aspect, one embodiment provides an LDO power supply including the transient response enhancement circuit as described in the first aspect.

[0038] In one embodiment, the error amplifier circuit of the LDO power supply includes the first amplifier EA and the output voltage regulator capacitor C. A ;

[0039] The positive input terminal of the first amplifier EA in the differential amplifier circuit is used to input the first DC power supply V. REF The negative input terminal of the first amplifier EA in the differential amplifier circuit is used to input the sampling voltage V. REF The output terminal of the first amplifier EA in the differential amplifier circuit is connected to the transient response enhancement circuit;

[0040] The output voltage regulator capacitor C A One end is connected to the output terminal of the first amplifier EA of the differential amplifier circuit, and the other end is grounded.

[0041] According to the transient response enhancement circuit of the above embodiment, the recovery speed of the LDO power supply output voltage is instantly increased by directly replacing the gate voltage of the MOS transistor in the regulating transistor circuit, thereby improving the PSRR characteristics of the LDO power supply. Attached Figure Description

[0042] Figure 1 This is a circuit connection diagram of an LDO power supply;

[0043] Figure 2 This is a schematic diagram of the connection of a transient response enhancement circuit in one embodiment;

[0044] Figure 3 This is a schematic diagram of the circuit structure of a transient response enhancement circuit in one embodiment;

[0045] Figure 4 This is a schematic diagram of the circuit connection of the energy storage circuit in one embodiment;

[0046] Figure 5 This is a circuit connection diagram of a voltage monitoring circuit in one embodiment;

[0047] Figure 6 This is a schematic diagram of the circuit connection of an LDO power supply in one embodiment;

[0048] Figure 7 In one embodiment, an energy storage capacitor C is selected. m The voltage value and the monitoring voltage V O A diagram illustrating the correspondence between the two relationships;

[0049] Figure 8 This is a schematic diagram comparing the output voltage recovery of an LDO with and without transient response enhancement circuitry in one embodiment. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0051] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0052] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0053] The rapid development of semiconductor technology has led to a huge demand for power management chips. Power management chips can remove noise from the power supply voltage and obtain a stable and reliable output voltage. Low-dropout linear regulator (LDO) chips, in particular, are widely used in wireless power transfer and battery-powered systems. If the transient response of the LDO is poor, changes in load current can cause excessively long output recovery times. This application proposes a transient response enhancement circuit suitable for LDO power supplies, which can effectively improve the transient response capability of the LDO power supply and reduce the output recovery time.

[0054] Example 1:

[0055] Please refer to Figure 2 This is a connection diagram of a transient response enhancement circuit in one embodiment. The LDO power supply is used to convert the first DC power supply V... REF Convert to a second DC power supply V OUT The output is then displayed. The LDO power supply includes an error amplifier circuit 1, a regulating transistor circuit 2, and a feedback circuit 3. The feedback circuit 3 is used to sample the second DC power supply V through a voltage divider circuit. OUT Perform voltage divider sampling to obtain the sampling voltage V FB The error amplifier circuit 1 includes a first amplifier EA, used to power the first DC power supply V. REF and sampling voltage V REF Perform differential amplification, and then obtain the driving voltage V after differential amplification. T The output is supplied to regulating transistor circuit 2. Regulating transistor circuit 2 includes MOSFET Q. MP Used to convert the driving voltage V T Loaded to MOSFET Q MP The gate of the MOSFET is used to control the Q gate. MP The voltage value of the gate is used to control the second DC power supply V. OUT The voltage value is maintained within a preset output control threshold range. The transient response enhancement circuit 5 is located between the error amplifier circuit 1 and the regulating transistor circuit 2. The transient response enhancement circuit 5 is used to monitor the second DC power supply V. OUT The voltage value, and when the second DC power supply V OUT When the voltage value is not within the output control threshold range, the connection between the error amplifier circuit 1 and the regulating transistor circuit 2 is disconnected by the switching circuit, and an enhanced voltage V of a preset voltage value is applied. C Replace drive voltage V T Loaded to MOSFET Q MPThe gate of the second DC power supply V is used to control the second DC power supply V. OUT The voltage value recovers to the output control threshold range more quickly.

[0056] Please refer to Figure 3 This is a schematic diagram of the transient response enhancement circuit 5 in one embodiment. The transient response enhancement circuit 5 includes a switching circuit 51, a voltage monitoring circuit 52, and an energy storage circuit 53. The voltage monitoring circuit 52 is connected to the feedback circuit 3 and the switching circuit 51, and is used to monitor the sampled voltage V. FB and / or a second DC power supply V OUT When the monitoring voltage V is obtained O When the voltage is not within a preset monitoring threshold range, a switching gate voltage signal SWITCH is output to the switching circuit 51. The preset monitoring threshold range is related to the output control threshold range; when the monitoring voltage V... O When the voltage is not within a preset monitoring threshold range, the second DC power supply V OUT The voltage value is also not within the output control threshold range. The switching circuit 51 is connected to the error amplifier circuit 1, the energy storage circuit 53, and the regulating tube circuit 2, respectively.

[0057] In one embodiment, when the switching circuit 51 does not receive the switching gate voltage signal SWITCH, the error amplifier circuit 1 and the adjustment transistor circuit 2 are connected to drive the voltage V output by the error amplifier circuit 1. T Loaded into the MOSFET Q in the regulating circuit 2 MP The gate of the MOSFET. When the switching circuit 51 receives the switching gate voltage signal SWITCH, it disconnects the error amplifier circuit 1 and the adjustment transistor circuit 2, and electrically connects the energy storage circuit 53 to the adjustment transistor circuit 2. The energy storage circuit 53 is used to supply power to the MOSFET Q in the adjustment transistor circuit 2 after being electrically connected to the adjustment transistor circuit 2 via the switching circuit 51. MP Gate-loaded enhancement voltage V C To replace the drive voltage V T Among them, the monitoring voltage V O The greater the difference between the voltage value and the preset monitoring threshold range, the stronger the voltage V. C The higher the voltage value.

[0058] Please refer to Figure 4 This is a circuit connection diagram of an energy storage circuit in one embodiment. The energy storage circuit 53 includes an energy storage capacitor C. m The transient response enhancement circuit also includes a charging circuit 54, which is used to charge the energy storage capacitor C in the energy storage circuit 53 via a switching circuit 51. mCharging is performed. After the energy storage circuit 53 is electrically connected to the regulating tube circuit 2 through the switching circuit 51, the switching circuit 51 charges the energy storage capacitor C in the energy storage circuit 53. m Connected between error amplifier circuit 1 and adjustment transistor circuit 2, to charge energy storage capacitor C. m The voltage obtained after charging is used as the boost voltage V. C Loaded into the MOSFET Q in the regulating circuit 2 MP On the gate.

[0059] In one embodiment, the energy storage circuit 53 includes at least two energy storage capacitors C. m The charging circuit 54 is used to charge each energy storage capacitor C in the energy storage circuit 53 via the switching circuit 51. m Charging is performed, and each energy storage capacitor C m The voltage values ​​after charging are all different. When the energy storage circuit 53 is electrically connected to the regulating tube circuit 2 through the switching circuit 51, the switching circuit 51 will charge one of the energy storage capacitors C in the energy storage circuit 53. m Connected between error amplifier circuit 1 and adjustment transistor circuit 2, to charge energy storage capacitor C. m The voltage obtained after charging is used as the boost voltage V. C Loaded into the regulating transistor circuit MOSFET Q MP On the gate.

[0060] In one embodiment, the charging circuit 54 includes a first charging input terminal, a second charging input terminal, a first discharging output terminal, a second discharging output terminal, a second amplifier EB, a first switch K1, a second switch K2, and a switched capacitor C. S The first charging input terminal is used for a preset charging voltage V. RECT The second charging input is used to sample the voltage V. FB The first and second discharge output terminals are connected to the energy storage circuit 53 to provide charging power. The positive input terminal of the second amplifier EB is connected to the first charging input terminal, the negative input terminal of the second amplifier EB is connected to the second discharge output terminal, and the output terminal of the second amplifier EB is connected to the first discharge output terminal. One end of the first switch K1 is connected to the second charging input terminal, and the other end is connected to the switched capacitor C. S Connect the positive terminal of the capacitor C to the switched capacitor. S The negative connection terminal is grounded. One end of the second switch K2 is connected to the second discharge output terminal, and the other end is connected to the switching capacitor C. S The positive connection terminal is connected. The opening and closing of the first switch K1 and the second switch K2 are controlled by the switching circuit 51.

[0061] In one embodiment, the energy storage circuit 53 includes at least two energy storage units 55, each energy storage unit 55 including a first connection terminal, a second connection terminal, a third switch K3, a fourth switch K4, and an energy storage capacitor C. m The first connection terminal of the energy storage unit 55 is used to control the connection to the first discharge output terminal of the charging circuit 54 or the error amplifier circuit 1 via the switching circuit 51. The second connection terminal of the energy storage unit 55 is used to control the connection to the second discharge output terminal of the charging circuit 54 or the regulating tube circuit 2 via the switching circuit 51. One end of the third switch K3 is connected to the first connection terminal of the energy storage unit 55, and the other end is connected to the energy storage capacitor C. m The positive connection terminal is connected, one end of the fourth switch K4 is connected to the second connection terminal of the energy storage unit 55, and the other end is connected to the energy storage capacitor C. m Connect the negative connection end.

[0062] In one embodiment, when the switching circuit 51 controls the first connection terminal of the energy storage unit 55 to be connected to the first discharge output terminal of the charging circuit 54, and connects the second connection terminal of the energy storage unit 55 to the second discharge output terminal of the charging circuit 54, the charging circuit 54 discharges energy into the energy storage capacitor C in the energy storage unit 55. m Charge it.

[0063] In one embodiment, when the switching circuit 51 controls the first connection terminal of the energy storage unit 55 to be connected to the error amplifier circuit 1, and connects the second connection terminal of the energy storage unit 55 to the adjustment tube circuit 2, the energy storage capacitor C in the energy storage unit 55... m The voltage obtained after charging is used as the boost voltage V. C Loaded into the MOSFET Q in the regulating circuit 2 MP On the gate.

[0064] Please refer to Figure 5 The diagram below shows the circuit connection of a voltage monitoring circuit in one embodiment. The voltage monitoring circuit 52 includes a third amplifier EC, a fourth amplifier ED, a logic OR gate TA, and a D flip-flop. The positive input terminal of the third amplifier EC is used to input a preset first comparison voltage V. A The negative input terminal of the third amplifier EC is used to input the monitoring voltage V. O The positive input terminal of the fourth amplifier ED is used to input a preset second comparison voltage V. B The negative input terminal of the fourth amplifier ED is used to input the monitoring voltage V. O Among them, the first comparison voltage V A Second comparison voltage V BThe voltage values ​​are the two endpoints of the preset monitoring threshold range. The two inputs of the OR gate circuit TA are connected to the outputs of the third amplifier EC and the fourth amplifier ED, respectively. The output of the OR gate circuit TA is connected to the input of the D flip-flop. The output of the D flip-flop is connected to the switching circuit 51, which is used to output the switching gate voltage signal SWITCH to the switching circuit 51.

[0065] In one embodiment, the voltage monitoring circuit 52 further includes a NAND gate circuit TB and a delay module. The output of the D flip-flop is connected to the delay module and one input of the NAND gate circuit TB, respectively. The other input of the NAND gate circuit TB is connected to the delay module. The output of the NAND gate circuit TB is connected to the reset terminal of the D flip-flop. The NAND gate circuit TB and the delay module are used to reset the D flip-flop when the output voltage of the LDO power supply recovers to a preset threshold, thereby stopping the output of the switching gate voltage signal SWITCH to the switching circuit 51. This allows the switching circuit 51 to restore the connection between the error amplifier circuit 1 and the regulating transistor circuit 2, and continues the connection from the error amplifier circuit 1 to the MOS transistor Q. MP Gate-loaded drive voltage V T .

[0066] In one embodiment of this application, an LDO power supply is also disclosed, including the transient response enhancement circuit described above.

[0067] Please refer to Figure 6 This is a circuit connection diagram of an LDO power supply in one embodiment. When the output load circuit 4 of the LDO power supply switches, the second DC power supply V at the output terminal... OUT When the voltage changes, the voltage monitoring circuit outputs a switching gate voltage signal SWITCH to the switching circuit 51. The switching circuit then charges one of the energy storage capacitors C in the energy storage circuit. m Connected between the error amplifier circuit and the regulating transistor circuit to charge the energy storage capacitor C. m The voltage obtained after charging is used as the boost voltage V. C Loaded into the regulating transistor circuit MOSFET Q MP On the gate. Taking the LDO power supply switching from light load to heavy load as an example, the energy storage capacitor C m After entering the circuit, the voltage on the gate will be higher than before (setting the boost voltage V). C Greater than the driving voltage V T This allows for a rapid increase in the power transistor's output current, thereby improving the transient response speed.

[0068] In one embodiment, the error amplifier circuit of the LDO power supply includes the first amplifier EA and the output voltage regulator capacitor C. A In the differential amplifier circuit, the positive input terminal of the first amplifier EA is used to input the first DC power supply V.REF The negative input terminal of the first amplifier EA in the differential amplifier circuit is used to input the sampling voltage V. REF The output of the first amplifier EA in the differential amplifier circuit is connected to the transient response enhancement circuit. For example... Figure 6 As shown, the output voltage regulator capacitor C A One end of the capacitor is connected to the output terminal of the first amplifier EA in the differential amplifier circuit, and the other end is grounded. The output voltage regulator capacitor C... A The driving voltage V used for the output of the error amplifier circuit T Stabilize the voltage.

[0069] Please refer to Figure 7 In one embodiment, an energy storage capacitor C is selected. m The voltage value and the monitoring voltage V O A schematic diagram of the correspondence is shown. In one embodiment, the switching circuit 51 is based on the energy storage capacitor C after charging. m The voltage value is selected by choosing the capacitor, and the selected capacitor voltage value is the same as the monitoring voltage V. O The voltage value is related to the difference between the preset monitoring threshold range and the voltage value.

[0070] Please refer to Figure 8 This is a schematic diagram comparing the output voltage recovery of an LDO with and without a transient response enhancement circuit in one embodiment. Figure 8 It can be clearly seen that the output voltage recovery speed of the circuit with transient response enhancement is much greater than that of the circuit without transient response enhancement.

[0071] The LDO power supply disclosed in this embodiment includes a transient response enhancement circuit positioned between the error amplifier circuit and the regulating transistor circuit of the LDO power supply. This circuit comprises a switching circuit, a voltage monitoring circuit, and an energy storage circuit. When the voltage monitoring circuit detects that the output voltage of the LDO power supply is not within the output control threshold range, the switching circuit applies a preset voltage enhancement value from the energy storage circuit to the gate of the MOS transistor in the regulating transistor circuit of the LDO power supply, thereby controlling the output voltage of the LDO power supply to quickly recover to the output control threshold range. Because the recovery speed of the LDO power supply output voltage is instantly increased by directly replacing the gate voltage of the MOS transistor in the regulating transistor circuit, the PSRR characteristic of the LDO power supply is improved.

[0072] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A transient response enhancement circuit for LDO power supplies, characterized in that, The LDO power supply is used to convert the first DC power supply V REF Convert to a second DC power supply V OUT The output is as follows: The LDO power supply includes an error amplifier circuit, a regulating transistor circuit, and a feedback circuit; the feedback circuit is used to sample the second DC power supply V through a voltage divider circuit. OUT Perform voltage divider sampling to obtain the sampling voltage V FB The error amplifier circuit includes a first amplifier EA, used to adjust the first DC power supply V. REF and sampling voltage V FB Perform differential amplification, and then obtain the driving voltage V after differential amplification. T The output is supplied to the regulating transistor circuit; the regulating transistor circuit includes a MOSFET Q. MP Used to convert the driving voltage V T Loaded to the MOS transistor Q MP The gate of the MOS transistor Q is used to control the MOS transistor Q. MP The voltage value of the gate is used to control the second DC power supply V. OUT The voltage value is maintained within a preset output control threshold range; The transient response enhancement circuit is disposed between the error amplifier circuit and the regulating transistor circuit, and the transient response enhancement circuit is used to monitor the second DC power supply V. OUT The voltage value, and when the second DC power supply V OUT When the voltage value is not within the output control threshold range, the connection between the error amplifier circuit and the regulating transistor circuit is disconnected by the switching circuit, and an enhanced voltage V of a preset voltage value is applied. C Replace the driving voltage V T Loaded to the MOS transistor Q MP The gate of the second DC power supply V is used to control the second DC power supply V. OUT The voltage value recovers to the output control threshold range more quickly; The transient response enhancement circuit includes a switching circuit, a voltage monitoring circuit, and an energy storage circuit; The voltage monitoring circuit is connected to the feedback circuit and the switching circuit, and the voltage monitoring circuit is used to monitor the sampled voltage V. FB and / or the second DC power supply V OUT When the monitoring voltage V is obtained O When the voltage is not within a preset monitoring threshold range, a switching gate voltage signal SWITCH is output to the switching circuit; wherein, the preset monitoring threshold range is related to the output control threshold range, and when the monitoring voltage V... O When the voltage is not within a preset monitoring threshold range, the second DC power supply V OUT The voltage value is also not within the output control threshold range; The switching circuit is connected to the error amplifier circuit, the energy storage circuit, and the adjustment transistor circuit, respectively. When the switching circuit does not receive the switching gate voltage signal SWITCH, it connects the error amplifier circuit and the adjustment transistor circuit to drive the voltage V output by the error amplifier circuit. T The MOS transistor Q is loaded into the regulating transistor circuit. MP The gate; when the switching circuit receives the switching gate voltage signal SWITCH, it disconnects the error amplifier circuit and the adjustment tube circuit, and electrically connects the energy storage circuit to the adjustment tube circuit; The energy storage circuit is used to supply energy to the MOS transistor Q in the adjustment transistor circuit after being electrically connected to the switching circuit via the switching circuit. MP The gate is loaded with the enhanced voltage V C To replace the driving voltage V T ; Wherein, the monitoring voltage V O The greater the difference between the voltage value and the preset monitoring threshold range, the greater the increase in the enhanced voltage V. C The higher the voltage value; The energy storage circuit includes an energy storage capacitor C. m The transient response enhancement circuit further includes a charging circuit; the charging circuit is used to charge the energy storage capacitor C in the energy storage circuit through the switching circuit. m Charge; When the energy storage circuit is electrically connected to the regulating tube circuit through the switching circuit, the switching circuit charges the energy storage capacitor C in the energy storage circuit. m Connected between the error amplifier circuit and the adjustment transistor circuit to charge the energy storage capacitor C. m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate; The charging circuit includes a first charging input terminal, a second charging input terminal, a first discharging output terminal, a second discharging output terminal, a second amplifier EB, a first switch K1, a second switch K2, and a switched capacitor C. S ; The first charging input terminal is used to input a preset charging voltage V. RECT ; The second charging input terminal is used to input the sampling voltage V. FB ; The first discharge output terminal and the second discharge output terminal are connected to the energy storage circuit and are used to provide charging power to the energy storage circuit. The positive input terminal of the second amplifier EB is connected to the first charging input terminal, the negative input terminal of the second amplifier EB is connected to the second discharging output terminal, and the output terminal of the second amplifier EB is connected to the first discharging output terminal. One end of the first switch K1 is connected to the second charging input terminal, and the other end is connected to the switched capacitor C. S The positive terminal of the switched capacitor C is connected. S The negative connection terminal is grounded; One end of the second switch K2 is connected to the second discharge output terminal, and the other end is connected to the switched capacitor C. S Connect the positive connection terminal; The switching on and off of the first switch K1 and the second switch K2 are controlled by the switching circuit.

2. The transient response enhancement circuit as described in claim 1, characterized in that, The energy storage circuit includes at least two energy storage capacitors C. m The charging circuit is used to charge each energy storage capacitor C in the energy storage circuit through the switching circuit. m Charging is performed, and each of the energy storage capacitors C m The voltage values ​​after charging are all different; When the energy storage circuit is electrically connected to the regulating tube circuit through the switching circuit, the switching circuit will charge one of the energy storage capacitors C in the energy storage circuit. m Connected between the error amplifier circuit and the adjustment transistor circuit to charge the energy storage capacitor C. m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate; The switching circuit is based on the energy storage capacitor C after charging. m The voltage value is selected by choosing the capacitor, and the selected capacitor voltage value is the same as the monitored voltage V. O The voltage value is related to the difference between the preset monitoring threshold range and the voltage value.

3. The transient response enhancement circuit as described in claim 2, characterized in that, The energy storage circuit includes at least two energy storage units, each energy storage unit including a first connection terminal, a second connection terminal, a third switch K3, a fourth switch K4, and an energy storage capacitor C. m ; The first connection terminal of the energy storage unit is used to control the connection to the first discharge output terminal of the charging circuit or the error amplifier circuit through the switching circuit. The second connection terminal of the energy storage unit is used to control the connection to the second discharge output terminal of the charging circuit or to the regulating tube circuit via the switching circuit. One end of the third switch K3 is connected to the first connection terminal of the energy storage unit, and the other end is connected to the energy storage capacitor C. m The positive connection terminal is connected, one end of the fourth switch K4 is connected to the second connection terminal of the energy storage unit, and the other end is connected to the energy storage capacitor C. m Connect the negative terminal; When the switching circuit controls the first connection terminal of the energy storage unit to connect to the first discharge output terminal of the charging circuit, and connects the second connection terminal of the energy storage unit to the second discharge output terminal of the charging circuit, the charging circuit supplies power to the energy storage capacitor C. m Charge; When the switching circuit controls the first connection terminal of the energy storage unit to be connected to the error amplifier circuit, and connects the second connection terminal of the energy storage unit to the adjustment tube circuit, the energy storage capacitor C m The voltage obtained after charging is used as the enhanced voltage V. C The MOS transistor Q is loaded into the regulating transistor circuit. MP On the gate.

4. The transient response enhancement circuit as described in claim 2, characterized in that, The voltage monitoring circuit includes a third amplifier EC, a fourth amplifier ED, a logic OR gate circuit TA, and a D flip-flop; The positive input terminal of the third amplifier EC is used to input a preset first comparison voltage V. A The negative input terminal of the third amplifier EC is used to input the monitoring voltage V. O The positive input terminal of the fourth amplifier ED is used to input a preset second comparison voltage V. B The negative input terminal of the fourth amplifier ED is used to input the monitoring voltage V. O Among them, the first comparison voltage V A Second comparison voltage V B The voltage values ​​are the two endpoints of the preset monitoring threshold range; The two input terminals of the OR gate TA are connected to the output terminals of the third amplifier EC and the fourth amplifier ED, respectively, and the output terminal of the OR gate TA is connected to the input terminal of the D flip-flop. The output of the D flip-flop is connected to the switching circuit and is used to output the switching gate voltage signal SWITCH to the switching circuit.

5. The transient response enhancement circuit as described in claim 4, characterized in that, The voltage monitoring circuit also includes a logic NAND gate circuit TB and a delay module; The output of the D flip-flop is connected to the input of the delay module and one input of the NAND gate TB. The other input of the NAND gate TB is connected to the output of the delay module. The output of the NAND gate TB is connected to the reset terminal of the D flip-flop.

6. An LDO power supply, characterized in that, Includes the transient response enhancement circuit as described in any one of claims 1 to 5.

7. The LDO power supply as described in claim 6, characterized in that, The error amplifier circuit in the LDO power supply includes a first amplifier EA and an output voltage regulator capacitor C. A ; The positive input terminal of the first amplifier EA in the error amplifier circuit is used to input the first DC power supply V. REF The negative input terminal of the first amplifier EA of the error amplifier circuit is used to input the sampling voltage V. FB The output terminal of the first amplifier EA of the error amplifier circuit is connected to the transient response enhancement circuit; The output voltage regulator capacitor C A One end is connected to the output terminal of the first amplifier EA of the error amplifier circuit, and the other end is grounded.

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