Calibration circuit and control method thereof, and memory device

Abstract

The embodiments of the present disclosure propose a calibration circuit, a control method thereof, and a memory device, wherein the calibration circuit includes: a calibration control circuit and an impedance calibration circuit; wherein the calibration control circuit is used to trigger the impedance calibration circuit to enter an idle state upon receiving a first indication signal or after a preset time length selected according to a delay selection signal; the impedance calibration circuit is used to perform an impedance calibration operation upon receiving a calibration command in the idle state; and generate a second indication signal after completing the impedance calibration operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a calibration circuit and a control method thereof, and a memory device. Background Art

[0002] As memory device operating speeds increase, the signal swing width at the interface between the memory device and the memory controller generally decreases. However, as the swing width decreases, the signals transmitted between the memory device and the memory controller may be more susceptible to distortion due to impedance mismatch caused by variations in process, voltage, and temperature (PVT). Summary of the Invention

[0003] In view of this, the embodiments of the present disclosure provide a calibration circuit and a control method thereof, and a memory device. In one aspect, the embodiments of the present disclosure provide a calibration circuit, comprising: a calibration control circuit and an impedance calibration circuit; wherein,

[0004] The calibration control circuit is configured to trigger the impedance calibration circuit to enter an idle state upon receiving a first indication signal or after a preset time period selected according to a delay selection signal;

[0005] The impedance calibration circuit is configured to perform an impedance calibration operation upon receiving a calibration command in an idle state; and generate a second indication signal after completing the impedance calibration operation.

[0006] In the above solution, the calibration control circuit includes a frequency division circuit, a delay selection circuit and a logic operation circuit; wherein,

[0007] The frequency division circuit is used to receive a reference clock signal and perform multiple frequency division processes on the reference clock signal to generate multiple different frequency signals;

[0008] The delay selection circuit receives the plurality of frequency signals and the delay selection signal, and is configured to select one of the frequency signals as the third indication signal for output according to the delay selection signal;

[0009] The logic operation circuit is coupled to the delay selection circuit, and is configured to output a calibration control signal upon receiving the third indication signal or the first indication signal, so as to trigger the impedance calibration circuit to enter an idle state.

[0010] In the above solution, the calibration control circuit further includes a latch circuit, and the latch circuit is used to latch the calibration control signal, and the latched calibration control signal triggers the impedance calibration circuit to enter an idle state.

[0011] In the above solution, the delay selection circuit includes a data selector, a control input end of the data selector is used to receive the delay selection signal, and a plurality of data input ends of the data selector are respectively used to receive a plurality of different frequency signals.

[0012] In the above scheme, the frequency division circuit includes a plurality of triggers connected in series in a cascade relationship; the data input terminal of each trigger is connected to the data complementary output terminal, the data output terminal of the previous trigger of two adjacent triggers is connected to the clock input terminal of the next trigger, and the data output terminal of one trigger is connected to a data input terminal of the delay selection circuit.

[0013] In the above solution, the first trigger among the multiple triggers further includes a reset input terminal, and the reset input terminal is used to receive the fourth indication signal;

[0014] The multiple triggers are used to perform a reset operation when receiving the fourth indication signal.

[0015] In the above solution, the logic operation circuit includes an OR gate, the two input ends of the OR gate are respectively used to receive the third indication signal and the first indication signal, and the output end of the OR gate outputs the calibration control signal.

[0016] In the above solution, the calibration control circuit is further configured to trigger the impedance calibration circuit to enter a busy state when the impedance calibration circuit receives the calibration command.

[0017] Another aspect of the present disclosure provides a memory device, comprising: a plurality of memory chips; each memory chip comprising a calibration circuit as described in the above embodiment of the present disclosure; each memory chip having a signal receiving end and a signal transmitting end; the signal receiving ends of two adjacent memory chips among the plurality of memory chips being connected to the signal transmitting end, the plurality of signal receiving ends and the plurality of signal transmitting ends of the plurality of memory chips forming a ring topology;

[0018] The signal receiving end is used to receive a first indication signal, and the signal sending end is used to send a second indication signal; the first indication signal indicates that the previous memory chip of the current memory chip has completed the impedance calibration operation, and the second indication signal indicates that the current memory chip has completed the impedance calibration operation.

[0019] In the above solution, the preset duration selected by the delay selection signal is related to the number of the memory chips.

[0020] In the above solution, when the number of the memory chips is in different ranges, the preset duration of the delay selection signal selection is different;

[0021] The greater the number of memory chips corresponding to the different ranges, the longer the preset duration of the delay selection signal selection.

[0022] In the above solution, the memory chip includes a dynamic random access memory.

[0023] Another aspect of the embodiments of the present disclosure provides a control method for a calibration circuit, wherein the calibration circuit includes a calibration control circuit and an impedance calibration circuit; the control method includes:

[0024] The calibration control circuit triggers the impedance calibration circuit to enter an idle state upon receiving a first indication signal or after a preset time period according to a delay selection signal;

[0025] When the impedance calibration circuit receives a calibration command in an idle state, it performs an impedance calibration operation; after completing the impedance calibration operation, it generates a second indication signal.

[0026] In the above solution, the calibration control circuit includes a frequency division circuit, a delay selection circuit and a logic operation circuit; wherein,

[0027] The step of triggering the impedance calibration circuit to enter an idle state after a preset time period according to the delay selection signal includes:

[0028] The frequency division circuit receives a reference clock signal and performs multiple frequency division processes on the reference clock signal to generate multiple different frequency signals;

[0029] The delay selection circuit receives the plurality of frequency signals and the delay selection signal, and selects one of the frequency signals as a third indication signal for output according to the delay selection signal;

[0030] When receiving the third indication signal or the first indication signal, the logic operation circuit outputs a calibration control signal to trigger the impedance calibration circuit to enter an idle state.

[0031] In the above solution, the method further includes: latching the quasi-control signal, and the latched calibration control signal triggers the impedance calibration circuit to enter an idle state.

[0032] In each embodiment of the present disclosure, the calibration control circuit can trigger the impedance calibration circuit to enter an idle state by receiving a first indication signal, or by receiving a delay selection signal and selecting a preset time length, etc., so that the impedance calibration circuit can perform the impedance calibration operation in a timely manner after receiving the impedance calibration command; in other words, when the calibration control circuit does not receive the first indication signal, it can select an appropriate waiting time length according to the actual situation of the memory device, thereby avoiding the delay of the next calibration operation caused by a fixed waiting time length, thereby reducing the overall calibration time length of the memory device and improving the multiplexing capability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the connection of multiple memory chips in a memory device provided in an embodiment of the present disclosure;

[0034] Figure 2 A schematic diagram of the corresponding relationship between the number of memory chips and the waiting time provided in an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram illustrating the connection of multiple memory chips in another memory device provided in an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of the structure of a calibration circuit provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of the corresponding relationship between different delay selection signals and preset time lengths provided in an embodiment of the present disclosure;

[0038] Figure 6 A schematic diagram of the composition of a calibration control circuit provided in an embodiment of the present disclosure;

[0039] Figure 7 A schematic diagram illustrating the principle of a calibration circuit provided in an embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of an implementation of a frequency division circuit provided in an embodiment of the present disclosure;

[0041] Figure 9 A schematic diagram of an implementation of a delay selection circuit provided in an embodiment of the present disclosure;

[0042] Figure 10 The present invention is a flowchart illustrating an implementation of a control method for a calibration circuit provided in an embodiment of the present invention.

[0043] Reference numerals

[0044] 10, 30 - memory device; 101, 301 - memory chip; 302 - signal receiving end; 303 - signal transmitting end; 40 - calibration circuit; 401 - calibration control circuit; 402 - impedance calibration circuit; 601 - frequency division circuit; 602 - delay selection circuit; 603 - logic operation circuit; 604 - latch circuit; 801 - first trigger; 802 - second trigger; 803 - third trigger; q0 - first frequency signal; q1 - second frequency signal; q2 - third frequency signal; Flag<1:0> - delay selection signal; Rx - first indication signal; Tx - second indication signal.

[0045] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0046] To make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0048] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0049] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0050] In the embodiments of the present disclosure, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0051] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0052] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0053] The calibration circuits described in the embodiments of the present disclosure can be used in a variety of memory chips or logic chips. In some embodiments, the memory chip can be a dynamic random access memory (DRAM) chip, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), etc. The following embodiments are described using DRAM as an example. However, it should be understood that the following description of DRAM is only for illustration of the present disclosure and is not intended to limit the scope of the present disclosure.

[0054] As the operating speed of dynamic random access memory (DRAM) increases, the speed of signal transmission within the memory device within the DRAM also increases. To minimize the delay required during signal transmission, reducing the signal swing width is typically employed to address the aforementioned issue. However, as the swing width decreases, the signal transmitted between the memory device and the memory controller becomes more susceptible to impedance mismatch caused by PVT variations, leading to distortion. This can result in distorted data within the memory device or misjudgment of signal levels.

[0055] To alleviate these adverse situations, the memory device can be provided with an on-chip termination (ODT, On-Die Termination, also known as "on-chip terminal resistance") for providing an adjustable termination impedance value. For example, when a signal (such as a command, data, etc.) is provided to the memory device, the impedance value of the on-chip termination can be adjusted to reduce the impedance mismatch. In actual operation, impedance calibration is usually performed periodically to adjust the impedance value of the on-chip termination, thereby facilitating impedance matching, and maintaining and calibrating the integrity of the signal and the data window in real time. However, the design specifications of dynamic random access memory usually require that the impedance calibration circuit must complete the calibration within a set time period, and the existing impedance calibration circuit has a situation where the calibration cannot be completed in time due to reasons such as the calibration time period.

[0056] In some embodiments, reference Figure 1 , Figure 1 shows a schematic diagram of a memory device, wherein the memory device 10 includes multiple memory chips 101, which are connected in sequence to form a ring topology. During an impedance calibration operation, each of the multiple memory chips 101 is connected to an input / output voltage (VDDQ) and sequentially performs the impedance calibration operation after receiving an impedance calibration command (ZQ Cal.). During the impedance calibration process in this ring topology, after the previous memory chip completes the impedance calibration operation, it sends an impedance calibration completion signal (Tx). After receiving this signal (Rx), the next memory chip begins the impedance calibration operation, and this continues until all memory chips 101 have completed the calibration. After the current impedance calibration operation is completed, the device enters an idle state. Upon receiving another impedance calibration command in the idle state, the device can perform the next impedance calibration operation. However, if the device does not receive an impedance calibration completion signal from the last memory chip, it cannot enter the idle state. In this case, it waits for a period of time (the duration required for the impedance calibration command to be latched) before entering the idle state to facilitate the next impedance calibration operation. The latching time length of the impedance calibration command for the next memory chip is generally set to 6 microseconds (μs) to ensure that the previous memory chip in the ring topology structure can complete the impedance calibration operation.

[0057] It should be noted that the waiting time mentioned above is different depending on the number of memory chips in the ring topology. The fewer the number of memory chips, the shorter the time it takes for the impedance calibration command to be latched. The more the number of memory chips, the longer the time it takes for the impedance calibration command to be latched. Figure 2 , Figure 2 FIG2 shows the correspondence between the number of memory chips and the time length for which the impedance calibration command needs to be latched, wherein when the number of memory chips in the memory device is 4 or less, the time length tZQCAL4 for which the impedance calibration command needs to be latched is at least 1.5 μs; when the number of memory chips is 5 to 8, the time length tZQCAL8 for which the impedance calibration command needs to be latched is at least 3 μs; when the number of memory chips is 9 to 16, the time length tZQCAL16 for which the impedance calibration command needs to be latched is at least 6 μs; however, in the above embodiment, in order to ensure that all memory chips in the ring topology have completed the calibration operation, regardless of the number of memory chips in the memory device, the latch time length of the impedance calibration command is set to 6 μs. This will increase the calibration time length of the memory device and reduce the multiplexing capability of the memory chips.

[0058] Based on this, a calibration circuit is proposed in an embodiment of the present disclosure, which can flexibly select the waiting time (latch time of the calibration command) according to the number of memory chips, so as to reduce the calibration time of the memory device in an overall sense and improve the reuse capability of the memory chips. Figure 3 and Figure 4 , Figure 3 shows another schematic diagram of a memory device, Figure 4 FIG shows a schematic diagram of a calibration circuit in an embodiment. It should be noted that: Figure 1 The memory device shown is also applicable to the embodiment of the present disclosure; wherein, Figure 3 The memory device 30 shown in the figure is provided with 8 memory chips 301, each memory chip 301 is provided with a calibration circuit 40, and each memory chip 301 has a signal receiving end 302 and a signal sending end 303, the signal receiving ends 302 of two adjacent memory chips in the multiple memory chips are connected to the signal sending end 303, and the multiple signal receiving ends 302 and the multiple signal sending ends 303 of the multiple memory chips are connected in sequence to form a ring topology structure; the signal receiving end 302 of each memory chip 301 can be used to receive a first indication signal (Rx), and the signal sending end 303 can be used to send a second indication signal (Tx), wherein the first indication signal is used to indicate that the previous memory chip of the current memory chip has completed the impedance calibration operation, and the impedance calibration operation can be performed on the current memory chip, and the second indication signal is used to indicate that the current memory chip has completed the impedance calibration operation.

[0059] refer to Figure 4 The calibration circuit 40 includes a calibration control circuit 401 and an impedance calibration circuit 402; wherein, the calibration control circuit 401 is used to trigger the impedance calibration circuit 402 to enter an idle state when receiving a first indication signal or after a preset time length according to a delay selection signal, and the impedance calibration circuit 402 is used to perform an impedance calibration operation when receiving a calibration command in the idle state; after completing the impedance calibration operation, a second indication signal is generated.

[0060] In some embodiments, after the previous memory chip completes the impedance calibration operation, it sends an indication signal indicating that the impedance calibration operation is completed. After the current memory chip receives the first indication signal indicating that the current memory chip can perform the impedance calibration operation, it triggers the impedance calibration circuit 402 to enter an idle state.

[0061] In other embodiments, after the previous memory chip completes the impedance calibration operation, when no indication signal indicating the completion of the impedance calibration operation is issued, the calibration control circuit 401 can select a preset time length from multiple preset time lengths based on the received delay selection signal, and trigger the impedance calibration circuit 402 to enter an idle state after the preset time length; the preset time length is the waiting time length (the latching time length of the impedance calibration command).

[0062] In some embodiments, a preset duration selected by the delay selection signal is related to the number of the memory chips.

[0063] Specifically, when the number of the memory chips is in different ranges, the preset duration of the delay selection signal selection is different; wherein, the more the number of memory chips corresponding to the different ranges is, the longer the preset duration of the delay selection signal selection is.

[0064] Exemplary, reference Figure 5 , Figure 5 A schematic diagram shows the corresponding relationship between different numbers of memory chips and preset durations. When the number of memory chips N is within a first numerical range (e.g., the delay selection signal is 00), the delay selection signal selects the first preset duration, so that the impedance calibration command is extended by the first preset duration, triggering the impedance calibration circuit to enter an idle state. Here, the first numerical range can be 0 < N ≤ 4, and the first preset duration is 1.5 μs. In other words, when the number of memory chips is 0 < N ≤ 4, after the previous memory chip completes the impedance calibration operation, the impedance calibration command corresponding to the current memory chip is latched for 1.5 μs. After 1.5 μs, the next impedance calibration operation can be performed.

[0065] When the number of memory chips is within the second numerical range (such as the delay selection signal is 01), the delay selection signal selects the second preset time length, so that the impedance calibration command is extended by the second preset time length, and the impedance calibration circuit is triggered to enter the idle state. Here, the second numerical range can be 5≤N≤8, and the second preset time length is 3μs. Figure 3 The figure shows a case where the number of memory chips is 8, that is, the preset time length is 8 μs.

[0066] When the number of memory chips is within a third numerical range (such as the delay selection signal is 10), the delay selection signal selects a third preset time length, so that the impedance calibration command is extended by the third preset time length, and then the impedance calibration circuit is triggered to enter an idle state. Here, the third numerical range can be 9≤N≤16, and the third preset time length is 6μs.

[0067] It should be noted that Figure 5 The data shown in the figure is only used as an example and is not used to limit the corresponding relationship between the total number of memory chips and the preset time length selected by the delay selection signal in the embodiment of the present disclosure.

[0068] Based on this, in embodiments of the present disclosure, different waiting times can be selected based on the number of memory chips in the memory device. This allows the current memory chip, if it has not received an indication signal indicating the completion of the impedance calibration operation from the last memory chip that previously performed the impedance calibration operation, to perform the next impedance calibration operation after waiting for a preset time period that matches the number of memory chips. Compared to the aforementioned embodiments in which the waiting time is set to 6μs, some embodiments of the present disclosure can reduce the corresponding impedance calibration command latch time to 1.5μs or 3μs. This reduces the waiting time, thereby reducing the calibration time of the memory device as a whole and improving the multiplexing capability of the memory chips.

[0069] In order to understand the present disclosure more clearly, Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 The calibration control circuit and the impedance calibration circuit in the above embodiment are described in detail. Figure 6 A schematic diagram of a calibration control circuit provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the specific structure of a calibration circuit provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of a connection relationship of multiple triggers in a cascade relationship connected in series provided in an embodiment of the present disclosure; Figure 9 The present invention is a schematic diagram of an implementation of a delay selection circuit provided in an embodiment of the present disclosure.

[0070] In some embodiments, reference Figure 6 、 Figure 7 、 Figure 8 The calibration control circuit 301 includes a frequency division circuit 601, a delay selection circuit 602 and a logic operation circuit 603; wherein,

[0071] The frequency division circuit 601 is used to receive a reference clock signal Tck and perform multiple frequency division processes (div) on the reference clock signal Tck to generate multiple different frequency signals (such as q0, q1, q2);

[0072] The delay selection circuit 602 receives the plurality of frequency signals and the delay selection signal, and is configured to select one of the frequency signals as a third indication signal (Master timeout) to be output according to the delay selection signal;

[0073] The logic operation circuit 603 is coupled to the delay selection circuit, and is configured to output a calibration control signal upon receiving the third indication signal or the first indication signal, so as to trigger the impedance calibration circuit to enter an idle state.

[0074] For example, refer to Figure 6 and Figure 7 The frequency division circuit 601 performs frequency division processing on the received reference clock signal Tck for multiple times, such as three times, and outputs three different frequency signals after the frequency division processing, respectively. Figure 5 The calibration control circuit 301 can select different waiting times according to different frequency signals.

[0075] In some specific embodiments, the frequency dividing circuit 601 includes a plurality of triggers connected in series in a cascade relationship; the data input terminal of each trigger is connected to the data complementary output terminal, the data output terminal of the previous trigger of two adjacent triggers is connected to the clock input terminal of the next trigger, and the data output terminal of one trigger is connected to a data input terminal of the delay selection circuit.

[0076] Exemplary, reference Figure 8The frequency division circuit 601 includes three triggers connected in series, namely a first trigger 801, a second trigger 802, and a third trigger 803; the clock input terminal C of the first trigger 801 is used to receive the reference clock signal Tck, the data input terminal D of the first trigger 801 is connected to the data complementary output terminal Q of the first trigger 801, the data output terminal Q of the first trigger 801 is connected to the clock input terminal C of the second trigger 802, the data input terminal D of the second trigger 802 is connected to the data complementary output terminal Q of the second trigger 802, the data output terminal Q of the second trigger 802 is connected to the clock input terminal C of the third trigger 803, the data input terminal D of the third trigger 803 is connected to the data complementary output terminal Q of the third trigger 803, and the data output terminal Q of the third trigger 803 is used to output the frequency division data.

[0077] It should be noted that the data output terminals Q of the first trigger 801, the second trigger 802, and the third trigger 803 are respectively used to output different frequency signals. For example, the data output terminal Q of the first trigger 801 is used to output the first frequency signal q0 after the first frequency division (div1), the data output terminal Q of the second trigger 802 is used to output the first frequency signal q1 after the second frequency division (div2), and the data output terminal Q of the third trigger 803 is used to output the first frequency signal q2 after the third frequency division (div3).

[0078] In some specific embodiments, the first frequency signal q0 is a target frequency signal, such as Tck or other frequency signals generated by Tck, the second frequency signal q1 is a clock signal divided by 2 of q0, and the third frequency signal q2 is a clock signal divided by 2 of q1; in this way, the calibration control circuit 301 can select frequency signals generated by different triggers according to the number of memory chips in the memory device to select different waiting times.

[0079] In some embodiments, the first trigger among the plurality of triggers further includes a reset input terminal, wherein the reset input terminal is configured to receive a fourth indication signal;

[0080] The plurality of triggers are configured to perform a reset operation upon receiving the fourth indication signal. Here, the fourth indication signal is further configured to indicate that the impedance calibration circuit 302 is in an idle state. That is, if the impedance calibration circuit 402 is busy, the frequency divider circuit 601 operates normally; if the impedance calibration circuit 402 is idle, the frequency divider circuit 601 stops the frequency division operation.

[0081] refer to Figure 7 、 Figure 8Among the three triggers, the first trigger 801 further includes a reset input terminal R for receiving a fourth indication signal, where the fourth indication signal is used to instruct a reset operation to be performed on the first trigger 801 in the frequency dividing circuit 601 .

[0082] In actual applications, after the frequency division circuit 601 divides the reference clock (div), multiple different frequency signals are transmitted to the delay selection circuit 602. The delay selection circuit 602 receives the multiple different frequency signals and the delay selection signal Flag<1:0>, and selects one of the multiple different frequency signals according to the indication of the delay selection signal Flag<1:0>, and outputs the selected frequency signal as the third indication signal (Mastertimeout).

[0083] In some embodiments, the delay selection circuit 602 includes a data selector, a control input terminal of the data selector is used to receive the delay selection signal, and a plurality of data input terminals of the data selector are used to receive a plurality of different frequency signals respectively.

[0084] refer to Figure 6 、 Figure 7 The delay selection circuit 602 may include a data selector (Mux, Multiplexer), which can selectively transmit data received by multiple receiving ends to a single shared data channel. During the multi-channel data transmission process, any one of the channels can be selected as needed. The data selector includes a control input, multiple data inputs, and a signal output. The control input of the data selector is used to receive a delay selection signal Flag<1:0>. The multiple data inputs of the data selector are respectively used to receive multiple different frequency signals (e.g., q0, q1, and q2). The signal output of the data selector is used to output a selected frequency signal as a third indication signal (Mastertimeout).

[0085] In some specific embodiments, reference Figure 9 The delay selection circuit 602 may include a 2:4 decoder and three data selectors in a cascade relationship. Specifically, the two bits of data Flag<0> and Flag<1> corresponding to Flag<1:0> are input into the 2:4 decoder, and the 2:4 decoder decodes the two bits of input data into corresponding four bits of data D0, D1, D2, and D3. Figure 9 The truth table corresponding to the 2-4 decoder shown on the left is shown in Table 1:

[0086] Table 1

[0087] Flag<1> Flag<0> D3 D2 D1 D0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

[0088] D0, D1, and D2 output by the 24 decoder are respectively connected to the control input terminals of three data 2-to-1 data selectors. The last 2-to-1 data selector will output one of q0, q1, and q2 according to the input Flag <0> and Flag <1>, and the value output by the last 2-to-1 data selector will be used as the output value of the delay selection circuit 602.

[0089] For example, when Flag<0> is 0 and Flag<1> is 0, D0, D1, and D2 are 1, 0, and 0 respectively, and the value output by the last two-choice data selector is q0; when Flag<0> is 1 and Flag<1> is 0, D0, D1, and D2 are 0, 1, and 0 respectively, and the value output by the last two-choice data selector is q1; when Flag<0> is 0 and Flag<1> is 1, D0, D1, and D2 are 0, 0, and 1 respectively, and the value output by the last two-choice data selector is q2. Figure 7 , the logic operation circuit 603 is coupled to the delay selection circuit 602, and the delay selection circuit 602 can transmit the third indication signal (Mastertimeout) to the logic operation circuit 603; in actual application, the logic operation circuit 603 is not only used to receive the third indication signal (Mastertimeout), but also used to receive the first indication signal Rx. When the logic operation circuit 603 receives the third indication signal (Mastertimeout) or the first indication signal Rx, it outputs a calibration control signal to trigger the impedance calibration circuit 302 to enter an idle state.

[0090] In this way, the impedance calibration circuit can be triggered to enter the idle state in a timely manner according to multiple indication signals, reducing the time it takes for the impedance calibration circuit to latch the impedance calibration command after receiving the impedance calibration command, thereby reducing the calibration time of the memory device and improving the multiplexing capability of the memory chip.

[0091] In some specific embodiments, the logic operation circuit 603 includes an OR gate, wherein two input terminals of the OR gate are respectively used to receive the third indication signal and the first indication signal, and an output terminal of the OR gate outputs the calibration control signal.

[0092] refer to Figure 7As long as one or more conditions are met, the OR gate will execute the content indicated by the corresponding condition. For example, when the logic operation circuit 603 only receives the first indication signal Rx, the first indication signal will be issued as the calibration control signal. When the logic operation circuit 603 only receives the third indication signal (Master timeout), the third indication signal (Master timeout) will be issued as the calibration control signal. Here, the OR gate includes two input terminals and an output terminal, wherein the two input terminals are respectively used to receive the third indication signal and the first indication signal, and the output terminal is used to output the calibration control signal.

[0093] It should be noted that, in some embodiments, the logic operation circuit 603 may also include but is not limited to a combination of multiple other logic circuits that implement the OR gate principle, which will not be elaborated here one by one.

[0094] In some embodiments, reference Figure 6 and Figure 7 The calibration control circuit 301 further includes a latch circuit 604, which is used to latch the calibration control signal. The latched calibration control signal triggers the impedance calibration circuit to enter an idle state. Figure 6 and Figure 7 The latch circuit 604 is connected to the logic operation circuit 603 and is used to receive the calibration control signal sent by the logic operation circuit 603 and latch the calibration control signal; the calibration control signal can be the first indication signal Rx or the third indication signal (Master timeout), which has been mentioned before and will not be repeated here.

[0095] It should be noted that if the logic operation circuit 603 first receives the third indication signal (Master timeout), it transmits the third indication signal (Master timeout) to the latch circuit 604. The latch circuit 604 latches the third indication signal and outputs the latched third indication signal as the calibration control signal to trigger the impedance calibration circuit 302 to enter the idle state. If the logic operation circuit 603 first receives the first indication signal Rx, it transmits the first indication signal Rx to the latch circuit 604. The latch circuit 604 latches the first indication signal and outputs the latched first indication signal as the calibration control signal to trigger the impedance calibration circuit 302 to enter the idle state.

[0096] In some embodiments, the calibration control circuit 301 is further configured to trigger the impedance calibration circuit 302 to enter a busy state when the impedance calibration circuit 302 receives the calibration command.

[0097] refer to Figure 7 After the impedance calibration circuit 302 enters the idle state, and when the impedance calibration circuit 302 receives the calibration command (ZQ Cal.), it starts to perform the impedance calibration operation. At this time, the impedance calibration circuit enters the busy state.

[0098] In some embodiments, after the calibration circuit 40 completes the impedance calibration operation, it generates a second indication signal Tx to indicate that the impedance calibration operation has been completed for the current memory chip and the impedance calibration operation can be performed on the next memory chip after the current memory chip.

[0099] In some embodiments, the calibration circuit 40 may further generate a calibration code (zqpd) after completing the impedance calibration operation. The calibration code is latched into an input-output circuit in a memory device.

[0100] Based on this, in each embodiment of the present disclosure, the calibration control circuit can trigger the impedance calibration circuit to enter an idle state by receiving a first indication signal, or by receiving a delay selection signal and selecting a preset time length, etc., so that the impedance calibration circuit can perform the impedance calibration operation in a timely manner after receiving the impedance calibration command; in other words, when the calibration control circuit does not receive the first indication signal, it can select a suitable waiting time length according to the actual situation of the memory device, thereby avoiding the delay of the next calibration operation caused by a fixed waiting time length, thereby reducing the overall calibration time length of the memory device and improving the multiplexing capability of the memory chip.

[0101] According to yet another aspect of an embodiment of the present disclosure, a memory system is provided. The memory system includes the memory device in the aforementioned embodiment and a memory controller coupled to the memory device.

[0102] According to another aspect of the present disclosure, a control method for a calibration circuit is provided, wherein the calibration circuit includes a calibration control circuit and an impedance calibration circuit; Figure 10 , the control method comprises the following steps:

[0103] Step S1001: the calibration control circuit triggers the impedance calibration circuit to enter an idle state upon receiving a first instruction signal or after a preset time period selected according to a delay selection signal;

[0104] Step S1002: When the impedance calibration circuit receives a calibration command in an idle state, it performs an impedance calibration operation; after completing the impedance calibration operation, it generates a second indication signal.

[0105] In some embodiments, the calibration control circuit includes a frequency division circuit, a delay selection circuit, and a logic operation circuit; wherein,

[0106] The step of triggering the impedance calibration circuit to enter an idle state after a preset time period according to the delay selection signal includes:

[0107] The frequency division circuit receives a reference clock signal and performs multiple frequency division processes on the reference clock signal to generate multiple different frequency signals;

[0108] The delay selection circuit receives the plurality of frequency signals and the delay selection signal, and selects one of the frequency signals as a third indication signal for output according to the delay selection signal;

[0109] When receiving the third indication signal or the first indication signal, the logic operation circuit outputs a calibration control signal to trigger the impedance calibration circuit to enter an idle state.

[0110] In some embodiments, the method further includes: latching the calibration control signal, wherein the latched calibration control signal triggers the impedance calibration circuit to enter an idle state.

[0111] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0112] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0114] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A calibration circuit, characterized in that: include: Calibration control circuit and impedance calibration circuit; wherein, The calibration control circuit is configured to trigger the impedance calibration circuit to enter an idle state upon receiving a first indication signal or after a preset time period selected according to a delay selection signal; The impedance calibration circuit is configured to perform an impedance calibration operation upon receiving a calibration command in an idle state; and generate a second indication signal after completing the impedance calibration operation; The calibration control circuit includes a frequency division circuit, a delay selection circuit and a logic operation circuit; wherein, The frequency division circuit is used to receive a reference clock signal and perform multiple frequency division processes on the reference clock signal to generate multiple different frequency signals; The delay selection circuit receives the plurality of frequency signals and the delay selection signal, and is configured to select one of the frequency signals as the third indication signal for output according to the delay selection signal; The logic operation circuit is coupled to the delay selection circuit, and is configured to output a calibration control signal upon receiving the third indication signal or the first indication signal, so as to trigger the impedance calibration circuit to enter an idle state.

2. The calibration circuit according to claim 1, wherein: The calibration control circuit further includes a latch circuit, and the latch circuit is used to latch the calibration control signal. The latched calibration control signal triggers the impedance calibration circuit to enter an idle state.

3. The calibration circuit according to claim 1, wherein: The delay selection circuit includes a data selector, a control input end of the data selector is used to receive the delay selection signal, and a plurality of data input ends of the data selector are respectively used to receive a plurality of different frequency signals.

4. The calibration circuit according to claim 1, wherein: The frequency division circuit includes a plurality of triggers connected in series in a cascade relationship; the data input terminal of each trigger is connected to the data complementary output terminal, the data output terminal of the previous trigger of two adjacent triggers is connected to the clock input terminal of the next trigger, and the data output terminal of one trigger is connected to a data input terminal of the delay selection circuit.

5. The calibration circuit according to claim 4, wherein: The first trigger among the plurality of triggers further includes a reset input terminal, wherein the reset input terminal is configured to receive a fourth indication signal; The multiple triggers are used to perform a reset operation when receiving the fourth indication signal.

6. The calibration circuit according to claim 1, wherein: The logic operation circuit includes an OR gate, wherein two input terminals of the OR gate are respectively used to receive the third indication signal and the first indication signal, and an output terminal of the OR gate outputs the calibration control signal.

7. The calibration circuit according to claim 1, wherein: The calibration control circuit is further configured to trigger the impedance calibration circuit to enter a busy state when the impedance calibration circuit receives the calibration command.

8. A memory device, characterized in that: include: A plurality of memory chips; each memory chip comprises a calibration circuit according to any one of claims 1 to 7; each memory chip has a signal receiving end and a signal transmitting end; the signal receiving ends of two adjacent memory chips among the plurality of memory chips are connected to the signal transmitting end, and the plurality of signal receiving ends and the plurality of signal transmitting ends of the plurality of memory chips form a ring topology structure; The signal receiving end is used to receive a first indication signal, and the signal sending end is used to send a second indication signal; The first indication signal indicates that the previous memory chip of the current memory chip has completed the impedance calibration operation, and the second indication signal indicates that the current memory chip has completed the impedance calibration operation.

9. The memory device according to claim 8, wherein: The preset duration selected by the delay selection signal is related to the number of the memory chips.

10. The memory device according to claim 9, wherein: When the number of the memory chips is in different ranges, the preset duration selected by the delay selection signal is different; The greater the number of memory chips corresponding to the different ranges, the longer the preset duration of the delay selection signal selection.

11. The memory device according to claim 8, wherein The memory chip includes a dynamic random access memory.

12. A control method for a calibration circuit, characterized in that: The calibration circuit includes a calibration control circuit and an impedance calibration circuit; and the control method includes: The calibration control circuit triggers the impedance calibration circuit to enter an idle state upon receiving a first indication signal or after a preset time period according to a delay selection signal; When the impedance calibration circuit receives a calibration command in an idle state, it performs an impedance calibration operation; after completing the impedance calibration operation, it generates a second indication signal; The calibration control circuit includes a frequency division circuit, a delay selection circuit and a logic operation circuit; wherein, The step of triggering the impedance calibration circuit to enter an idle state after a preset time period according to the delay selection signal includes: The frequency division circuit receives a reference clock signal and performs multiple frequency division processes on the reference clock signal to generate multiple different frequency signals; The delay selection circuit receives the plurality of frequency signals and the delay selection signal, and selects one of the frequency signals as a third indication signal for output according to the delay selection signal; When receiving the third indication signal or the first indication signal, the logic operation circuit outputs a calibration control signal to trigger the impedance calibration circuit to enter an idle state.

13. The control method according to claim 12, characterized in that: The method further includes: latching the calibration control signal, wherein the latched calibration control signal triggers the impedance calibration circuit to enter an idle state.

Images