A deep-base trench gate silicon carbide VDMOS and a preparation method thereof

Abstract

The invention provides a deep-base trench-gate silicon carbide VDMOS and a preparation method thereof, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the side of the silicon carbide substrate to form a drift region; performing ion implantation on the drift region to form a first drift layer, a current-balancing layer and a second drift layer; forming a base region, a P-type source region, a P-type well region and an N-type source region in the second drift layer; forming a barrier layer, etching to form a groove, performing dry oxygen oxidation in the groove to form a gate dielectric layer, wherein a groove is provided in the gate dielectric layer; depositing metal to form a gate metal layer and a source metal layer, removing the barrier layer and completing the preparation; improving the gate reliability of the device and reducing the on-resistance.

Description

Technical Field

[0001] The invention relates to a trench gate silicon carbide VDMOS with a deep base region and a preparation method thereof. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, which is widely used in electric vehicles, aerospace, power conversion and other fields. The device has achieved good characteristics within 1200V, and has replaced silicon MOSFET and IGBT within 1200V. With the improvement of device voltage resistance and the reduction of on-resistance, achieving high reliability and low on-resistance under high voltage resistance conditions has become a new requirement for the development of device technology; however, existing silicon carbide power devices still have internal current concentration, resulting in unreliable gate technology problems. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a deep-base trench-gate silicon carbide VDMOS and a preparation method thereof, which improves the gate reliability of the device and reduces the problem of current concentration inside the device, thereby achieving both low on-resistance and high reliability.

[0004] In a first aspect, the present invention provides a method for preparing a deep base trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift region;

[0006] Step 2: Perform ion implantation on the drift region to form a first drift layer, a current balancing layer and a second drift layer, and the ion implantation energy is 500-600kev;

[0007] Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, performing ion implantation into the second drift layer, forming a base region in the second drift layer, wherein the lower side of the base region is connected to the current balancing layer, and the ion implantation energy is 300-500kev;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the second drift layer, form a P-type source region on the base region, and the ion implantation energy is 300-400kev;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a P-type well region in the second drift layer, with an ion implantation energy of 200-300kev;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the second drift layer, form an N-type source region in the second drift layer, and the ion implantation energy is 100-200kev;

[0011] Step 7, removing the original barrier layer, forming a barrier layer, etching the barrier layer to form a through hole, etching the second drift layer and the P-type well region to form a groove, performing dry oxygen oxidation in the groove to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove;

[0012] Step 8: removing the original barrier layer, forming a barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift layer to a depth of 900 nm, and depositing metal to form a first source metal region;

[0014] Step 10, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the second drift layer, the etching depth is 300nm, deposit metal, and form a second source metal area; the source metal layer includes the first source metal layer and the second source metal area, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a deep-base trench-gate silicon carbide VDMOS, which is prepared by the method for preparing a deep-base trench-gate silicon carbide VDMOS according to the first aspect.

[0016] The advantages of the present invention are:

[0017] 1. The device adopts a deep base trench gate VDMOS device structure, which effectively suppresses the reliability problem caused by the electric field concentration at the corner of the trench gate of the silicon carbide VDMOS device through the deep base structure;

[0018] Second, an N-type current-balancing layer is constructed under the P-type base region of the device. The bottom of the device gate dielectric in the N-type current-balancing layer has a distance equal to the thickness of the P-type base region, which does not affect the protection of the device P-type base region to the gate dielectric;

[0019] 3. The high doping concentration of the N-type current balancing layer can effectively suppress the depth of the space charge region formed by the P-type base region and the N-type drift layer toward the device drain, thus avoiding the influence of the deep base region on the device on-resistance;

[0020] Fourth, the N-type current-balancing layer can realize the lateral distribution of the current under the gate structure, thereby reducing the overall on-resistance of the device, while suppressing the internal heat concentration of the device caused by current concentration, making the heat distribution uniform;

[0021] 5. The distance between the device's deep well and the corner of the gate dielectric layer does not affect the device's on-resistance, that is, the N-type drift layer above the N-type current-balancing layer is compressed by the gate when the device is turned on, so that this part of the conductive channel is not affected by the P-type base region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0023] Figure 1 The present invention is a flow chart of a method for preparing a trench gate silicon carbide VDMOS with a deep base region.

[0024] Figure 2 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 1 .

[0025] Figure 3 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 2 .

[0026] Figure 4 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 3 .

[0027] Figure 5 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 4 .

[0028] Figure 6 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 5 .

[0029] Figure 7 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 6 .

[0030] Figure 8 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 7 .

[0031] Fig. 9 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 8 .

[0032] Fig.10 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 9 .

[0033] Fig.11 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 10 .

[0034] Fig.12 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 10 one.

[0035] Fig.13 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 10 two.

[0036] Fig.14 A cross-sectional view of the process of a deep-base trench gate silicon carbide VDMOS according to the present invention Figure 10 three.

[0037] Fig.15 The schematic diagram of the trench gate silicon carbide VDMOS with a deep base region of the present invention is shown in FIG. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS with a deep base region, comprising the following steps:

[0044] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111, and epitaxially growing on the side of the silicon carbide substrate 101 to form a drift region a;

[0045] Step 2: Perform ion implantation on the drift region a to form a first drift layer 102, a current balancing layer 103 and a second drift layer 104, wherein the ion implantation energy is 500-600 kev;

[0046] Step 3, forming a barrier layer b on the second drift layer 104, etching the barrier layer b to form a through hole, performing ion implantation into the second drift layer 104, forming a base region 105 in the second drift layer 104, wherein the lower side of the base region 105 is connected to the current balancing layer 103, and the ion implantation energy is 300-500 kev;

[0047] Step 4: remove the original barrier layer b, re-form the barrier layer b, etch the barrier layer b to form a through hole, perform ion implantation into the second drift layer 104, and form a P-type source region 1051 on the base region 105. The ion implantation energy is 300-400kev;

[0048] Step 5: remove the original barrier layer b, re-form the barrier layer b, etch the barrier layer b to form a through hole, perform ion implantation into the second drift layer 104, form a P-type well region 106 in the second drift layer 104, and the ion implantation energy is 200-300kev;

[0049] Step 6: remove the original barrier layer b, re-form the barrier layer b, etch the barrier layer b to form a through hole, perform ion implantation into the second drift layer 104, and form an N-type source region 107 in the second drift layer 104. The ion implantation energy is 100-200 keV.

[0050] Step 7, removing the original barrier layer b, forming a barrier layer b, etching the barrier layer b to form a through hole, etching the second drift layer 104 and the P-type well region 106 to form a groove 112, performing dry oxygen oxidation in the groove 112 to form a gate dielectric layer 108, and the gate dielectric layer 108 is provided with a groove 1081;

[0051] Step 8: remove the original barrier layer b, form a barrier layer b, etch the barrier layer b to form a through hole, deposit metal, and form a gate metal layer 109;

[0052] Step 9, remove the original barrier layer b, re-form the barrier layer b, etch the barrier layer b to form a through hole, etch the second drift layer 104 to a depth of 900 nm, deposit metal, and form a first source metal region 1101;

[0053] Step 10, remove the original barrier layer b, re-form the barrier layer b, etch the barrier layer b to form a through hole, etch the second drift layer 104, the etching depth is 300nm, deposit metal, and form a second source metal region 1102; the source metal layer 110 includes a first source metal layer 1101 and a second source metal region 1102, remove the barrier layer b, and complete the preparation.

[0054] The doping concentration of the silicon carbide substrate 101 is 5e18cm -3 The doping concentration of the first drift layer 102 and the second drift layer 104 is 2e17cm -3 The doping concentration of the current balancing layer 103 is 1e18 cm -3 The doping concentration of the base region 105 is 1e18 cm -3 The doping concentration of the P-type source region 1051 is 4e19cm -3 The doping concentration of the P-type well region 106 is 5e17cm -3 The doping concentration of the N-type source region 107 is 8e18cm -3The silicon carbide substrate 101, the drift layer 102 and the current-balancing layer 103 are all N-type, the base region 105 is P-type, the thickness of the current-balancing layer 103 is 300nm, the width L1 of the second drift layer 104 is 1μm-1.5μm, and the width L2 of the gate dielectric layer 108 is 600nm-1100nm; the thickness of the P-type base region 105 is 600nm, and the thickness of the P-type source region 1051 is 300nm. m, the thickness of the P-type well region 106 is 300nm, the thickness of the N-type source region 107 is 300nm, the sidewall and bottom thickness of the gate dielectric layer 108 are 30nm, the thickness of the N-type current balancing layer 103 is 300nm, the thickness from the top of the source metal layer 110 to the top of the N-type source region 107 is 300nm, the device withstand voltage is 1200-3000V, and the distance between the P-type base region 105 and the nearest gate corner is controlled at 200nm;

[0055] The concentration of the N-type silicon carbide substrate 101 is to form a low-resistance ohmic contact with the drain metal layer 111 to reduce the on-resistance of the device. Its thickness is to ensure support during device epitaxy and improve process stability. The thickness and concentration of the N-type current equalizing layer 103 are to ensure the realization of internal current equalization while reducing the impact on the device's voltage resistance. The doping concentration and thickness of the P-type well region 106 are designed to ensure the device's gate control ability of the P-type well region 106. The doping concentrations of the first drift layer 102 and the second drift layer 104 are to take into account the compromise between the device's voltage resistance and on-resistance. The P-type source region 1051 and the N-type source region 107 are to achieve ohmic contact with the source metal layer 110. The thickness of the gate dielectric layer 108 is a compromise between the device's gate control ability and gate reliability.

[0056] The base region 105 of the device and the second drift layer 104 above the N-type current balancing layer 103 form a lateral space charge region, which is distributed and covers the corner of the device gate dielectric layer 108, thereby protecting the dielectric at the corner of the device gate. The lateral distance from the P-type base region 105 to the gate corner and the device gate width take into account the influence of the space charge region on the on-resistance of the second drift layer 104 above the N-type current balancing layer 103, thereby avoiding the influence of the structure on the on-resistance of the device.

[0057] An N-type current equalizing layer 103 is constructed below the P-type base region 105 of the device. In addition to achieving current equalization and suppressing current concentration, the N-type current equalizing layer 103 has a distance of the thickness of the P-type base region 105 at the bottom of the device gate dielectric layer 108, which does not affect the protection of the device P-type base region 105 on the gate dielectric layer 108. The N-type current equalizing layer 103 has a high doping concentration and can effectively suppress the depth of the space charge region formed by the P-type base region 105 and the first drift layer 102 toward the device drain direction, thereby avoiding the influence of the deep base region 105 on the device on the on-resistance.

[0058] like Fig.15 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0059] Silicon carbide substrate 101,

[0060] A first drift layer 102, wherein a lower side of the first drift layer 102 is connected to an upper side of the silicon carbide substrate 101;

[0061] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the first drift layer 102;

[0062] A second drift layer 104, wherein the lower side of the second drift layer 104 is connected to the upper side of the current balancing layer 103;

[0063] A base region 105, wherein the lower side of the base region 105 is connected to the upper side of the current balancing layer 103, the inner side of the base region 105 is connected to the outer side of the second drift layer 104, and a P-type source region 1051 is provided in the base region 105;

[0064] A P-type well region 106, wherein the lower side of the P-type well region 106 is connected to the upper side of the base region 105 and the upper side of the second drift layer 104;

[0065] An N-type source region 107, wherein the lower side of the N-type source region 107 is connected to the upper side of the P-type well region 106;

[0066] A gate dielectric layer 108, wherein the lower side of the gate dielectric layer 108 is connected to the upper side of the second drift layer 104, the outer side of the gate dielectric layer 108 is connected to the inner side of the P-type well region 106 and the inner side of the N-type source region 107, and a groove 1081 is provided in the gate dielectric layer 108;

[0067] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1081;

[0068] A source metal layer 110 , wherein the source metal layer 110 is respectively connected to the P-type source region 1051 , the P-type well region 106 , and the N-type source region 107 ;

[0069] and a drain metal layer 111 , wherein the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101 .

[0070] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a deep base trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift region; Step 2: performing ion implantation on the drift region to form a first drift layer, a current balancing layer and a second drift layer; Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, performing ion implantation into the second drift layer, forming a base region in the second drift layer, wherein the lower side of the base region is connected to the current balancing layer; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the second drift layer, and form a P-type source region on the base region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, performing ion implantation into the second drift layer, and forming a P-type well region in the second drift layer; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the second drift layer, and form an N-type source region in the second drift layer; Step 7, removing the original barrier layer, forming a barrier layer, etching the barrier layer to form a through hole, etching the second drift layer and the P-type well region to form a groove, performing dry oxygen oxidation in the groove to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove; Step 8: removing the original barrier layer, forming a barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift layer, depositing metal, and forming a first source metal region; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift layer, depositing metal, and forming a second source metal region; The source metal layer includes a first source metal layer and a second source metal region, and the barrier layer is removed to complete the preparation; The lower side of the first drift layer is connected to the upper side of the silicon carbide substrate; The lower side of the current equalizing layer is connected to the upper side of the first drift layer; the lower side of the second drift layer is connected to the upper side of the current equalizing layer; the lower side of the base region is connected to the upper side of the current equalizing layer, the inner side of the base region is connected to the outer side of the second drift layer, and a P-type source region is provided in the base region; the lower side of the P-type well region is connected to the upper side of the base region and the upper side of the second drift layer; the lower side of the N-type source region is connected to the upper side of the P-type well region; the lower side of the gate dielectric layer is connected to the upper side of the second drift layer, the outer side of the gate dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region, and a groove is provided in the gate dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected to the P-type source region, the P-type well region and the N-type source region; the drain metal layer is connected to the lower side of the silicon carbide substrate.

2. The method for preparing a deep-base trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the silicon carbide substrate is 5e18cm -3 The doping concentrations of the first drift layer and the second drift layer are both 2e17cm -3 The doping concentration of the current balancing layer is 1e18cm -3 , the doping concentration of the base region is 1e18 cm -3 The doping concentration of the P-type source region is 4e19cm -3 The doping concentration of the P-type well region is 5e17 cm -3 The doping concentration of the N-type source region is 8e18cm -3 .

3. The method for preparing a deep-base trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer and current balancing layer are all N-type, and the base region is P-type.

4. The method for preparing a deep-base trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the flow balancing layer is 300 nm.

5. The method for preparing a deep-base trench gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the second drift layer is 1 μm-1.5 μm, and the width of the gate dielectric layer is 600 nm-1100 nm.

6. The method for preparing a deep-base trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the base region is 600nm, and the thickness of the P-type source region is 300nm.

7. A deep-base trench-gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 6.

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