A gallium oxide vertical trench gate mosfet having a dielectric pillar and a method of manufacturing the same

Abstract

The application discloses a gallium oxide vertical trench gate MOSFET with a dielectric column and a preparation method thereof, and relates to the technical field of gallium oxide MOSFETs. The oxide dielectric column of the gallium oxide vertical trench gate MOSFET with the dielectric column provided by the application improves the potential distribution during breakdown, forms a capacitor between the source, the dielectric column and the drain in a reverse state, and the coupling effect makes the potential distribution in the dielectric column and the drift region more uniform in the vertical direction. In addition, the application also adjusts the breakdown position in the case without the dielectric column, thereby relieving the avalanche multiplication effect of the device, improving the breakdown voltage, and improving the reliability and performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gallium oxide MOSFET, and particularly relates to a gallium oxide vertical trench gate MOSFET with dielectric pillars and a preparation method thereof. BACKGROUND

[0002] Compared with traditional wide-bandgap semiconductor materials such as SiC and GaN, Ga2O3 has become an emerging important participant in the fields of electric energy switching, electronic appliance industry, power and radio frequency electronic industry due to its excellent material properties such as super-wide bandgap (4.5-4.9 eV) and high critical breakdown field (8 MV / cm), and high Baliga figure of merit (over 3000). In recent years, through the innovation and efforts of researchers in the field of semiconductors, various Ga2O3-based devices with excellent performance have been proposed, such as Schottky diodes (SBD), field effect transistors (MOSFET), and heterojunction diodes (HJD), which all indicate that Ga2O3 has great potential and development prospects in the application of power devices. However, the imperfect p-type doping technology of Ga2O3 hinders the further development of power devices.

[0003] In order to better exert the advantages of Ga2O3, compared with lateral MOSFET devices, vertical MOSFET devices have the advantages of occupying smaller size and higher power density. The existing vertical MOSFETs can be basically divided into two types: fin field effect transistors (FinFET) and current blocking type (CBL) field effect transistors. However, the forward opening of the FinFET device is largely dependent on the size of the fin channel, and the manufacturing process hinders the production efficiency and yield of the device. The CBL type field effect transistor has developed rapidly in recent years and has attracted the interest of a large number of researchers. The CBL type field effect transistor includes current aperture vertical electron transistors (CAVET), vertical diffusion barrier field effect transistors (VDBFET), and U-shaped trench gate field effect transistors (UMOSFET), but compared with the mature FinFET, the performance still needs to be improved. SUMMARY

[0004] Therefore, the present application aims to overcome the deficiencies of the prior art and provides a gallium oxide vertical trench gate MOSFET with dielectric pillars and a preparation method thereof. The gallium oxide vertical trench gate MOSFET with dielectric pillars provided by the present application can improve the performance of the device and alleviate the problem of low breakdown voltage of the conventional gallium oxide vertical trench gate MOSFET.

[0005] To achieve the above object, the technical scheme adopted by the present application is as follows: a gallium oxide vertical trench gate MOSFET with dielectric columns, comprising a drain metal layer, a high-doped N-type gallium oxide substrate layer, a low-doped N-type gallium oxide drift layer, an oxide dielectric column, a current blocking layer, a high-doped N-type ohmic contact layer, a source metal layer, an oxide dielectric layer, and a gate metal layer;

[0006] The drain metal layer, the high-doped N-type gallium oxide substrate layer, and the low-doped N-type gallium oxide drift layer are sequentially arranged, the upper surface of the drain metal layer is in contact with the lower surface of the high-doped N-type gallium oxide substrate layer, and the low-doped N-type gallium oxide drift layer is provided with the oxide dielectric columns on both sides thereof; the lower surface of the oxide dielectric column is in contact with the high-doped N-type gallium oxide substrate layer.

[0007] The current blocking layer and the high-doped N-type ohmic contact layer are sequentially arranged, and the lower surface of the current blocking layer is in contact with the low-doped N-type gallium oxide drift layer and the oxide dielectric column.

[0008] The vertical trench gate MOSFET is provided with a U-shaped trench, and the U-shaped trench is recessed downward from the upper surface of the high-doped N-type ohmic contact layer to the low-doped N-type gallium oxide drift layer.

[0009] The oxide dielectric layer covers the inner wall of the U-shaped trench and the upper surface of the high-doped N-type ohmic contact layer, the oxide dielectric layer has a through hole penetrating through the upper and lower surfaces, the through hole is located above the high-doped N-type ohmic contact layer, the source metal layer is arranged in the through hole, the lower surface of the source metal layer is in contact with the high-doped N-type ohmic contact layer, and the upper surface of the oxide dielectric layer is provided with the gate metal layer.

[0010] The current blocking layer is formed by N ion implantation to compensate the semiconductor and play the role of current blocking.

[0011] The present application increases the dielectric columns on both sides of the drift layer, so that a capacitor is formed by the source, the dielectric column, and the drain in the reverse state, the coupling effect can improve the potential distribution at the time of breakdown, adjust the original breakdown position, improve the breakdown voltage of the MOSFET, and improve the reliability and performance of the device. Therefore, the MOSFET structure of the present application can effectively improve the reverse breakdown voltage of the gallium oxide vertical trench gate MOSFET.

[0012] Preferably, the thickness of the high-doped N-type gallium oxide substrate layer is 2-4 μm, the effective doping concentration of the N-type gallium oxide is 2×10 18 -4×10 18 cm -3 .

[0013] More preferably, the thickness of the highly doped N-type gallium oxide substrate is 2 μm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 cm -3 .

[0014] Preferably, the thickness of the lightly doped N-type gallium oxide drift layer is 5-7 μm, and the effective doping concentration of N-type gallium oxide is 1×10⁻⁶. 16 -2.5×10 16 cm -3 .

[0015] More preferably, the thickness of the lightly doped N-type gallium oxide drift layer is 6 μm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 16 cm -3

[0016] Preferably, the width of the oxide dielectric pillar is 2-3.5 μm and the thickness is 5-7 μm.

[0017] Preferably, the thickness of the oxide dielectric layer is 20-40 nm. More preferably, the thickness of the oxide dielectric layer is 20 nm.

[0018] Preferably, the thickness of the current blocking layer is 0.2-0.4 μm, and the effective nitrogen ion doping concentration is 5 × 10⁻⁶. 18 -7×10 18 cm -3 .

[0019] Preferably, the thickness of the highly doped N-type ohmic contact layer is 100-150 nm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 -4×10 18 cm -3 .

[0020] More preferably, the thickness of the highly doped N-type ohmic contact layer is 100 nm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 cm -3 .

[0021] Preferably, the drain metal layer comprises a titanium layer and a gold layer stacked from bottom to top, the gold layer being connected to the highly doped N-type gallium oxide substrate layer, wherein the thickness of the gold layer is 130-160 nm and the thickness of the titanium layer is 40-70 nm; the source metal layer comprises a gold layer and a titanium layer stacked from bottom to top, wherein the thickness of the titanium layer is 130-160 nm and the thickness of the gold layer is 40-70 nm; the gate metal layer comprises a gold layer and a nickel layer stacked from bottom to top, wherein the thickness of the nickel layer is 130-160 nm and the thickness of the gold layer is 40-70 nm.

[0022] Furthermore, the present invention provides a method for fabricating a gallium oxide vertical trench gate MOSFET with dielectric pillars, comprising the following steps:

[0023] S1. Deposit a low-doped N-type gallium oxide drift layer on the upper surface of a highly doped N-type gallium oxide substrate;

[0024] S2. Apply adhesive to the surface of the low-doped N-type gallium oxide drift layer and etch both sides to form two trenches.

[0025] S3. Deposit oxide dielectric in the trench to fill the trench to obtain oxide dielectric pillars and remove adhesive;

[0026] S4. Continue to deposit a low-doped N-type gallium oxide drift layer on the upper surface of the oxide dielectric pillar and the low-doped N-type gallium oxide drift layer to prepare a current blocking layer;

[0027] S5. Nitrogen ions are injected into the drift layer of the sample and annealed to activate the injected nitrogen ions and form a current blocking layer.

[0028] S6. Silicon ions are implanted into the sample and annealed to activate the implanted silicon ions and form a highly doped N-type ohmic contact layer.

[0029] S7. Apply adhesive to the upper surface of the highly doped N-type ohmic contact layer, and then etch to form a U-shaped trench in the middle of the square of the highly doped N-type ohmic contact layer. The bottom of the trench is etched to the low-doped N-type gallium oxide drift layer.

[0030] S8. An oxide dielectric layer is deposited on the sample after the U-shaped trench is formed;

[0031] S9. On both sides of the U-shaped trench, the upper surface of the oxide dielectric layer is etched and deposited to obtain the source metal layer;

[0032] S10. A drain metal layer is deposited on the lower surface of a highly doped N-type gallium oxide substrate and rapidly annealed.

[0033] S11. In the U-shaped trench, a gate metal layer is deposited on the upper surface of the oxide dielectric layer to obtain the gallium oxide vertical trench gate MOSFET with dielectric pillars.

[0034] Preferably, in step S1, before depositing the low-doped N-type gallium oxide drift layer on the surface of the highly doped N-type gallium oxide substrate, the highly doped N-type gallium oxide substrate needs to be cleaned. The specific steps are: cleaning with acetone, ethanol and deionized water for 10-15 minutes each, and drying in a high-purity (>99%) nitrogen environment.

[0035] Preferably, in step S1, the method for depositing the low-doped N-type gallium oxide drift layer on the surface of the highly doped N-type gallium oxide substrate is one of hydride vapor phase epitaxy (HVPE) or metal-organic chemical vapor deposition (MOCVD).

[0036] Preferably, the adhesive application in steps S2 and S7 includes a first spin coating, a second spin coating, and annealing in sequence; the first spin coating is performed at a speed of 300-800 rpm for 10-15 s; the second spin coating is performed at a speed of 500-1600 rpm for 60-90 s; and the annealing temperature is 100-150℃ for 60-90 s.

[0037] Preferably, in step S3, the method for depositing the oxide dielectric column is plasma-enhanced chemical vapor deposition (PECVD) process, and after deposition at 80-90°C, the sample is then debonded.

[0038] Preferably, in S5 and S6, the ion implantation method includes the following steps: depositing a 120 nm thick silicon dioxide film on the upper surface of the sample as a sacrificial layer for implantation, then implanting N ions or Si ions into the drift layer using an ion implantation device, removing the sacrificial layer after implantation, and finally annealing at 1200°C for 25 minutes to activate the implanted N ions or Si ions.

[0039] Preferably, the deposition method of the source metal layer, drain metal layer and gate metal layer is one of electron beam evaporation, thermal evaporation and magnetron sputtering techniques.

[0040] Compared to existing technologies, the beneficial effects of this invention are as follows: The oxide dielectric pillars of the gallium oxide vertical trench gate MOSFET with dielectric pillars provided by this invention improve the potential distribution during breakdown. In the reverse state, a capacitor is formed between the source, dielectric pillar, and drain, and its coupling effect makes the potential distribution within the dielectric pillar and in the drift region more uniform in the vertical direction. In addition, this invention also adjusts the breakdown position in the case of no dielectric pillar, thereby mitigating the avalanche multiplication effect of the device, improving the breakdown voltage, and enhancing the reliability and performance of the device. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of the gallium oxide vertical trench gate MOSFET with dielectric pillars in Example 1;

[0042] Figure 2 This is a schematic diagram of the structure of a conventional gallium oxide vertical trench gate MOSFET, as shown in Comparative Example 1.

[0043] Figure 3A comparison diagram of the potential distribution during MOSFET breakdown in Example 1 and Comparative Example 1;

[0044] Figure 4 The simulation comparison graphs show the reverse breakdown voltage of the MOSFETs in Examples 1-6 and Comparative Example 1.

[0045] Figures 1-2 In the middle: 1. Drain metal layer; 2. Highly doped N-type gallium oxide substrate layer; 3. Low-doped N-type gallium oxide drift layer; 4. Oxide dielectric pillar; 5. Current blocking layer; 6. Highly doped N-type ohmic contact layer; 7. Source metal layer; 8. Oxide dielectric layer; 9. Gate metal layer. Detailed Implementation

[0046] To better illustrate the purpose, technical solution, and advantages of this invention, the invention will be further described below with reference to the accompanying drawings and specific embodiments. Unless otherwise specified, the experimental methods used in the embodiments are conventional methods, and the materials and reagents used are commercially available unless otherwise specified.

[0047] Example 1

[0048] like Figure 1 As shown, a gallium oxide vertical trench gate MOSFET with dielectric pillars includes: a drain metal layer 1, a highly doped N-type gallium oxide substrate layer 2, a lightly doped N-type gallium oxide drift layer 3, an oxide dielectric pillar 4, a current blocking layer 5, a highly doped N-type ohmic contact layer 6, a source metal layer 7, an oxide dielectric layer 8, and a gate metal layer 9.

[0049] The drain metal layer 1, the highly doped N-type gallium oxide substrate layer 2, and the lightly doped N-type gallium oxide drift layer 3 are arranged sequentially. The upper surface of the drain metal layer 1 is in contact with the lower surface of the highly doped N-type gallium oxide substrate layer 2. Oxide dielectric pillars 4 are respectively arranged on both sides of the lightly doped N-type gallium oxide drift layer 3. The lower surface of the oxide dielectric pillars 4 is in contact with the highly doped N-type gallium oxide substrate layer 2.

[0050] The current blocking layer 5 and the highly doped N-type ohmic contact layer 6 are arranged sequentially, and the lower surface of the current blocking layer 5 is in contact with the low-doped N-type gallium oxide drift layer 3 and the oxide dielectric pillar 4.

[0051] The vertical trench gate MOSFET is provided with a U-shaped trench, which is recessed from the upper surface of the highly doped N-type ohmic contact layer 6 to the low-doped N-type gallium oxide drift layer 3.

[0052] The oxide dielectric layer 8 covers the inner wall of the U-shaped trench and the upper surface of the highly doped N-type ohmic contact layer 6. The oxide dielectric layer 8 has a through hole that penetrates the upper and lower surfaces of 8. The through hole is located above 6. A source metal layer 7 is disposed inside the through hole. The lower surface of the source metal layer 7 is in contact with the highly doped N-type ohmic contact layer 6. A gate metal layer 9 is disposed on the upper surface of the oxide dielectric layer 8.

[0053] The drain metal layer 1 comprises a stacked gold layer and a titanium layer, wherein the gold layer is connected to the highly doped N-type gallium oxide substrate layer; wherein the thickness of the gold layer is 150 nm; and the thickness of the titanium layer is 50 nm.

[0054] The thickness of the highly doped N-type gallium oxide substrate 2 is 2 μm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 cm -3 .

[0055] The thickness of the low-doped N-type gallium oxide drift layer 3 is 6 μm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 16 cm -3 The lower surface of the low-doped N-type gallium oxide drift layer 3 is in contact with the high-doped N-type gallium oxide substrate layer 2.

[0056] The oxide dielectric pillar 4 is made of silicon dioxide and consists of two identical regions with a width of 3μm and a thickness of 6μm. They are located on both sides of the low-doped N-type gallium oxide drift layer 3, and the lower surface of the oxide dielectric pillar 4 is in contact with the high-doped N-type gallium oxide substrate layer 2.

[0057] The current blocking layer 5 has a thickness of 0.3 μm and an effective nitrogen ion doping concentration of 6 × 10⁻⁶. 18 cm -3 ,

[0058] The highly doped N-type ohmic contact layer 6 has a thickness of 100 nm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 cm -3 .

[0059] The source metal layer 7 comprises a stacked titanium layer and a gold layer; the titanium layer has a thickness of 150 nm, and the gold layer has a thickness of 50 nm.

[0060] The oxide dielectric layer 8 is made of aluminum oxide, located around the U-shaped trench, and has a thickness of 20 nm.

[0061] The gate metal layer 9 comprises a stacked nickel layer and a gold layer; the nickel layer has a thickness of 150 nm and the gold layer has a thickness of 50 nm.

[0062] A method for fabricating a gallium oxide vertical trench gate MOSFET with dielectric pillars includes the following steps:

[0063] S1. The highly doped N-type gallium oxide substrate 2 is washed sequentially in acetone, ethanol and deionized water for 10 min each, and the washed sample is dried under pure N2 conditions.

[0064] S2. A low-doped N-type gallium oxide drift layer 3 is deposited on the surface of a highly doped N-type gallium oxide substrate 2 using hydride vapor phase epitaxy (HVPE).

[0065] S3. Apply photoresist to the surface of the low-doped N-type gallium oxide drift layer 3, and use BCl gas to etch the layer using photolithography and etching processes to prepare two trenches with the same thickness as the low-doped N-type gallium oxide drift layer 3 and a width of 3 μm on the surface of the epitaxial layer.

[0066] 3a) The coating process in step 3 includes placing the sample in a spin coater, first spin coating at a speed of 500 rpm for 15 seconds; then spin coating at a speed of 1000 rpm for 80 seconds; and finally annealing at 150°C for 80 seconds.

[0067] 3b) After the annealed sample is exposed in a photolithography machine for 1.5s, it is placed in a developing solution for development to expose the low-doped N-type gallium oxide drift layer 3 of the part to be etched.

[0068] 3c) Place the developed sample in deionized water to remove residual developer from the sample surface and dry it in an N2 environment;

[0069] 3d) The dried sample was placed in the reaction chamber of an inductively coupled plasma (ICP) etching instrument and etched using BCl gas to obtain two trenches with a thickness of 6 μm and a width of 3 μm on the upper surface of the epitaxial layer.

[0070] S4. Using plasma-enhanced chemical vapor deposition (PECVD) to deposit oxide dielectric pillars 4 in the two trenches of the low-doped N-type gallium oxide drift layer 3, after deposition at 80-90℃, the sample is then stripped of the resist.

[0071] S5. Using hydride vapor phase epitaxy (HVPE), a drift layer is further deposited on the upper surface of the low-doped N-type gallium oxide drift layer 3 and the oxide dielectric pillar 4 to prepare the current blocking layer 5.

[0072] S6. A 120 nm thick silicon dioxide film is deposited on the surface of the drift layer used to prepare the current blocking layer 5 as a sacrificial layer for implantation. Then, nitrogen ions are implanted into the drift layer using an ion implantation device. After implantation, the sacrificial layer is removed, and finally, the implanted nitrogen ions are activated by annealing at 1200 °C for 25 minutes.

[0073] S7. A 120nm thick silicon dioxide film is deposited on the upper surface of the current blocking layer 5 as a sacrificial layer for implantation. Then, silicon ions are implanted into the sample using an ion implantation device. After implantation, the sacrificial layer is removed, and finally, the silicon ions are activated using a rapid annealing device.

[0074] S8. Apply photoresist to the surface of the highly doped N-type ohmic contact layer 6, and use BCl gas to etch the layer using photolithography and etching processes to form a 77μm wide U-shaped trench in the middle of the highly doped N-type ohmic contact layer. The bottom of the trench is etched down to the low-doped N-type gallium oxide drift layer 3 and the photoresist is removed.

[0075] 8a) The coating process in step 8 includes placing the sample in a spin coater, first spin coating at a speed of 500 rpm for 15 seconds; then spin coating at a speed of 1000 rpm for 80 seconds; and finally annealing at 150°C for 80 seconds.

[0076] 8b) After the annealed sample is exposed in a photolithography machine for 1.5s, it is placed in a developing solution for development to expose the highly doped N-type ohmic contact layer 6 of the part to be etched.

[0077] 8c) Place the developed sample in deionized water to remove residual developer on the sample surface and dry it in an N2 environment;

[0078] 8d) The dried sample was placed in the reaction chamber of an inductively coupled plasma (ICP) etching instrument and etched using BCl gas to form a 77 μm wide U-shaped trench in the middle of the highly doped N-type ohmic contact layer 6. The bottom of the trench was etched down to the low-doped N-type gallium oxide drift layer 3 and the resist was removed.

[0079] S9. An oxide medium layer 8 is deposited in the U-shaped trench using a plasma-enhanced chemical vapor deposition (PECVD) process, and the deposition is completed at 80-90℃.

[0080] S10. Apply a photoresist to the surface of the oxide dielectric layer 8, and use photolithography and etching processes, using BCl gas to etch the source region above the highly doped N-type ohmic contact layer 6.

[0081] 10a) The coating process in step 10 includes placing the sample in a spin coater, first spin coating at a speed of 500 rpm for 15 seconds; then spin coating at a speed of 1000 rpm for 80 seconds; and finally annealing at 150°C for 80 seconds.

[0082] 10b) After the annealed sample is exposed in a photolithography machine for 1.5s, it is placed in a developing solution for development to expose the highly doped N-type ohmic contact layer 6 of the part to be etched.

[0083] 10c) Place the developed sample in deionized water to remove residual developer on the sample surface and dry it in an N2 environment;

[0084] 10d) The dried sample was placed in the reaction chamber of an inductively coupled plasma (ICP) etching instrument and etched using BCl gas to etch the source region above the highly doped N-type ohmic contact layer 6.

[0085] S11. A source metal layer 7 is obtained by depositing and rapidly annealing in the source region using an electron beam evaporation process. A drain metal layer 1 is obtained by depositing and rapidly annealing on the lower surface of a highly doped N-type gallium oxide substrate layer 2. A gate metal layer 9 is obtained by depositing and rapidly annealing on the upper surface of an oxide dielectric layer 8 in the middle U-shaped trench.

[0086] Example 2

[0087] The only difference between Example 2 and Example 1 is that the effective doping concentration of the low-doped N-type gallium oxide drift layer 3 in Example 2 is 1×10⁻⁶. 16 cm -3 The oxide dielectric pillar 4 has a width of 2.5 μm; the current blocking layer 5 has a thickness of 0.25 μm and an effective nitrogen ion doping concentration of 5.6 × 10⁻⁶. 18 cm -3 .

[0088] Example 3

[0089] The only difference between Example 3 and Example 1 is that the effective doping concentration of the low-doped N-type gallium oxide drift layer 3 in Example 3 is 2.5 × 10⁻⁶. 16 cm -3 The oxide dielectric pillar 4 has a width of 3.5 μm; the current blocking layer 5 has a thickness of 0.35 μm and an effective nitrogen ion doping concentration of 6.5 × 10⁻⁶. 18 cm -3 .

[0090] Example 4

[0091] The only difference between Example 4 and Example 1 is that the effective doping concentration of the low-doped N-type gallium oxide drift layer 3 in Example 4 is 3 × 10⁻⁶. 16 cm -3 .

[0092] Example 5

[0093] The only difference between Example 5 and Example 1 is that the width of the oxide dielectric pillar 4 in Example 5 is 1 μm.

[0094] Example 6

[0095] The only difference between Example 6 and Example 1 is that the thickness of the current blocking layer 5 in Example 6 is 0.1 μm.

[0096] Comparative Example 1

[0097] The only difference between Comparative Example 1 and Example 1 is that: Figure 2 As shown, the low-doped N-type gallium oxide drift layer 3 in Comparative Example 1 does not contain oxide dielectric pillars 4 on either side.

[0098] Performance testing

[0099] Using Sentaurus software, the device size and density parameters of the MOSFETs in Examples 1-3 and the comparative example were set, and the reverse breakdown voltage simulation test was performed. The data are shown in Table 1 and 2. Figure 4 .

[0100] Table 1 shows the reverse breakdown voltages of the MOSFETs in Examples 1-6 and Comparative Example 1.

[0101] Group Reverse breakdown voltage / V Example 1 865.2 Example 2 801.3 Example 3 822.4 Example 4 613.0 Example 5 575.3 Example 6 596.6 Comparative Example 1 430.7

[0102] From Table 1 and Figure 4 It can be seen that the reverse breakdown voltage of Examples 1-3 all reached over 700V. Example 1 showed a 100.9% improvement compared to Comparative Example 1, Example 2 showed an 86.0% improvement compared to Comparative Example 1, and Example 3 showed a 90.9% improvement compared to Comparative Example 1; Furthermore, from... Figure 3 The comparison shows that the potential distribution in the vertical direction of the MOSFET with dielectric pillars is indeed more uniform than that of the conventional MOSFET without dielectric pillars. Therefore, the MOSFET structure of this invention can effectively mitigate the avalanche multiplication effect, improve the breakdown voltage, and enhance the reliability and performance of the device.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A gallium oxide vertical trench gate MOSFET with dielectric pillars, characterized in that, It includes a drain metal layer, a highly doped N-type gallium oxide substrate layer, a lightly doped N-type gallium oxide drift layer, an oxide dielectric pillar, a current blocking layer, a highly doped N-type ohmic contact layer, a source metal layer, an oxide dielectric layer, and a gate metal layer. The drain metal layer, the highly doped N-type gallium oxide substrate layer, and the lightly doped N-type gallium oxide drift layer are arranged sequentially. The upper surface of the drain metal layer is in contact with the lower surface of the highly doped N-type gallium oxide substrate layer. Oxide dielectric pillars are respectively arranged on both sides of the lightly doped N-type gallium oxide drift layer. The lower surface of the oxide dielectric pillars is in contact with the highly doped N-type gallium oxide substrate layer. The current blocking layer and the highly doped N-type ohmic contact layer are arranged sequentially, and the lower surface of the current blocking layer is in contact with the low-doped N-type gallium oxide drift layer and the oxide dielectric pillar; The vertical trench gate MOSFET is provided with a U-shaped trench, which is recessed from the upper surface of the highly doped N-type ohmic contact layer to the low-doped N-type gallium oxide drift layer. The oxide dielectric layer covers the inner wall of the U-shaped trench and the upper surface of the highly doped N-type ohmic contact layer. The oxide dielectric layer has a through-hole that penetrates both the upper and lower surfaces. The through-hole is located above the highly doped N-type ohmic contact layer. A source metal layer is disposed inside the through-hole. The lower surface of the source metal layer is in contact with the highly doped N-type ohmic contact layer. A gate metal layer is disposed on the upper surface of the oxide dielectric layer. The thickness of the highly doped N-type gallium oxide substrate is 2-4 µm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 -4×10 18 cm -3 ; The thickness of the lightly doped N-type gallium oxide drift layer is 5-7 µm, and the effective doping concentration of N-type gallium oxide is 1 × 10⁻⁶. 16 -2.5×10 16 cm -3 ; The oxide dielectric pillar has a width of 2-3.5µm and a thickness of 5-7µm; The thickness of the oxide dielectric layer is 20-40 nm; The thickness of the current blocking layer is 0.2-0.4 µm, and the effective nitrogen ion doping concentration is 5 × 10⁻⁶. 18 -7×10 18 cm -3 .

2. The gallium oxide vertical trench gate MOSFET with dielectric pillars as described in claim 1, characterized in that, The thickness of the highly doped N-type ohmic contact layer is 100-150 nm, and the effective doping concentration of N-type gallium oxide is 2 × 10⁻⁶. 18 -4×10 18 cm -3 .

3. The gallium oxide vertical trench gate MOSFET with dielectric pillars as described in claim 1, characterized in that, The drain metal layer comprises a titanium layer and a gold layer stacked from bottom to top, the gold layer being connected to the highly doped N-type gallium oxide substrate layer, wherein the thickness of the gold layer is 130-160 nm and the thickness of the titanium layer is 40-70 nm; the source metal layer comprises a gold layer and a titanium layer stacked from bottom to top, wherein the thickness of the titanium layer is 130-160 nm and the thickness of the gold layer is 40-70 nm; the gate metal layer comprises a gold layer and a nickel layer stacked from bottom to top, wherein the thickness of the nickel layer is 130-160 nm and the thickness of the gold layer is 40-70 nm.

4. The gallium oxide vertical trench gate MOSFET with dielectric pillars as described in claim 1, characterized in that, The thickness of the oxide dielectric layer is 20-40 nm.

5. The method for fabricating a gallium oxide vertical trench gate MOSFET with dielectric pillars as described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Deposit a low-doped N-type gallium oxide drift layer on the upper surface of a highly doped N-type gallium oxide substrate; S2. Apply adhesive to the surface of the low-doped N-type gallium oxide drift layer and etch both sides to form two trenches. S3. Deposit oxide dielectric in the trench to fill the trench to obtain oxide dielectric pillars and remove adhesive; S4. Continue to deposit a low-doped N-type gallium oxide drift layer on the upper surface of the oxide dielectric pillar and the low-doped N-type gallium oxide drift layer to prepare a current blocking layer. S5. Nitrogen ions are injected into the drift layer of the sample and annealed to activate the injected nitrogen ions and form a current blocking layer. S6. Silicon ions are implanted into the sample and annealed to activate the implanted silicon ions and form a highly doped N-type ohmic contact layer. S7. Apply adhesive to the upper surface of the highly doped N-type ohmic contact layer, and then etch to form a U-shaped trench in the middle of the square of the highly doped N-type ohmic contact layer. The bottom of the trench is etched to the low-doped N-type gallium oxide drift layer. S8. An oxide dielectric layer is deposited on the sample after the U-shaped trench is formed; S9. On both sides of the U-shaped trench, the upper surface of the oxide dielectric layer is etched and deposited to obtain the source metal layer; S10. A drain metal layer is deposited on the lower surface of a highly doped N-type gallium oxide substrate and rapidly annealed. S11. In the U-shaped trench, a gate metal layer is deposited on the upper surface of the oxide dielectric layer to obtain the gallium oxide vertical trench gate MOSFET with dielectric pillars.

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