Power semiconductor device and its control method

Abstract

The present disclosure relates to a power semiconductor device and a control method thereof. The power semiconductor device includes: a chip unit and an auxiliary packaging structure. The chip unit includes a turn-on optimization region and a turn-off optimization region. The auxiliary packaging structure includes an auxiliary turn-off component connected at least to the turn-off optimization region. Wherein, the chip unit is configured to: provide a first current path in the turn-on optimization region, provide a second current path in the turn-off optimization region in the turn-on mode, and transfer the current in the turn-on optimization region to the turn-off optimization region and the auxiliary turn-off component in the turn-off mode. The auxiliary turn-off component is configured to: increase the turn-off current of the turn-off optimization region to assist the turn-off of the turn-off optimization region. The present disclosure can simultaneously take into account the effective improvement of the current conduction ability and the current turn-off ability on a single power semiconductor device to further improve the electrical performance of the power semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and particularly to a power semiconductor device and a control method thereof. Background Art

[0002] As a basic component for power conversion in a power electronic converter, the current conduction ability of a power semiconductor device can determine the upper limit of the capacity of the power converter, and the current turn-off ability of the power semiconductor device can determine the fault resistance performance of the power converter. Therefore, the stronger the current conduction ability and the current turn-off ability of the power semiconductor device, the better.

[0003] However, reducing the carrier lifetime of a power semiconductor device can improve the current turn-off ability of the power semiconductor device, but will reduce the current conduction ability of the power semiconductor device; conversely, increasing the carrier lifetime of the power semiconductor device can improve the current conduction ability of the power semiconductor device, but will reduce the current turn-off ability of the power semiconductor device. Therefore, the current conduction ability and the current turn-off ability can only be optimized for a single target according to its application scenario on a single power semiconductor device. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a power semiconductor device and a control method thereof, which can simultaneously take into account the effective improvement of the current conduction ability and the current turn-off ability on a single power semiconductor device, so as to further improve the electrical performance of the power semiconductor device.

[0005] To achieve the above object, in a first aspect, some embodiments of the present disclosure provide a power semiconductor device, including: a chip unit and an auxiliary packaging structure. The chip unit includes a conduction optimization region and a turn-off optimization region. The auxiliary packaging structure includes at least an auxiliary turn-off component connected to the turn-off optimization region. Wherein, the chip unit is configured to: provide a first current path in the conduction optimization region and a second current path in the turn-off optimization region in the on mode, and transfer the current in the conduction optimization region to the turn-off optimization region and the auxiliary turn-off component in the off mode. The auxiliary turn-off component is configured to: increase the turn-off current of the turn-off optimization region to assist the turn-off optimization region to turn off.

[0006] In some embodiments of the present disclosure, the chip unit includes: an inner active region, an inner gate, an outer active region, and an outer gate; wherein, the implementation manners of the inner active region, the inner gate, the outer active region, and the outer gate include any one of the following:

[0007] Embodiment 1, the inner active region, the inner gate, the outer active region, and the outer gate are arranged in a ring shape from the inside to the outside along the radial direction of the chip unit.

[0008] Embodiment 2: The inner gate, the inner active region, the outer active region, and the outer gate are arranged in a ring from the inside to the outside along the radial direction of the chip unit.

[0009] Embodiment 3: The inner active region, the inner gate, the outer gate, and the outer active region are arranged in a ring from the inside to the outside along the radial direction of the chip unit.

[0010] Embodiment 4: The inner gate, the inner active region, the outer gate, and the outer active region are arranged in a ring from the inside to the outside along the radial direction of the chip unit.

[0011] Optionally, the conduction optimization region includes the inner gate and the inner active region; the turn-off optimization region includes the outer gate and the outer active region.

[0012] In some embodiments of the present disclosure, the first ends of the inner active region and the outer active region are isolated, and the second ends of the inner active region and the outer active region are connected to form a first current port.

[0013] In some embodiments of the present disclosure, the auxiliary turn-off component includes a gate-cathode enhanced turn-off component. The embodiments of the gate-cathode enhanced turn-off component include any one of the following:

[0014] Embodiment 1: The gate-cathode enhanced turn-off component includes a gate FET group and a cathode FET group; wherein, the first end of the gate FET group is connected to the outer gate; the first end of the cathode FET group is connected to the third end of the outer active region; the second ends of the gate FET group, the cathode FET group, and the third end of the inner active region are connected to form a second current port.

[0015] Embodiment 2: The gate-cathode enhanced turn-off component includes a gate FET group, a cathode FET group, and an auxiliary connection component; wherein, the first end of the gate FET group is connected to the outer gate, and the first end of the cathode FET group is connected to the third end of the outer active region; the second ends of the gate FET group, the cathode FET group, and the third end of the inner active region are connected to form a second current port; the auxiliary connection component is connected to the inner gate.

[0016] Embodiment 3: The gate-cathode enhanced turn-off component includes a gate FET group and a cathode diode group; wherein, the first end of the gate FET group is connected to the outer gate; the first end of the cathode diode group is connected to the third end of the outer active region; the second ends of the gate FET group, the cathode diode group, and the third end of the inner active region are connected to form a second current port.

[0017] Embodiment 4. The gate-cathode enhanced turn-off component includes a gate field-effect transistor group, a gate capacitor group, and a cathode diode group. Among them, the gate field-effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field-effect transistor group and the gate capacitor group is connected to the external gate. The first end of the cathode diode group is connected to the third end of the external active region. The second end of the series branch of the gate field-effect transistor group and the gate capacitor group, the second end of the cathode diode group, and the third end of the internal active region are connected to form a second current port.

[0018] Embodiment 5. The gate-cathode enhanced turn-off component includes a gate field-effect transistor group, a gate capacitor group, a cathode diode group, and an auxiliary connection component. Among them, the gate field-effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field-effect transistor group and the gate capacitor group is connected to the external gate. The first end of the cathode diode group is connected to the third end of the external active region. The second end of the series branch of the gate field-effect transistor group and the gate capacitor group, the second end of the cathode diode group, and the third end of the internal active region are connected to form a second current port. The auxiliary connection component is connected to the internal gate.

[0019] In some other embodiments of the present disclosure, the auxiliary turn-off component includes a gate enhanced turn-off component. The embodiments of the gate enhanced turn-off component include any one of the following:

[0020] Embodiment 1. The gate enhanced turn-off component includes a gate field-effect transistor group. Among them, the first end of the gate field-effect transistor group is connected to the external gate. The second end of the gate field-effect transistor group, the third end of the external active region, and the third end of the internal active region are connected to form a second current port.

[0021] Embodiment 2. The gate enhanced turn-off component includes a gate field-effect transistor group, a first auxiliary connection component, and / or a second auxiliary connection component. Among them, the first end of the gate field-effect transistor group is connected to the external gate. The second end of the gate field-effect transistor group, the third end of the external active region, and the third end of the internal active region are connected to form a second current port. The first auxiliary connection component is used to connect the internal gate. The second auxiliary connection component is used to connect the external active region.

[0022] Embodiment 3. The gate enhanced turn-off component includes a gate field effect transistor group and a gate capacitor group. Among them, the gate field effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field effect transistor group and the gate capacitor group is connected to the external gate. The second end of the series branch of the gate field effect transistor group and the gate capacitor group, the third end of the external active region, and the third end of the internal active region are connected to form a second current port.

[0023] Embodiment 4. The gate enhanced turn-off component includes a gate field effect transistor group, a gate capacitor group, and a first auxiliary connection component and / or a second auxiliary connection component. Among them, the gate field effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field effect transistor group and the gate capacitor group is connected to the external gate. The second end of the series branch of the gate field effect transistor group and the gate capacitor group, the third end of the external active region, and the third end of the internal active region are connected to form a second current port. The first auxiliary connection component is used to connect the internal gate. The second auxiliary connection component is used to connect the external active region.

[0024] In some other embodiments of the present disclosure, the auxiliary turn-off component includes a gate-gate cathode enhanced turn-off component. The embodiments of the gate-gate cathode enhanced turn-off component include any one of the following:

[0025] Embodiment 1. The gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode field effect transistor group, and an internal gate field effect transistor group. Among them, the first end of the external gate field effect transistor group is connected to the external gate. The first end of the external cathode field effect transistor group is connected to the third end of the external active region. The first end of the internal gate field effect transistor group is connected to the internal gate. The second ends of the external gate field effect transistor group, the external cathode field effect transistor group, the internal gate field effect transistor group, and the third end of the internal active region are connected to form a second current port.

[0026] Embodiment 2. The gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode diode group, and an internal gate field effect transistor group. Among them, the first end of the external gate field effect transistor group is connected to the external gate. The first end of the external cathode diode group is connected to the third end of the external active region. The first end of the internal gate field effect transistor group is connected to the internal gate. The second ends of the external gate field effect transistor group, the external cathode diode group, the internal gate field effect transistor group, and the third end of the internal active region are connected to form a second current port.

[0027] Embodiment 3. The gate-gate cathode enhanced turn-off component includes an outer gate field effect transistor group, an outer cathode field effect transistor group, an inner gate field effect transistor group, and an inner gate capacitor group. Among them, the first end of the outer gate field effect transistor group is connected to the outer gate; the first end of the outer cathode field effect transistor group is connected to the third end of the outer active region; the first end of the inner gate field effect transistor group is connected to the inner gate; the second end of the inner gate field effect transistor group is connected to the first end of the inner gate capacitor group; the second end of the outer gate field effect transistor group, the second end of the outer cathode field effect transistor group, the second end of the inner gate capacitor group, and the third end of the inner active region are connected and form a second current port.

[0028] Embodiment 4. The gate-gate cathode enhanced turn-off component includes: an outer gate field effect transistor group, an outer cathode diode group, an inner gate field effect transistor group, and an inner gate capacitor group. Among them, the first end of the outer gate field effect transistor group is connected to the outer gate; the first end of the outer cathode diode group is connected to the third end of the outer active region; the first end of the inner gate field effect transistor group is connected to the inner gate; the second end of the inner gate field effect transistor group is connected to the first end of the inner gate capacitor group; the second end of the outer gate field effect transistor group, the second end of the outer cathode diode group, the second end of the inner gate capacitor group, and the third end of the inner active region are connected and form a second current port.

[0029] Embodiment 5. The gate-gate cathode enhanced turn-off component includes an outer gate field effect transistor group, an outer cathode diode group, an outer gate capacitor group, and an inner gate field effect transistor group. Among them, the first end of the outer gate field effect transistor group is connected to the outer gate, and the second end of the outer gate field effect transistor group is connected to the first end of the outer gate capacitor group; the first end of the outer cathode diode group is connected to the third end of the outer active region; the first end of the inner gate field effect transistor group is connected to the inner gate; the second end of the outer gate capacitor group, the second end of the outer cathode diode group, the second end of the inner gate field effect transistor group, and the third end of the inner active region are connected and form a second current port.

[0030] Embodiment 6. The gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode diode group, an external gate capacitor group, an internal gate field effect transistor group, and an internal gate capacitor group. Wherein, the first end of the external gate field effect transistor group is connected to the external gate, and the second end of the external gate field effect transistor group is connected to the first end of the external gate capacitor group; the first end of the external cathode diode group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate, and the second end of the internal gate field effect transistor group is connected to the first end of the internal gate capacitor group; the second ends of the external gate capacitor group, the external cathode diode group, the internal gate capacitor group, and the internal gate capacitor group and the third end of the internal active region are connected to form a second current port.

[0031] In some other embodiments of the present disclosure, the auxiliary turn-off component includes a gate-gate enhanced turn-off component; the gate-gate enhanced turn-off component includes an external gate auxiliary turn-off component, an internal gate auxiliary turn-off component, and an auxiliary connection component disposed between the external gate auxiliary turn-off component and the internal gate auxiliary turn-off component; the auxiliary connection component is used to connect the external active region.

[0032] In some embodiments of the present disclosure, the auxiliary packaging structure further includes a first vacant area for exposing at least a part of the conduction optimization area; the first vacant area is used to accommodate the cathode lead electrode of the conduction optimization area.

[0033] In a second aspect, some embodiments of the present disclosure further provide a control method for a power semiconductor device, which is applied to the power semiconductor device described in the foregoing some embodiments. The working modes of the power semiconductor device include a turn-on mode and a turn-off mode. The control method includes the following steps.

[0034] In the turn-on mode, a first control signal is applied to the conduction optimization area, a second control signal is applied to the turn-off optimization area, and a third control signal is applied to the auxiliary turn-off component, so as to provide a first current path in the conduction optimization area and a second current path in the turn-off optimization area.

[0035] In the turn-off mode, a fourth control signal is applied to the conduction optimization area to transfer the current in the conduction optimization area to the turn-off optimization area and the auxiliary turn-off component; a fifth control signal is applied to the auxiliary turn-off component to increase the turn-off current of the turn-off optimization area to assist the turn-off of the turn-off optimization area.

[0036] In some embodiments of the present disclosure, the chip unit includes: an inner active region, an inner gate, an outer active region, and an outer gate; the conduction optimization region includes the inner gate and the inner active region; the turn-off optimization region includes the outer gate and the outer active region; wherein, the first control signal and the fourth control signal are respectively control signals for the inner gate; the second control signal is a control signal for the outer gate; the third control signal and the fifth control signal are respectively gate control signals in the auxiliary turn-off component.

[0037] The embodiments of the present disclosure may / at least have the following advantages:

[0038] In the embodiments of the present disclosure, a conduction optimization region and a turn-off optimization region are integrated within the same chip unit, and at least an auxiliary turn-off component connected to the turn-off optimization region is provided in the auxiliary packaging structure, so that the chip unit can provide a first current path in the conduction optimization region and a second current path in the turn-off optimization region in the turn-on mode, and can transfer the current in the conduction optimization region to the turn-off optimization region and the auxiliary turn-off component in the turn-off mode, and can increase the turn-off current of the turn-off optimization region through the auxiliary turn-off component to assist the turn-off of the turn-off optimization region. Thus, through the circuit structure design of the chip unit and the auxiliary turn-off component in the power semiconductor device, the embodiments of the present disclosure can simultaneously take into account the effective improvement of the current conduction ability and the current turn-off ability on a single power semiconductor device, so as to further improve the electrical performance of the power semiconductor device.

[0039] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1 It is a schematic structural diagram of a chip unit provided in some embodiments;

[0042] Figure 2 It is a schematic structural diagram of another chip unit provided in some embodiments;

[0043] Figure 3 It is a schematic structural diagram of yet another chip unit provided in some embodiments;

[0044] Figure 4 Schematic diagram of another chip unit structure provided in some embodiments;

[0045] Figure 5 Schematic diagram of a structure of an auxiliary turn-off component provided in some embodiments;

[0046] Figure 6 Schematic diagram of another structure of an auxiliary turn-off component provided in some embodiments;

[0047] Figure 7 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0048] Figure 8 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0049] Figure 9 Schematic diagram of an equivalent circuit of a power semiconductor device provided in some embodiments;

[0050] Figure 10 For Figure 9 A control timing diagram of the shown power semiconductor device;

[0051] Figure 11 Schematic diagram of another equivalent circuit of a power semiconductor device provided in some embodiments;

[0052] Figure 12 For Figure 11 A control timing diagram of the shown power semiconductor device;

[0053] Figure 13 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0054] Figure 14 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0055] Figure 15 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0056] Figure 16 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0057] Figure 17 Schematic diagram of yet another equivalent circuit of a power semiconductor device provided in some embodiments;

[0058] Figure 18 Schematic diagram of yet another structure of an auxiliary turn-off component provided in some embodiments;

[0059] Figure 19 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0060] Figure 20 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0061] Figure 21 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0062] Figure 22 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0063] Figure 23 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0064] Figure 24 Schematic diagram of the equivalent circuit of yet another power semiconductor device provided in some embodiments;

[0065] Figure 25 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0066] Figure 26 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0067] Figure 27 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0068] Figure 28 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0069] Figure 29 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0070] Figure 30 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0071] Figure 31 Schematic diagram of the equivalent circuit of yet another power semiconductor device provided in some embodiments;

[0072] Figure 32 Schematic diagram of yet another auxiliary turn-off component provided in some embodiments;

[0073] Figure 33 Schematic diagram of the equivalent circuit of yet another power semiconductor device provided in some embodiments;

[0074] Figure 34 ForFigure 33 A control timing diagram of the shown power semiconductor device;

[0075] Figure 35 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0076] Figure 36 For Figure 35 A control timing diagram of the shown power semiconductor device;

[0077] Figure 37 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0078] Figure 38 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0079] Figure 39 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0080] Figure 40 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0081] Figure 41 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0082] Figure 42 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0083] Figure 43 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0084] Figure 44 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0085] Figure 45 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0086] Figure 46 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0087] Figure 47 A schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0088] Figure 48 A schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0089] Figure 49 Schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments;

[0090] Figure 50 Schematic diagram of the structure of another auxiliary turn-off component provided in some embodiments;

[0091] Figure 51 Schematic diagram of an equivalent circuit of another power semiconductor device provided in some embodiments. Detailed implementation manners

[0092] For ease of understanding the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is thorough and comprehensive.

[0093] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0094] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be denoted as the second element, component, region, layer, or part.

[0095] It should be understood that when an element is considered to be "connected" to another element, it may be directly connected to the other element or connected to the other element through an intermediate element. In addition, in the following embodiments, "connection", if there is a transmission of electrical signals or data between the connected objects, should be understood as "electrical connection", "communication connection", etc.

[0096] It should be understood that the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprise / include" or "have", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the related listed items.

[0097] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0098] Embodiments of the present disclosure provide a power semiconductor device and a control method thereof, which can effectively improve both the current conduction ability and the current turn-off ability on a single power semiconductor device to further improve the electrical performance of the power semiconductor device.

[0099] In some embodiments of the present disclosure, please refer to Figures 1 to 8 Understand that the power semiconductor device includes: a chip unit 1 and an auxiliary packaging structure. The chip unit 1 includes a conduction optimization region and a turn-off optimization region. The auxiliary packaging structure includes an auxiliary turn-off component 2 connected at least to the turn-off optimization region. Among them, the chip unit is configured to: provide a first current path in the conduction optimization region in the on mode, provide a second current path in the turn-off optimization region, and transfer the current in the conduction optimization region to the turn-off optimization region and the auxiliary turn-off component in the off mode. The auxiliary turn-off component is configured to: increase the turn-off current of the turn-off optimization region to assist the turn-off optimization region in turning off.

[0100] Exemplarily, the chip unit 1 is a dual-chip power semiconductor chip, which can integrate two different chips at the same time to optimize the current conduction ability through one of the chips (i.e., constitute the conduction optimization region), and optimize the current turn-off ability through the other of the chips (i.e., constitute the turn-off optimization region); that is, one of the chips focuses on the optimization of conduction loss, which is beneficial to reducing the thermal resistance and resistance of the corresponding packaging structure to achieve a comprehensive improvement in the current conduction ability of the device; the other of the chips focuses on the optimization of turn-off loss and turn-off ability to achieve a comprehensive improvement in the current turn-off ability of the device. In addition, the current paths of the two chips are in parallel.

[0101] Exemplarily, the chip unit 1 may set the inner region R1 as the conduction optimization region and the outer region R2 as the turn-off optimization region; or, the chip unit 1 may also set the outer region R2 as the conduction optimization region and the inner region R1 as the turn-off optimization region.

[0102] Here, the inner region R1 is the central region of the chip unit 1, and the outer region R2 can surround the circumferential side of the inner region R1.

[0103] In some examples, the inner region R1 of the chip unit 1 is an on-optimization region, and the outer region R2 is an off-optimization region. In this way, it is convenient to arrange the off-enhancing components in the auxiliary packaging structure in terms of physical structure to increase the space utilization rate.

[0104] For the convenience of description, in the following embodiments of the present disclosure, the inner region R1 of the chip unit 1 is taken as the on-optimization region, and the outer region R2 is taken as the off-optimization region as an example for description.

[0105] In some embodiments, please refer to Figures 1 to 4 , the chip unit 1 includes: an outer gate 11, an outer active region 12, an inner gate 13, and an inner active region 14. And, the implementation manners of the outer gate 11, the outer active region 12, the inner gate 13, and the inner active region 14 can adopt any one of the following:

[0106] Embodiment 1, as shown in Figure 1 , the inner active region 14, the inner gate 13, the outer active region 12, and the outer gate 11 are arranged in a ring shape from the inside to the outside along the radial direction of the chip unit 1.

[0107] Embodiment 2, as shown in Figure 2 , the inner gate 13, the inner active region 14,, the outer active region 12, and the outer gate 11 are arranged in a ring shape from the inside to the outside along the radial direction of the chip unit 1.

[0108] Embodiment 3, as shown in Figure 3 , the inner active region 14, the inner gate 13, the outer gate 11, and the outer active region 12 are arranged in a ring shape from the inside to the outside along the radial direction of the chip unit 1.

[0109] Embodiment 4, as shown in Figure 4 , the inner gate 13, the inner active region 14, the outer gate 11, and the outer active region 12 are arranged in a ring shape from the inside to the outside along the radial direction of the chip unit 1.

[0110] In some embodiments, please combine with Figures 1 to 4 to understand that the on-optimization region includes the inner gate 13 and the inner active region 14; the off-optimization region includes the outer gate 11 and the outer active region 12. Correspondingly, the first ends of the inner active region 14 and the outer active region 12 are isolated, and the second ends of the inner active region 14 and the outer active region 12 are connected to form a first current port A.

[0111] Here, the first current port A is the main circuit current inflow port.

[0112] In addition, matching the relative positional relationship between the outer active region 12 and the outer gate 11, the isolation between the inner active region 14 and the outer active region 12 can be achieved through the inner gate 13, for example Figure 1 as shown in; or can be achieved through the inner gate 13 and the outer gate 11 together, for example Figure 3as shown in; or it can be achieved through the external gate 11, for example Figure 4 as shown in; or other isolation methods can also be used for isolation, such as Figure 2 physical isolation in

[0113] Moreover, it can be understood that the first ends of the inner active region 14 and the outer active region 12 are isolated by the corresponding gate, which means that the first ends of the inner active region 14 and the outer active region 12 can be insulated and isolated through the insulating layer included in the corresponding gate. It should be added that in the embodiments of the present disclosure, each element involved may include insulating materials for insulation protection as appropriate; the connection between the elements mentioned in the embodiments of the present disclosure only describes the conductive connection that can be achieved between the elements, and the implementation manner of the conductive connection between the elements can also be set according to the requirements. In addition, in the embodiments of the present disclosure, each element involved may also include other necessary components as appropriate. For example, reference can be made to the relevant features in the related art, and the embodiments of the present disclosure will not expand on this.

[0114] In the embodiments of the present disclosure, an on-optimization region and an off-optimization region are integrated in the same chip unit 1, and at least an auxiliary off-component 2 connected to the off-optimization region is provided in the auxiliary package structure. Thus, the chip unit 1 can provide a first current path in the on-optimization region and a second current path in the off-optimization region in the on mode, and transfer the current in the on-optimization region to the off-optimization region and the auxiliary off-component 2 in the off mode, and the off current of the off-optimization region can be increased through the auxiliary off-component 2 to assist the off-optimization region to turn off. In this way, through the circuit structure design of the chip unit 1 and the auxiliary off-component 2 in the power semiconductor device, the present disclosure can effectively improve both the current conduction ability and the current off ability on a single power semiconductor device, so as to further improve the electrical performance of the power semiconductor device. In addition, the power semiconductor device provided by the embodiments of the present disclosure also has the advantages of retaining double-sided heat dissipation and short-circuit failure mode.

[0115] Optionally, the auxiliary off-component 2 includes: a gate-cathode enhanced off-component, a gate enhanced off-component, a gate-gate-cathode enhanced off-component or a gate-gate enhanced off-component. That is: the auxiliary off-component 2 can be implemented by using a gate-cathode enhanced off-component, a gate enhanced off-component, a gate-gate-cathode enhanced off-component or a gate-gate enhanced off-component, etc. corresponding to the chip type of the chip unit 1. And, matching the chip type of the chip unit 1, the auxiliary off-component 2 can have a variety of different specific implementations. In the following some embodiments, the focus is on describing the differences between different embodiments, and the relevant or similar setting methods can be referred to and executed.

[0116] In some embodiments of the present disclosure, please refer toFigure 5 and Figure 6 The auxiliary turn-off component 2 is a gate-cathode enhanced turn-off component. The gate-cathode enhanced turn-off component includes a gate field-effect transistor group 21 and a cathode field-effect transistor group 22. Among them, the first end of the gate field-effect transistor group 21 is connected to the outer gate 11. The first end of the cathode field-effect transistor group 22 is connected to the third end of the outer active region 12. The second ends of the gate field-effect transistor group 21, the cathode field-effect transistor group 22, and the third end of the inner active region 14 are connected to form a second current port K.

[0117] Here, the second current port K is also the main circuit current output port.

[0118] Optionally, the setting area of the gate field-effect transistor group 21 can be located above the outer gate 11 and have the same or similar shape and size as the outer gate 11.

[0119] Optionally, the setting area of the cathode field-effect transistor group 22 can be located above the outer active region 12 and have the same or similar shape and size as the outer active region 12.

[0120] Here, it can be understood that matching the relative positional relationship between the outer active region 12 and the outer gate 11, Figure 5 The shown gate-cathode enhanced turn-off component can be applicable to Figure 1 and Figure 2 the shown chip unit 1, Figure 6 The shown gate-cathode enhanced turn-off component can be applicable to Figure 3 and Figure 4 the shown chip unit 1.

[0121] Exemplarily, please continue to refer to Figure 5 and Figure 6 The auxiliary packaging structure further includes a first vacant area 24 for exposing at least part of the conduction optimization area; the first vacant area 24 is used to accommodate the cathode lead electrode of the conduction optimization area. Among them, taking Figure 5 the shown gate-cathode enhanced turn-off component as an example, the gate field-effect transistor group 21 can be arranged around the periphery of the cathode field-effect transistor group 22. And, the cathode field-effect transistor group 22 can be arranged in a ring shape to form a first vacant area 24 inside the ring of the cathode field-effect transistor group 22. And, the first vacant area 24 in other gate-cathode enhanced turn-off components can be specifically set according to its structure, which will not be elaborated one by one here.

[0122] It should be added that, in some examples, the auxiliary encapsulation structure may further include lead electrodes and gate components. In this way, the aforementioned first current port A and second current port K can both be led out and connected through corresponding lead electrodes, and the gates of the outer gate 11, inner gate 13, and the gate FET group 21 and cathode FET group 22 in the auxiliary turn-off component 2 can all be led out and connected through corresponding gate components. The embodiments of the present disclosure do not limit the structures of the lead electrodes and gate components, as long as they have corresponding functions.

[0123] In some other embodiments of the present disclosure, please refer to Figure 7 and Figure 8 , the auxiliary turn-off component 2 is a gate-cathode enhanced turn-off component. The gate-cathode enhanced turn-off component includes a gate FET group 21, a cathode FET group 22, and an auxiliary connection component 25; wherein, the first end of the gate FET group 21 is connected to the outer gate 11, and the first end of the cathode FET group 22 is connected to the third end of the outer active region 12; the second ends of the gate FET group 21, the cathode FET group 22, and the third end of the inner active region 14 are connected and form the second current port K; the auxiliary connection component 25 is connected to the inner gate 13.

[0124] Exemplarily, the auxiliary connection component 25 can adopt a ring-shaped copper electrode with surface exposed treatment for electrically leading out the inner gate 13.

[0125] To more clearly understand the above Figures 5 to 8 gate-cathode enhanced turn-off component, Figure 9 shows Figures 5 to 8 an equivalent circuit diagram of the gate-cathode enhanced turn-off component in Figure 9 and Figure 10 , taking the thyristor (GCT-ETO) of the gate-commutated-emitter turn-off type as the power semiconductor device as an example, a possible control method of the power semiconductor device is schematically shown.

[0126] Please combine Figure 9 and Figure 10 to understand that the working modes of the power semiconductor device include: turn-on mode, conduction mode, turn-off mode, and blocking mode. Among them, the impedance between the first current port A and the second current port K is lower in the conduction mode and higher in the blocking mode. And the turn-on mode refers to the intermediate process from the blocking mode to the conduction mode, and the turn-off mode refers to the intermediate process from the conduction mode to the blocking mode.

[0127] The turn-on mode includes t 1 moment, t 2 moment and t 3 moment.

[0128] At t 1 moment, the control signal of gate G1 changes from the off signal to the on signal, and the internal active region 14 presents a low impedance, so as to provide a main circuit current path for the conduction optimization region; among them, the voltage clamping between the first current port A and the second current port K is close to 0V. At the same time, the control signal of gate G4 changes from the off signal to the on signal, and the cathode field effect transistor group 22 presents a low impedance, but the external active region 12 in series with the cathode field effect transistor group 22 is still a high impedance and cannot establish a main circuit current path in the turn-off optimization region.

[0129] At t 2 moment, the control signal of gate G2 changes from the off signal to the on signal, but because the control signal of gate G3 remains the on signal, the gate field effect transistor group 21 can continuously clamp the control signal of gate G2 as the off signal, and the external active region 12 still maintains a high impedance.

[0130] At t 3 moment, the control signal of gate G3 changes from the on signal to the off signal, the clamping of the control signal of gate G2 is released, and the external active region 12 can present a low impedance after zero-voltage turn-on, so as to provide an additional main circuit current path for the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the turn-on mode.

[0131] The turn-off mode includes t 4 moment, t 5 moment and t 6 moment.

[0132] At t 4 moment, the control signal of gate G1 changes from the on signal to the off signal, and the internal active region 14 presents a high impedance after zero-voltage turn-off, which can transfer all the current between the first current port A and the second current port K to the external active region 12 and the cathode field effect transistor group 22.

[0133] At t 5At this moment, the control signal of gate G3 changes from the off signal to the on signal. The gate FET group 21 presents a low impedance. The gate FET group 21 can re-clamp the control signal of gate G2 to the off signal and bypass the control ability of gate G2 to the external active region 12.

[0134] At t 6 At this moment, the control signal of gate G4 changes from the on signal to the off signal. The cathode FET group 22 presents a high impedance. The current of the cathode FET group 22 can be completely transferred to the low-impedance gate FET group 21. The external active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0135] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 At this moment, the control signal of gate G2 changes from the on signal to the off signal. However, since the control signal of gate G2 is clamped by the gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0136] In some other embodiments of the present disclosure, the auxiliary turn-off component 2 is a gate-cathode enhanced turn-off component. Please refer to Figures 5 to 8 and Figure 11 for understanding. The gate-cathode enhanced turn-off component includes a gate FET group 21 and a cathode diode group 22; wherein, the gate-cathode enhanced turn-off component includes; a gate FET group 21 and a cathode diode group 22. Among them, the first end of the gate FET group 21 is connected to the external gate 11. The first end of the cathode diode group 22 is connected to the third end of the external active region 12. The second end of the gate FET group 21, the second end of the cathode diode group 22 and the third end of the internal active region 14 are connected to form the second current port K.

[0137] In some examples, the auxiliary package structure may further include lead electrodes and a gate component. In this way, the aforementioned first current port A and second current port K can both be led out and connected through corresponding lead electrodes. The external gate 11, the internal gate 13 and the gate of the gate FET group 21 in the auxiliary turn-off component 2 can all be led out and connected through corresponding gate components. The embodiments of the present disclosure do not limit the structures of the lead electrodes and the gate components, as long as they have corresponding functions.

[0138] Thus, at Figure 11In the equivalent circuit diagram shown, gate G1 is the control gate for the conduction optimization region (i.e., the inner gate 13) and is used to control the inner active region 14; gate G2 is the control gate for the turn-off optimization region (i.e., the outer gate 11) and is used to control the outer active region 12; gate G3 is the control gate for the gate field effect transistor group 21. Accordingly, Figure 11 and Figure 12 take the thyristor (GCT-DAGCT) with the power semiconductor device as the gate-commutated diode-assisted gate-commutated type in

[0139] Please combine with Figure 11 and Figure 12 to understand that the operating modes of the power semiconductor device include: turn-on mode, conduction mode, turn-off mode, and blocking mode. Among them, the impedance between the first current port A and the second current port K is lower in the conduction mode and higher in the blocking mode. And the turn-on mode refers to the intermediate process from the blocking mode to the conduction mode, and the turn-off mode refers to the intermediate process from the conduction mode to the blocking mode.

[0140] The turn-on mode includes t 1 moment and t 2 moment.

[0141] At t 1 moment, the control signal of gate G1 changes from the off signal to the on signal, and the inner active region 14 presents a low impedance to provide a main circuit current path for the conduction optimization region; among them, the voltage clamp between the first current port A and the second current port K is close to 0V. At the same time, the control signal of gate G2 changes from the off signal to the on signal, but because the control signal of gate G3 remains the on signal, the gate field effect transistor group 21 can continuously clamp the control signal of gate G2 as the off signal, and the outer active region 12 still maintains a high impedance.

[0142] At t 2 moment, the control signal of gate G3 changes from the on signal to the off signal, the clamping of the control signal of gate G2 is released, and the outer active region 12 can achieve zero-voltage turn-on and then presents a low impedance to provide an additional main circuit current path for the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the conduction mode.

[0143] The turn-off mode includes t 3 moment and t 4 moment.

[0144] At t3 At this moment, the control signal of the gate G1 changes from the turn-on signal to the turn-off signal. After the internal active region 14 is turned off with zero voltage, it presents a high impedance, which can transfer all the current between the first current port A and the second current port K to the external active region 12 and the cathode diode group 22.

[0145] At t 4 At this moment, the control signal of the gate G3 changes from the turn-off signal to the turn-on signal. The gate field effect transistor group 21 presents a low impedance. The gate field effect transistor group 21 can re-clamp the control signal of the gate G2 to the turn-off signal and bypass the control ability of the gate G2 to the external active region 12. At the same time, the impedance of the cathode diode group 22 is higher than that of the gate field effect transistor group 21. The current of the cathode diode group 22 can be all transferred to the low-impedance gate field effect transistor group 21. The external active region 12 realizes commutation turn-off and presents a high impedance, and the main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0146] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 5 At this moment, the control signal of the gate G2 changes from the turn-on signal to the turn-off signal, but since the control signal of the gate G2 is clamped by the gate field effect transistor group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0147] In some other embodiments of the present disclosure, please refer to Figure 13 and Figure 14 , the auxiliary turn-off component 2 is a gate-cathode enhanced turn-off component. The gate-cathode enhanced turn-off component includes a gate field effect transistor group 21, a gate capacitor group 23 and a cathode diode group 22; wherein, the gate field effect transistor group 21 is connected in series with the gate capacitor group 23, and the first end of the series branch of the gate field effect transistor group 21 and the gate capacitor group 23 is connected to the external gate 11. The first end of the cathode diode group 22 is connected to the third end of the external active region 12. The second end of the series branch of the gate field effect transistor group 21 and the gate capacitor group 23, the second end of the cathode diode group 22 and the third end of the internal active region 14 are connected to form the second current port K.

[0148] In some other embodiments of the present disclosure, please refer to Figure 15 and Figure 16, the auxiliary turn-off component 2 is a gate-cathode enhanced turn-off component. The gate-cathode enhanced turn-off component includes a gate field-effect transistor group 21, a gate capacitor group 23, a cathode diode group 22, and an auxiliary connection component 25. Among them, the gate field-effect transistor group 21 is connected in series with the gate capacitor group 23, and the first end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23 is connected to the external gate 11. The first end of the cathode diode group 22 is connected to the third end of the external active region 12. The second end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23, the second end of the cathode diode group 22, and the third end of the internal active region 14 are connected to form a second current port K. The auxiliary connection component 25 is connected to the internal gate 13.

[0149] In some examples, the auxiliary packaging structure may further include a lead electrode and a gate component. Thus, the aforementioned first current port A and second current port K can both be led out and connected through the corresponding lead electrodes, and the external gate 11, the internal gate 13, and the gates of the gate field-effect transistor group 21 and the charging ports of the gate capacitor group 23 in the auxiliary turn-off component 2 can all be led out and connected through the corresponding gate components. The embodiments of the present disclosure do not limit the structures of the lead electrode and the gate component, as long as they have the corresponding functions.

[0150] For a clearer understanding of the above Figures 13 to 16 gate-cathode enhanced turn-off component, Figure 17 shows Figures 13 to 16 an equivalent circuit diagram of the gate-cathode enhanced turn-off component. In the Figure 17 shown equivalent circuit diagram, the gate G1 is the control gate of the conduction optimization region (i.e., the internal gate 13) for controlling the internal active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the external gate 11) for controlling the external active region 12; the gate G3 is the control gate of the gate field-effect transistor group 21; the charging port Cp is the charging port of the gate capacitor group 22, and the electric potential at the charging port Cp is lower than the electric potential of the second current port K. Correspondingly, in Figure 17 when the power semiconductor device is a gate-commutated thyristor with diode-assisted gate commutation (GCT-DAGCT) type, the control method of this power semiconductor device can be implemented with reference to the Figure 12 shown control timing and the corresponding control method, and the difference between the two is only in t 4 the moment (the same implementation in other aspects will not be elaborated here).

[0151] In t 4At this moment, the control signal of the gate G3 changes from the off signal to the on signal. The gate field effect transistor group 21 presents a low impedance. The gate field effect transistor group 21 can re-clamp the control signal of the gate G2 to the off signal and bypass the control ability of the gate G2 to the external active region 12. At the same time, the impedance of the cathode diode group 22 is higher than that of the series branch of the gate field effect transistor group 21 and the gate capacitor group 23. The current of the cathode field effect transistor group 22 can be completely transferred to the gate field effect transistor group 21. The external active region 12 realizes commutation turn-off and presents a high impedance, and the main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0152] In some other embodiments of the present disclosure, please refer to Figure 18 and Figure 19 , the auxiliary turn-off component 2 is a gate enhancement turn-off component. The gate enhancement turn-off component includes a gate field effect transistor group 21. Among them, the first end of the gate field effect transistor group 21 is connected to the external gate 11. The second end of the gate field effect transistor group 21, the third end of the external active region 12, and the third end of the internal active region 14 are connected to form a second current port K.

[0153] Exemplarily, please refer to Figure 18 , the gate field effect transistor group 21 can be arranged in a ring shape to form a first vacant area 24 inside the ring of the gate field effect transistor group 21. In this way, the first vacant area 24 can be used to expose the conduction optimization area to reserve space for the cathode lead electrode of the conduction optimization area.

[0154] Exemplarily, please refer to Figure 19 , the gate field effect transistor group 21 can be arranged in a ring shape to form a first vacant area 24 inside the ring of the gate field effect transistor group 21 and a second vacant area 24' outside the ring of the gate field effect transistor group 21. In this way, the first vacant area 24 can be used to expose the conduction optimization area to reserve space for the cathode lead electrode of the conduction optimization area. The second vacant area 24' can be used to expose the external active region 12 so that the external active region 12 is connected to the cathode package case through the second vacant area 24'.

[0155] Optionally, the setting area of the gate field effect transistor group 21 can be located above the external gate 11 and has the same or similar shape and size as the external gate 11.

[0156] In some examples, the auxiliary package structure may further include a lead electrode and a gate component. In this way, the aforementioned first current port A and second current port K can be led out and connected through the corresponding lead electrodes, and the external gate 11, the internal gate 13, and the gates of the gate field effect transistor group 21 can be led out and connected through the corresponding gate components. The embodiments of the present disclosure do not limit the structures of the lead electrode and the gate component, as long as they have the corresponding functions.

[0157] In some other embodiments of the present disclosure, please refer to Figures 20 to 23 , the auxiliary turn-off component 2 is a gate-enhanced turn-off component. The gate-enhanced turn-off component includes a gate field-effect transistor group 21 and a first auxiliary connection component 25 and / or a second auxiliary connection component 25'; wherein, the first end of the gate field-effect transistor group 21 is connected to the outer gate 11. The second end of the gate field-effect transistor group 21, the third end of the outer active region 12, and the third end of the inner active region 14 are connected and form a second current port K. The first auxiliary connection component 25 is used to connect the inner gate 13. The second auxiliary connection component 25' is used to connect the outer active region 12.

[0158] Exemplarily, the first auxiliary connection component 25 may adopt a surface-exposed annular copper electrode for electrically leading out the inner gate 13. The second auxiliary connection component 25' may adopt a double-sided exposed annular copper electrode for connecting the outer active region 12 and the cathode package case ( Figures 20 to 23 not shown in the figure).

[0159] To more clearly understand the gate-enhanced turn-off component in the above Figures 18 to 23 , Figure 24 shows Figures 18 to 23 an equivalent circuit diagram of the gate-enhanced turn-off component in Figures 18 to 23 . Among them, the gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the gate field-effect transistor group 21. Correspondingly, when taking the power semiconductor device as a gate-commutated MOS turn-off thyristor (GCT-MTO) in Figure 12 , the control method of the power semiconductor device can be implemented with reference to the control timing and the corresponding control method shown in t 4 time (the same implementation in other places will not be elaborated here).

[0160] At t 4 time, the control signal of the gate G3 changes from the off signal to the on signal, the gate field-effect transistor group 21 presents a low impedance, the gate field-effect transistor group 21 can re-clamp the control signal of the gate G2 to the off signal, and bypass the control ability of the gate G2 to the outer active region 12. At the same time, the impedance between the gate and cathode of the outer active region 12 is higher than the impedance of the gate field-effect transistor group 21, and the current of the outer active region 12 can be completely transferred to the gate field-effect transistor group 21. The outer active region 12 realizes commutation turn-off and presents a high impedance, and the main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0161] In some other embodiments of the present disclosure, please refer to Figure 25 and Figure 26 , the auxiliary turn-off component 2 is a gate-enhanced turn-off component. The gate-enhanced turn-off component includes a gate field-effect transistor group 21 and a gate capacitor group 23. Among them, the gate field-effect transistor group 21 is connected in series with the gate capacitor group 23, and the first end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23 is connected to the outer gate 11. The second end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23, the third end of the outer active region 12, and the third end of the inner active region 14 are connected to form a second current port K.

[0162] In some other embodiments of the present disclosure, please refer to Figures 27 to 30 , the auxiliary turn-off component 2 is a gate-enhanced turn-off component. The gate-enhanced turn-off component includes a gate field-effect transistor group 21, a gate capacitor group 23, and a first auxiliary connection component 25 and / or a second auxiliary connection component 25'. Among them, the gate field-effect transistor group 21 is connected in series with the gate capacitor group 23, and the first end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23 is connected to the outer gate 11. The second end of the series branch of the gate field-effect transistor group 21 and the gate capacitor group 23, the third end of the outer active region 12, and the third end of the inner active region 14 are connected to form a second current port K. The first auxiliary connection component 25 is used to connect the inner gate 13. The second auxiliary connection component 25' is used to connect the outer active region 12.

[0163] In some examples, the auxiliary package structure may further include lead electrodes and gate components. In this way, the aforementioned first current port A and second current port K can both be led out and connected through corresponding lead electrodes, and the outer gate 11, the inner gate 13, the gate of the gate field-effect transistor group 21 in the auxiliary turn-off component 2, and the charging port in the gate capacitor group 23 can all be led out and connected through corresponding gate components. The embodiments of the present disclosure do not limit the structures of the lead electrodes and the gate components, as long as they have corresponding functions.

[0164] To more clearly understand the Figures 25 to 30 gate cathode enhanced turn-off component above, Figure 31 shows Figures 25 to 30 an equivalent circuit diagram of the gate cathode enhanced turn-off component in Figures 25 to 30When taking the gate-commutated thyristor (GCT-ICT) with a power semiconductor device as the gate-commutated - internal commutation type as an example, the control method of the power semiconductor device can refer to Figure 12 the control timing shown and the corresponding control method for implementation, and the difference between the two is only t 4 at the moment (the same implementation for others is not elaborated here).

[0165] At t 4 moment, the control signal of gate G3 changes from the off signal to the on signal, the gate MOSFET group 21 presents a low impedance, the gate MOSFET group 21 can re-clamp the control signal of gate G2 to the off signal, and bypass the control ability of gate G2 to the external active region 12. At the same time, the impedance between the gate and cathode of the external active region 12 is higher than the impedance of the series branch of the gate MOSFET group 21 and the gate capacitor group 23, and the current between the gate and cathode of the external active region 12 can be all transferred to the gate MOSFET group 21, the external active region 12 realizes commutation turn-off and presents a high impedance, and the main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0166] In some other embodiments of the present disclosure, please refer to Figure 32 , the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. The gate-gate cathode enhanced turn-off component includes an external gate MOSFET group 21, an external cathode MOSFET group 22, and an internal gate MOSFET group 26. Among them, the first end of the external gate MOSFET group 21 is connected to the external gate 11. The first end of the external cathode MOSFET group 22 is connected to the third end of the external active region 12. The first end of the internal gate MOSFET group 26 is connected to the internal gate 13. The second ends of the external gate MOSFET group 21, the external cathode MOSFET group 22, the internal gate MOSFET group 26, and the third end of the internal active region 14 are connected and form the second current port K.

[0167] For a clearer understanding of the above Figure 32 gate-gate cathode enhanced turn-off component in, Figure 33 shows an equivalent circuit diagram of the foregoing gate-gate cathode enhanced turn-off component. In Figure 33 the equivalent circuit diagram shown, the first current port A is the current inflow port, and the second current port K is the current outflow port. Gate G1 is the control gate of the conduction optimization region (i.e., the internal gate 13) for controlling the internal active region 14; Gate G2 is the control gate of the turn-off optimization region (i.e., the external gate 11) for controlling the external active region 12; Gate G3 is the control gate of the external gate MOSFET group 21; Gate G4 is the control gate of the external cathode MOSFET group 22; Gate G5 is the control gate of the internal gate MOSFET group 26. Correspondingly, inFigure 33 When taking the thyristor (MTO-ETO) with the power semiconductor device of MOS turn-off-emitter turn-off type as an example, the control method of the power semiconductor device can refer to Figure 34 the shown control timing sequence and the corresponding control method for implementation.

[0168] The turn-on mode includes t 1 moment, t 2 moment and t 3 moment.

[0169] At t 1 moment, the control signal of gate G1 changes from the off signal to the on signal. However, since the control signal of gate G5 remains the on signal, the inner gate FET group 26 can continuously clamp the control signal of gate G1 as the off signal, and the inner active region 14 still maintains a high impedance. At the same time, the control signal of gate G4 changes from the off signal to the on signal, and the outer cathode FET group 22 presents a low impedance, but the series-connected outer active region 12 thereof is still a high impedance and cannot establish the main circuit current path.

[0170] At t 2 moment, the control signal of gate G5 changes from the on signal to the off signal, the clamping of the control signal of gate G1 is released, and the inner active region 14 presents a low impedance to provide the main circuit current path. The voltage clamping between the first current port A and the second current port K is close to 0V. The control signal of gate G2 changes from the off signal to the on signal. However, since the control signal of gate G3 remains the on signal, the outer gate FET group 21 can continuously clamp the control signal of gate G2 as the off signal, and the outer active region 12 still maintains a high impedance.

[0171] At t 3 moment, the control signal of gate G3 changes from the on signal to the off signal, the clamping of the control signal of gate G2 is released, and the outer active region 12 can present a low impedance after achieving zero-voltage turn-on to provide an additional main circuit current path in the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the conduction mode.

[0172] The turn-off mode includes t 4 moment, t 5 moment and t 6 moment.

[0173] At t 4At this moment, the control signal of the gate G5 changes from the off signal to the on signal, and the internal gate FET group 26 presents a low impedance, which can re-clamp the control signal of the gate G1 and bypass the control ability of the gate G1 to the internal active region 14.

[0174] At t 5 At this moment, the control signal of the gate G1 changes from the on signal to the off signal. After the internal active region 14 is turned off with zero voltage, it presents a high impedance, and all the current between the first current port A and the second current port K is transferred to the external active region 12 and the external cathode FET group 22. At the same time, the control signal of the gate G3 changes from the off signal to the on signal, and the external gate FET group 21 presents a low impedance, which can re-clamp the control signal of the gate G2 and bypass the control ability of the gate G2 to the external active region 12.

[0175] At t 6 At this moment, the control signal of the gate G4 changes from the on signal to the off signal, the external cathode FET group 22 presents a high impedance, all the current of the external cathode FET group 22 is transferred to the low-impedance external gate FET group 21, and the external active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0176] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 At this moment, the control signal of the gate G2 changes from the on signal to the off signal, but since the control signal of the gate G2 is clamped by the external gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0177] In some other embodiments of the present disclosure, the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. Please refer to Figure 32 and Figure 35 for understanding. The gate-gate cathode enhanced turn-off component includes an external gate FET group 21, an external cathode diode group 22 and an internal gate FET group 26; wherein, the first end of the external gate FET group 21 is connected to the external gate 11. The first end of the external cathode diode group 22 is connected to the third end of the external active region 12. The first end of the internal gate FET group 26 is connected to the internal gate 13. The second ends of the external gate FET group 21, the external cathode diode group 22, the internal gate FET group 26 and the third end of the internal active region 14 are connected to form the second current port K.

[0178] At Figure 35In the equivalent circuit diagram shown, the first current port A is the current input port, and the second current port K is the current output port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. Correspondingly, when taking the thyristor (MTO-DAGCT) with the MOS turn-off - diode assisted gate commutation type as the power semiconductor device in Figure 35 as an example, the control method of this power semiconductor device can refer to Figure 36 the control timing shown and the corresponding control method for implementation.

[0179] The turn-on mode includes t 1 moment, t 2 moment and t 3 moment.

[0180] At t 1 moment, the control signal of the gate G1 changes from the off signal to the on signal. However, since the control signal of the gate G5 remains the on signal, the inner gate field effect transistor group 26 can continuously clamp the control signal of the gate G1 as the off signal, and the inner active region 14 still maintains a high impedance.

[0181] At t 2 moment, the control signal of the gate G5 changes from the on signal to the off signal, the clamping of the control signal of the gate G1 is released, the inner active region 14 presents a low impedance to provide the main circuit current path. The voltage clamping between the first current port A and the second current port K is close to 0V. The control signal of the gate G2 changes from the off signal to the on signal. However, since the control signal of the gate G3 remains the on signal, the outer gate field effect transistor group 21 can continuously clamp the control signal of the gate G2 as the off signal, and the outer active region 12 still maintains a high impedance.

[0182] At t 3 moment, the control signal of the gate G3 changes from the on signal to the off signal, the clamping of the control signal of the gate G2 is released, the outer active region 12 can achieve zero voltage turn-on and then presents a low impedance to provide an additional main circuit current path in the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the turn-on mode.

[0183] The turn-off mode includes t 4 moment, t5 Time and t 6 time.

[0184] At t 4 time, the control signal of gate G5 changes from the off signal to the on signal, and the internal gate FET group 26 presents a low impedance, which can re-clamp the control signal of gate G1 and bypass the control ability of gate G1 to the internal active region 14.

[0185] At t 5 time, the control signal of gate G1 changes from the on signal to the off signal. After the internal active region 14 is turned off at zero voltage, it presents a high impedance, and all the current between the first current port A and the second current port K is transferred to the external active region 12 and the external cathode diode group 22.

[0186] At t 6 time, the control signal of gate G3 changes from the off signal to the on signal, and the external gate FET group 21 presents a low impedance, which can re-clamp the control signal of gate G2 and bypass the control ability of gate G2 to the external active region 12. The impedance of the external cathode diode group 22 is higher than that of the external gate FET group 21, and all the current of the external cathode diode group 22 is transferred to the low-impedance external gate FET group 21. The external active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0187] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 time, the control signal of gate G2 changes from the on signal to the off signal, but since the control signal of gate G2 is clamped by the external gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0188] In some other embodiments of the present disclosure, please refer to Figure 37, the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. The gate-gate cathode enhanced turn-off component includes an outer gate field effect transistor group 21, an outer cathode field effect transistor group 22, an inner gate field effect transistor group 26, and an inner gate capacitor group 27; wherein, the first end of the outer gate field effect transistor group 21 is connected to the outer gate 11. The first end of the outer cathode field effect transistor group 22 is connected to the third end of the outer active region 12. The first end of the inner gate field effect transistor group 26 is connected to the inner gate 13, and the second end of the inner gate field effect transistor group 26 is connected to the first end of the inner gate capacitor group 27. The second ends of the outer gate field effect transistor group 21, the outer cathode field effect transistor group 22, the second end of the inner gate capacitor group 27, and the third end of the inner active region 14 are connected and form a second current port K.

[0189] For a clearer understanding of the above Figure 37 gate-gate cathode enhanced turn-off component in Figure 38 shows an equivalent circuit diagram of the aforementioned gate-gate cathode enhanced turn-off component. In Figure 38 the shown equivalent circuit diagram, the first current port A is the current inflow port, and the second current port K is the current outflow port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G4 is the control gate of the outer cathode field effect transistor group 22; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp' is the charging port of the inner gate capacitor group 27, and the electric potential at the charging port Cp' is lower than the electric potential of the second current port K. Correspondingly, when Figure 38 taking the thyristor (ICT-ETO) with the internal commutation-emitter turn-off type as the power semiconductor device as an example, the control method of this power semiconductor device can be implemented with reference to Figure 34 the shown control timing and the corresponding control method.

[0190] The turn-on mode includes t 1 moment, t 2 moment, and t 3 moment.

[0191] At t 1At this moment, the control signal of gate G1 changes from the off signal to the on signal. However, since the control signal of gate G5 remains the on signal, the internal gate FET group 26 can continuously clamp the control signal of gate G1 as the off signal, and the internal active region 14 still maintains a high impedance. At the same time, the control signal of gate G4 changes from the off signal to the on signal. The external cathode FET group 22 presents a low impedance, but the series-connected external active region 12 is still of high impedance and cannot establish a main circuit current path.

[0192] At t 2 this moment, the control signal of gate G5 changes from the on signal to the off signal, and the clamping of the control signal of gate G1 is released. The internal active region 14 presents a low impedance to provide a main circuit current path. The voltage clamp between the first current port A and the second current port K is close to 0V. The control signal of gate G2 changes from the off signal to the on signal. However, since the control signal of gate G3 remains the on signal, the external gate FET group 21 can continuously clamp the control signal of gate G2 as the off signal, and the external active region 12 still maintains a high impedance.

[0193] At t 3 this moment, the control signal of gate G3 changes from the on signal to the off signal, and the clamping of the control signal of gate G2 is released. The external active region 12 can present a low impedance after achieving zero-voltage turn-on to provide an additional main circuit current path in the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the conduction mode.

[0194] The turn-off mode includes t 4 this moment, t 5 this moment and t 6 this moment.

[0195] At t 4 this moment, the control signal of gate G5 changes from the off signal to the on signal. The internal gate FET group 26 presents a low impedance, can re-clamp the control signal of gate G1, and bypass the control ability of gate G1 on the internal active region 14. At this time, the impedance between the gate and cathode of the internal active region 14 is higher than the impedance of the series circuit of the internal gate FET group 26 and the internal gate capacitor group 27. All of its current is transferred to the internal gate FET group 26, and the internal active region 14 realizes commutation turn-off and presents a high impedance. All the current between the first current port A and the second current port K is transferred to the external active region 12 and the external cathode FET group 22.

[0196] At t 5At this moment, the control signal of gate G1 changes from the turn-on signal to the turn-off signal. However, due to the control clamping of the inner gate FET group 26 on gate G1, the state of the inner active region 14 remains unchanged and remains in the high-impedance blocking state. At the same time, the control signal of gate G3 changes from the turn-off signal to the turn-on signal, and the outer gate FET group 21 presents a low impedance, which can re-clamp the control signal of gate G2 and bypass the control ability of gate G2 on the outer active region 12.

[0197] At t 6 At this moment, the control signal of gate G4 changes from the turn-on signal to the turn-off signal, the outer cathode FET group 22 presents a high impedance, and all the current of the outer cathode FET group 22 is transferred to the low-impedance outer gate FET group 21. The outer active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0198] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 At this moment, the control signal of gate G2 changes from the turn-on signal to the turn-off signal. However, due to the control signal of gate G2 being clamped by the outer gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0199] In some other embodiments of the present disclosure, the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. Please refer to Figure 37 and Figure 39 for understanding. The gate-gate cathode enhanced turn-off component includes an outer gate FET group 21, an outer cathode diode group 22, an inner gate FET group 26, and an inner gate capacitor group 27; wherein, the first end of the outer gate FET group 21 is connected to the outer gate 11. The first end of the outer cathode diode group 22 is connected to the third end of the outer active region 12. The first end of the inner gate FET group 26 is connected to the inner gate 13, and the second end of the inner gate FET group 26 is connected to the first end of the inner gate capacitor group 27. The second end of the outer gate FET group 21, the second end of the outer cathode diode group 22, the second end of the inner gate capacitor group 27, and the third end of the inner active region 14 are connected to form the second current port K.

[0200] At Figure 39In the equivalent circuit diagram shown, the first current port A is the current inflow port, and the second current port K is the current outflow port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp' is the charging port of the inner gate capacitor group 27, and the electric potential at the charging port Cp' is lower than the electric potential of the second current port K. Correspondingly, when taking the thyristor (ICT-DAGCT) with the power semiconductor device as the internal commutation - diode assisted gate commutation type in Figure 39 as an example, the control method of this power semiconductor device can refer to Figure 36 the control timing shown and the corresponding control method for implementation.

[0201] The turn-on mode includes t 1 moment, t 2 moment, and t 3 moment.

[0202] At t 1 moment, the control signal of the gate G1 changes from the off signal to the on signal. However, since the control signal of the gate G5 remains the on signal, the inner gate field effect transistor group 26 can continuously clamp the control signal of the gate G1 as the off signal, and the inner active region 14 still maintains a high impedance.

[0203] At t 2 moment, the control signal of the gate G5 changes from the on signal to the off signal, the clamping of the control signal of the gate G1 is released, and the inner active region 14 presents a low impedance to provide the main circuit current path. The voltage clamping between the first current port A and the second current port K is close to 0V. At the same time, the control signal of the gate G2 changes from the off signal to the on signal. However, since the control signal of the gate G3 remains the on signal, the outer gate field effect transistor group 21 can continuously clamp the control signal of the gate G2 as the off signal, and the outer active region 12 still maintains a high impedance.

[0204] At t 3 moment, the control signal of the gate G3 changes from the on signal to the off signal, the clamping of the control signal of the gate G2 is released, and the outer active region 12 can achieve zero-voltage turn-on and then present a low impedance to provide an additional main circuit current path in the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the turn-on mode.

[0205] The turn-off mode includes t 4 a moment, t 5 a moment, and t 6 a moment.

[0206] At t 4 the moment, the control signal of gate G5 changes from the off signal to the on signal. The inner gate FET group 26 presents a low impedance, can re-clamp the control signal of gate G1, and bypasses the control ability of gate G1 to the inner active region 14. At this time, the impedance between the gate and cathode of the inner active region 14 is higher than the impedance of the series circuit of the inner gate FET group 26 and the inner gate capacitor group 27. All of its current is transferred to the inner gate FET group 26, and the inner active region 14 realizes commutation turn-off and presents a high impedance. All the current between the first current port A and the second current port K is transferred to the outer active region 12 and the outer cathode diode group 22.

[0207] At t 5 the moment, the control signal of gate G1 changes from the on signal to the off signal. However, due to the control clamping of gate G1 by the inner gate FET group 26, the state of the inner active region 14 remains unchanged and remains in a high-impedance blocking state.

[0208] At t 6 the moment, the control signal of gate G3 changes from the off signal to the on signal. The outer gate FET group 21 presents a low impedance, can re-clamp the control signal of gate G2, and bypasses the control ability of gate G2 to the outer active region 12. The impedance of the outer cathode diode group 22 is higher than that of the outer gate FET group 21. All the current of the outer cathode diode group 22 is transferred to the low-impedance outer gate FET group 21, and the outer active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0209] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 the moment, the control signal of gate G2 changes from the on signal to the off signal. However, since the control signal of gate G2 is clamped by the outer gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0210] In some other embodiments of the present disclosure, please refer to Figure 40 and Figure 41It is understood that the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. The gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group 21, an external cathode diode group 22, an external gate capacitor group 23, and an internal gate field effect transistor group 26. Among them, the first end of the external gate field effect transistor group 21 is connected to the external gate 11, and the second end of the external gate field effect transistor group 21 is connected to the first end of the external gate capacitor group 23. The first end of the external cathode diode group 22 is connected to the third end of the external active region 12. The first end of the internal gate field effect transistor group 26 is connected to the internal gate 13. The second end of the external gate capacitor group 23, the second end of the external cathode diode group 22, the second end of the internal gate field effect transistor group 26, and the third end of the internal active region 14 are connected and form a second current port K.

[0211] In Figure 41 In the equivalent circuit diagram shown, the first current port A is the current inflow port, and the second current port K is the current outflow port. The gate G1 is the control gate of the conduction optimization region (i.e., the internal gate 13) for controlling the internal active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the external gate 11) for controlling the external active region 12; the gate G3 is the control gate of the external gate field effect transistor group 21; the gate G5 is the control gate of the internal gate field effect transistor group 26. The charging port Cp is the charging port of the external gate capacitor group 23, and the potential of the charging port Cp is lower than the potential of the second current port K. Correspondingly, in Figure 41 when the power semiconductor device is a thyristor of the MOS turn-off-diode auxiliary gate turn-off type (MTO-DAGTO) as an example, the control method of the power semiconductor device can refer to Figure 36 the control timing and the corresponding control method shown for implementation.

[0212] The turn-on mode includes t 1 moment, t 2 moment, and t 3 moment.

[0213] In t 1 At this moment, the control signal of the gate G1 changes from the off signal to the on signal. However, since the control signal of the gate G5 remains the on signal, the internal gate field effect transistor group 26 can continuously clamp the control signal of the gate G1 to the off signal, and the internal active region 14 still maintains a high impedance.

[0214] In t 2At this moment, the control signal of gate G5 changes from the turn-on signal to the turn-off signal, the clamping of the control signal of gate G1 is released, and the internal active region 14 presents a low impedance to provide the main circuit current path. The voltage clamping between the first current port A and the second current port K is close to 0V. At the same time, the control signal of gate G2 changes from the turn-off signal to the turn-on signal. However, since the control signal of gate G3 remains the turn-on signal, the external gate MOSFET group 21 can continuously clamp the control signal of gate G2 to the turn-off signal, and the external active region 12 still maintains a high impedance.

[0215] At t 3 At this moment, the control signal of gate G3 changes from the turn-on signal to the turn-off signal, the clamping of the control signal of gate G2 is released, and the external active region 12 can present a low impedance after zero-voltage turn-on to provide an additional main circuit current path in the turn-off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the conduction mode.

[0216] The turn-off mode includes t 4 At this moment, t 5 At this moment, and t 6 At this moment.

[0217] At t 4 At this moment, the control signal of gate G5 changes from the turn-off signal to the turn-on signal, the internal gate MOSFET group 26 presents a low impedance, can reclamp the control signal of gate G1, and bypasses the control ability of gate G1 to the internal active region 14.

[0218] At t 5 At this moment, the control signal of gate G1 changes from the turn-on signal to the turn-off signal, the internal active region 14 presents a high impedance after zero-voltage turn-off, and all the current between the first current port A and the second current port K is transferred to the external active region 12 and the external cathode diode group 22.

[0219] At t 6At this moment, the control signal of the gate G3 changes from the off signal to the on signal. The external gate FET group 21 presents a low impedance, can re-clamp the control signal of the gate G2, and bypasses the control ability of the gate G2 to the external active region 12. At this time, the impedance of the external cathode diode group 22 is higher than the impedance of the series circuit of the external gate FET group 21 and the external gate capacitor group 23. All the current of the external cathode diode group 22 is transferred to the external gate FET group 21, and the external active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0220] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 At this moment, the control signal of the gate G2 changes from the on signal to the off signal, but since the control signal of the gate G2 is clamped by the external gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0221] In some other embodiments of the present disclosure, please refer to Figure 42 and Figure 43 to understand that the auxiliary turn-off component 2 is a gate-gate cathode enhanced turn-off component. The gate-gate cathode enhanced turn-off component includes an external gate FET group 21, an external cathode diode group 22, an external gate capacitor group 23, an internal gate FET group 26, and an internal gate capacitor group 27. Among them, the first end of the external gate FET group 21 is connected to the external gate 11, and the second end of the external gate FET group 21 is connected to the first end of the external gate capacitor group 23. The first end of the external cathode diode group 22 is connected to the third end of the external active region 12. The first end of the internal gate FET group 26 is connected to the internal gate 13. The second end of the internal gate FET group 26 is connected to the first end of the internal gate capacitor group 27. The second end of the external gate capacitor group 23, the second end of the external cathode diode group 22, the second end of the internal gate FET group 26, the second end of the internal gate capacitor group 27, and the third end of the internal active region 14 are connected and form the second current port K.

[0222] At Figure 43In the equivalent circuit diagram shown, the first current port A is the current input port, and the second current port K is the current output port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp is the charging port of the outer gate capacitor group 23, and the charging port Cp' is the charging port of the inner gate capacitor group 27. The electric potentials of the charging ports Cp and Cp' are both lower than the electric potential of the second current port K. Correspondingly, when taking the thyristor (ICT-DAGTO) with the power semiconductor device as the internal commutation - diode assisted gate turn-off type in Figure 43 as an example, the control method of this power semiconductor device can refer to Figure 36 the shown control timing sequence and the corresponding control method for implementation.

[0223] The turn - on mode includes t 1 moment, t 2 moment and t 3 moment.

[0224] At t 1 moment, the control signal of the gate G1 changes from the off signal to the on signal. However, since the control signal of the gate G5 remains the on signal, the inner gate field effect transistor group 26 can continuously clamp the control signal of the gate G1 as the off signal, and the inner active region 14 still maintains a high impedance.

[0225] At t 2 moment, the control signal of the gate G5 changes from the on signal to the off signal, the clamping of the control signal of the gate G1 is released, and the inner active region 14 presents a low impedance to provide the main circuit current path. The voltage clamping between the first current port A and the second current port K is close to 0V. At the same time, the control signal of the gate G2 changes from the off signal to the on signal. However, since the control signal of the gate G3 remains the on signal, the outer gate field effect transistor group 21 can continuously clamp the control signal of the gate G2 as the off signal, and the outer active region 12 still maintains a high impedance.

[0226] At t 3 moment, the control signal of the gate G3 changes from the on signal to the off signal, the clamping of the control signal of the gate G2 is released, and the outer active region 12 can achieve zero - voltage turn - on and then presents a low impedance to provide an additional main circuit current path for the turn - off optimization region, thereby further reducing the conduction loss of the power semiconductor device. Thus, the power semiconductor device enters the turn - on mode.

[0227] The turn-off mode includes t 4 a moment, t 5 a moment, and t 6 a moment.

[0228] At t 4 the moment, the control signal of gate G5 changes from the off signal to the on signal, and the inner gate FET group 26 presents a low impedance, which can re-clamp the control signal of gate G1 and bypass the control ability of gate G1 to the inner active region 14. At this time, the impedance between the gate and cathode of the inner active region 14 is higher than the impedance of the series circuit of the inner gate FET group 26 and the inner gate capacitor group 27, and all its current is transferred to the inner gate FET group 26. The inner active region 14 realizes commutation turn-off and presents a high impedance. The current between the first current port A and the second current port K is all transferred to the outer active region 12 and the outer cathode diode group 22.

[0229] At t 5 the moment, the control signal of gate G1 changes from the on signal to the off signal. After the inner active region 14 is turned off at zero voltage, it presents a high impedance, and the current between the first current port A and the second current port K is all transferred to the outer active region 12 and the outer cathode diode group 22.

[0230] At t 6 the moment, the control signal of gate G3 changes from the off signal to the on signal, and the outer gate FET group 21 presents a low impedance, which can re-clamp the control signal of gate G2 and bypass the control ability of gate G2 to the outer active region 12. At this time, the impedance of the outer cathode diode group 22 is higher than the impedance of the series circuit of the outer gate FET group 21 and the outer gate capacitor group 23, and all the current of the outer cathode diode group 22 is transferred to the outer gate FET group 21. The outer active region 12 realizes commutation turn-off and presents a high impedance. The main circuit current path between the first current port A and the second current port K is completely cut off. Thus, the power semiconductor device enters the blocking mode.

[0231] In addition, by way of example, the operating mode of the power semiconductor device further includes a holding mode. For example, at t 7 the moment, the control signal of gate G2 changes from the on signal to the off signal, but since the control signal of gate G2 is clamped by the outer gate FET group 21. Therefore, the power semiconductor device is in the holding mode, that is, the operating mode of the device will not change.

[0232] In some other embodiments of the present disclosure, please refer to Figures 44 to 51It is understood that the auxiliary turn-off component 2 is a gate-gate enhanced turn-off component. The gate-gate enhanced turn-off component includes an outer gate auxiliary turn-off component, an inner gate auxiliary turn-off component, and an auxiliary connection component 25' disposed between the outer gate auxiliary turn-off component and the inner gate auxiliary turn-off component. The auxiliary connection component 25' is used to connect the outer active region 12.

[0233] Optionally, the auxiliary connection component 25' connects the outer active region 12 and the lead electrode of the package case.

[0234] Here, the outer gate auxiliary turn-off component and the inner gate auxiliary turn-off component can be set with reference to the structures of the gate enhanced turn-off components in some of the foregoing embodiments respectively.

[0235] Exemplarily, please refer to Figure 44 and Figure 45 , the outer gate auxiliary turn-off component is composed of an outer gate field effect transistor group 21, and the inner gate auxiliary turn-off component is composed of an inner gate field effect transistor group 26. Figure 45 shows an equivalent circuit of a gate-gate enhanced turn-off component with a power semiconductor device being a MOS turn-off - MOS turn-off type thyristor (MTO - MTO) as an example. In the Figure 45 shown equivalent circuit diagram, the first current port A is the current inflow port, and the second current port K is the current outflow port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The control method of this power semiconductor device can be implemented with reference to the control timing and the corresponding control method shown in Figure 36 .

[0236] Exemplarily, please refer to Figure 46 and Figure 47 , the outer gate auxiliary turn-off component is composed of an outer gate field effect transistor group 21, and the inner gate auxiliary turn-off component is composed of a series connection of an inner gate field effect transistor group 26 and an inner gate capacitor group 27. Figure 47 shows an equivalent circuit of a gate-gate enhanced turn-off component with a power semiconductor device being an internal commutation - MOS turn-off type thyristor (ICT - MTO) as an example. In Figure 47In the equivalent circuit diagram shown, the first current port A is the current input port, and the second current port K is the current output port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp' is the charging port of the inner gate capacitor group 27, and the potential of the charging port Cp' is lower than the potential of the second current port K. The control method of this power semiconductor device can refer to Figure 36 the control timing diagram shown and the corresponding control method for implementation.

[0237] Exemplarily, please refer to Figure 48 and Figure 49 , the outer gate auxiliary turn-off component is composed of a series connection of the outer gate field effect transistor group 21 and the outer gate capacitor group 23, and the inner gate auxiliary turn-off component is composed of the inner gate field effect transistor group 26. Figure 49 In Figure 49 the equivalent circuit diagram shown, the first current port A is the current input port, and the second current port K is the current output port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp is the charging port of the outer gate capacitor group 23, and the potential of the charging port Cp is lower than the potential of the second current port K. The control method of this power semiconductor device can refer to Figure 36 the control timing diagram shown and the corresponding control method for implementation.

[0238] Exemplarily, please refer to Figure 50 and Figure 51 , the outer gate auxiliary turn-off component is composed of a series connection of the outer gate field effect transistor group 21 and the outer gate capacitor group 23, and the inner gate auxiliary turn-off component is composed of a series connection of the inner gate field effect transistor group 26 and the inner gate capacitor group 27. Figure 51 In Figure 51In the equivalent circuit diagram shown, the first current port A is the current input port, and the second current port K is the current output port. The gate G1 is the control gate of the conduction optimization region (i.e., the inner gate 13) for controlling the inner active region 14; the gate G2 is the control gate of the turn-off optimization region (i.e., the outer gate 11) for controlling the outer active region 12; the gate G3 is the control gate of the outer gate field effect transistor group 21; the gate G5 is the control gate of the inner gate field effect transistor group 26. The charging port Cp is the charging port of the outer gate capacitor group 23, and the charging port Cp' is the charging port of the inner gate capacitor group 27. The electric potentials of the charging ports Cp and Cp' are both lower than the electric potential of the second current port K. The control method of this power semiconductor device can refer to Figure 36 the control timing diagram and the corresponding control method shown for implementation.

[0239] In summary, some embodiments of the present disclosure also provide a control method for a power semiconductor device, which can be applied to the power semiconductor devices described in the foregoing some embodiments. The working modes of the power semiconductor device include a turn-on mode and a turn-off mode, and the control method includes the following steps.

[0240] In the turn-on mode, a first control signal is applied to the conduction optimization region, a second control signal is applied to the turn-off optimization region, and a third control signal is applied to the auxiliary turn-off component to provide a first current path in the conduction optimization region and a second current path in the turn-off optimization region.

[0241] In the turn-off mode, a fourth control signal is applied to the conduction optimization region to transfer the current in the conduction optimization region to the turn-off optimization region and the auxiliary turn-off component; a fifth control signal is applied to the auxiliary turn-off component to increase the turn-off current in the turn-off optimization region to assist the turn-off of the turn-off optimization region.

[0242] In some embodiments of the present disclosure, the chip unit includes: an inner active region, an inner gate, an outer active region, and an outer gate. The conduction optimization region includes the inner gate and the inner active region. The turn-off optimization region includes the outer gate and the outer active region. Correspondingly, the first control signal and the fourth control signal are respectively the control signals of the inner gate; the second control signal is the control signal of the outer gate; the third control signal and the fifth control signal are respectively the gate control signals in the auxiliary turn-off component.

[0243] It can be understood that matching different structures of the auxiliary turn-off component, the gate control signals applied in the third control signal and the fifth control signal can be different. The control methods of the corresponding power semiconductor devices can be implemented with reference to the relevant content recorded in the foregoing some embodiments, and will not be elaborated here.

[0244] In addition, by way of example, the operating modes of the power semiconductor device further include a conduction mode and a blocking mode; among them, the turn-on mode refers to the intermediate process from the blocking mode to the conduction mode, and the turn-off mode refers to the intermediate process from the conduction mode to the blocking mode.

[0245] By way of example, the operating modes of the power semiconductor device further include a holding mode. In the holding mode, applying a sixth control signal to the turn-off optimization region does not change the operating mode of the device.

[0246] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0247] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A power semiconductor device, characterized in that: include: Chip unit, including a turn-on optimized area and a turn-off optimized area; The chip unit comprises: an inner active region, an inner gate, an outer active region and an outer gate; the conduction optimization region comprises the inner gate and the inner active region; the turn-off optimization region comprises the outer gate and the outer active region; an auxiliary packaging structure, comprising an auxiliary shutdown component connected to at least the shutdown optimization area; The chip unit is configured to: provide a first current path in the conduction optimization region in an on-mode, provide a second current path in the off-mode optimization region, and transfer the current in the conduction optimization region to the off-mode optimization region and the auxiliary off-component in an off-mode; The auxiliary turn-off component is configured to increase the turn-off current of the turn-off optimization area to assist the turn-off of the turn-off optimization area; the auxiliary turn-off component includes: a gate cathode enhancement turn-off component, a gate electrode enhancement turn-off component, a gate electrode-gate cathode enhancement turn-off component or a gate electrode-gate enhancement turn-off component; Wherein, the gate cathode enhanced turn-off component comprises a gate field effect tube group and a cathode field effect tube group; the first end of the gate field effect tube group is connected to the external gate; the first end of the cathode field effect tube group is connected to the third end of the external active region; the second end of the gate field effect tube group, the second end of the cathode field effect tube group and the third end of the internal active region are connected to form a second current port; Or, the gate cathode enhanced turn-off component includes a gate field effect tube group, a cathode field effect tube group and an auxiliary connection component; the first end of the gate field effect tube group is connected to the external gate, and the first end of the cathode field effect tube group is connected to the third end of the external active region; the second end of the gate field effect tube group, the second end of the cathode field effect tube group and the third end of the internal active region are connected to form a second current port; the auxiliary connection component is connected to the internal gate; Or, the gate cathode enhanced turn-off component includes a gate field effect tube group and a cathode diode group; the first end of the gate field effect tube group is connected to the external gate; the first end of the cathode diode group is connected to the third end of the external active region; the second end of the gate field effect tube group, the second end of the cathode diode group and the third end of the internal active region are connected to form a second current port; Or, the gate cathode enhanced turn-off component includes a gate field effect tube group, a gate capacitor group and a cathode diode group; the gate field effect tube group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field effect tube group and the gate capacitor group is connected to the external gate; the first end of the cathode diode group is connected to the third end of the external active region; the second end of the series branch of the gate field effect tube group and the gate capacitor group, the second end of the cathode diode group and the third end of the internal active region are connected to form a second current port; Or, the gate cathode enhanced turn-off component includes a gate field effect transistor group, a gate capacitor group, a cathode diode group and an auxiliary connection component; the gate field effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field effect transistor group and the gate capacitor group is connected to the external gate; the first end of the cathode diode group is connected to the third end of the external active area; the second end of the series branch of the gate field effect transistor group and the gate capacitor group, the second end of the cathode diode group and the third end of the internal active area are connected to form a second current port; the auxiliary connection component is connected to the internal gate.

2. The power semiconductor device according to claim 1, characterized in that: The inner active region, the inner gate, the outer active region and the outer gate are arranged in a circle from inside to outside along the radial direction of the chip unit; Or, the inner gate, the inner active region, the outer active region and the outer gate are arranged in a circle from inside to outside along the radial direction of the chip unit; Or, the inner active region, the inner gate, the outer gate and the outer active region are arranged in a circle from inside to outside along the radial direction of the chip unit; Alternatively, the inner gate, the inner active region, the outer gate and the outer active region are arranged in a circle from inside to outside along the radial direction of the chip unit.

3. The power semiconductor device according to claim 2, characterized in that: The first end of the inner active region is isolated from the first end of the outer active region, and the second end of the inner active region is connected to the second end of the outer active region to form a first current port.

4. The power semiconductor device according to claim 3, characterized in that: The auxiliary turn-off component is the gate enhancement turn-off component; The gate enhancement turn-off component includes a gate field effect transistor group; wherein the first end of the gate field effect transistor group is connected to the external gate; the second end of the gate field effect transistor group, the third end of the external active region and the third end of the internal active region are connected to form a second current port; Or, the gate enhancement turn-off component includes a gate field effect transistor group and a first auxiliary connection component and / or a second auxiliary connection component; wherein the first end of the gate field effect transistor group is connected to the external gate; the second end of the gate field effect transistor group, the third end of the external active region and the third end of the internal active region are connected to form a second current port; the first auxiliary connection component is used to connect the internal gate; the second auxiliary connection component is used to connect the external active region; Or, the gate enhancement turn-off component includes a gate field effect transistor group and a gate capacitor group; wherein the gate field effect transistor group is connected in series with the gate capacitor group, and a first end of a series branch of the gate field effect transistor group and the gate capacitor group is connected to the external gate, and a second end of the series branch of the gate field effect transistor group and the gate capacitor group, a third end of the external active region, and a third end of the internal active region are connected to form a second current port; Or, the gate enhancement turn-off component includes a gate field effect transistor group, a gate capacitor group and a first auxiliary connection component and / or a second auxiliary connection component; wherein the gate field effect transistor group is connected in series with the gate capacitor group, and the first end of the series branch of the gate field effect transistor group and the gate capacitor group is connected to the external gate, the second end of the series branch of the gate field effect transistor group and the gate capacitor group, the third end of the external active area and the third end of the internal active area are connected to form a second current port; the first auxiliary connection component is used to connect the internal gate; the second auxiliary connection component is used to connect the external active area.

5. The power semiconductor device according to claim 3, characterized in that: The auxiliary shutdown component is the gate-gate cathode enhanced shutdown component; The gate-gate cathode enhanced turn-off component comprises an external gate field effect transistor group, an external cathode field effect transistor group and an internal gate field effect transistor group; wherein the first end of the external gate field effect transistor group is connected to the external gate; the first end of the external cathode field effect transistor group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate; the second end of the external gate field effect transistor group, the second end of the external cathode field effect transistor group, the second end of the internal gate field effect transistor group and the third end of the internal active region are connected to form a second current port; Or, the gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode diode group and an internal gate field effect transistor group; wherein the first end of the external gate field effect transistor group is connected to the external gate; the first end of the external cathode diode group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate; the second end of the external gate field effect transistor group, the second end of the external cathode diode group, the second end of the internal gate field effect transistor group and the third end of the internal active region are connected to form a second current port; Or, the gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode field effect transistor group, an internal gate field effect transistor group and an internal gate capacitor group; wherein the first end of the external gate field effect transistor group is connected to the external gate; the first end of the external cathode field effect transistor group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate; the second end of the internal gate field effect transistor group is connected to the first end of the internal gate capacitor group; the second end of the external gate field effect transistor group, the second end of the external cathode field effect transistor group, the second end of the internal gate capacitor group and the third end of the internal active region are connected to form a second current port; Or, the gate-gate cathode enhanced turn-off component includes: an external gate field effect transistor group, an external cathode diode group, an internal gate field effect transistor group and an internal gate capacitor group; wherein the first end of the external gate field effect transistor group is connected to the external gate; the first end of the external cathode diode group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate; the second end of the internal gate field effect transistor group is connected to the first end of the internal gate capacitor group; the second end of the external gate field effect transistor group, the second end of the external cathode diode group, the second end of the internal gate capacitor group and the third end of the internal active region are connected to form a second current port; Or, the gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode diode group, an external gate capacitor group and an internal gate field effect transistor group; wherein the first end of the external gate field effect transistor group is connected to the external gate, and the second end of the external gate field effect transistor group is connected to the first end of the external gate capacitor group; the first end of the external cathode diode group is connected to the third end of the external active region; the first end of the internal gate field effect transistor group is connected to the internal gate; the second end of the external gate capacitor group, the second end of the external cathode diode group, the second end of the internal gate field effect transistor group and the third end of the internal active region are connected to form a second current port; Or, the gate-gate cathode enhanced turn-off component includes an external gate field effect transistor group, an external cathode diode group, an external gate capacitor group, an internal gate field effect transistor group and an internal gate capacitor group; wherein, the first end of the external gate field effect transistor group is connected to the external gate, and the second end of the external gate field effect transistor group is connected to the first end of the external gate capacitor group; the first end of the external cathode diode group is connected to the third end of the external active area; the first end of the internal gate field effect transistor group is connected to the internal gate, and the second end of the internal gate field effect transistor group is connected to the first end of the internal gate capacitor group; the second end of the external gate capacitor group, the second end of the external cathode diode group, the second end of the internal gate capacitor group, the second end of the internal gate capacitor group and the third end of the internal active area are connected to form a second current port.

6. The power semiconductor device according to claim 3, characterized in that: The auxiliary turn-off component is the gate-gate enhanced turn-off component; The gate-gate enhanced turn-off component includes an external gate auxiliary turn-off component, an internal gate auxiliary turn-off component and an auxiliary connection component arranged between the external gate auxiliary turn-off component and the internal gate auxiliary turn-off component; the auxiliary connection component is used to connect the external active area.

7. The power semiconductor device according to claim 2, characterized in that: The auxiliary packaging structure further includes a first vacant area for exposing at least a portion of the conduction optimization area; the first vacant area is used to accommodate a cathode lead-out electrode of the conduction optimization area.

8. A method for controlling a power semiconductor device, characterized in that: The power semiconductor device comprises a chip unit and an auxiliary packaging structure; the chip unit comprises a conduction optimization region and a shutdown optimization region; the auxiliary packaging structure comprises an auxiliary shutdown component connected to at least the shutdown optimization region; The working mode of the power semiconductor device includes an on mode and an off mode; The control method comprises: In the on-mode, a first control signal is applied to the on-optimized region, a second control signal is applied to the off-optimized region, and a third control signal is applied to the auxiliary off-component, so as to provide a first current path in the on-optimized region and a second current path in the off-optimized region; In the shutdown mode, a fourth control signal is applied to the conduction optimization area to transfer the current of the conduction optimization area to the shutdown optimization area and the auxiliary shutdown component; a fifth control signal is applied to the auxiliary shutdown component to increase the shutdown current of the shutdown optimization area to assist the shutdown of the shutdown optimization area.

9. The control method of a power semiconductor device according to claim 8, characterized in that: The chip unit includes: an inner active region, an inner gate, an outer active region and an outer gate; the conduction optimization region includes the inner gate and the inner active region; the turn-off optimization region includes the outer gate and the outer active region; wherein, The first control signal and the fourth control signal are control signals of the inner gate respectively; The second control signal is a control signal of the external gate; The third control signal and the fifth control signal are respectively gate control signals in the auxiliary turn-off component.

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