A high-reliability infrared light-emitting LED chip and its manufacturing method

Abstract

The present invention relates to the field of LED technology, and more specifically to a high-reliability infrared light-emitting LED chip and a method for manufacturing the same. The chip comprises a back electrode, a silicon substrate, a first bonding layer, a second bonding layer, a current expansion and reflection structure, a functional layer, and an annular contact electrode, arranged sequentially from bottom to top. A light exit hole is provided within the ring of the annular contact electrode. The current expansion and reflection structure comprises a silver nanowire current expansion layer, a dielectric film layer, and a mirror layer. The upper surface of the dielectric film layer has a first groove, and the silver nanowire current expansion layer is embedded in the first groove. The center of the dielectric film layer has a conductive through-hole that passes through the first groove and the second groove. The chip provided in this application improves the chip's luminous intensity while also improving its reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and in particular to a high-reliability infrared light-emitting LED chip and a manufacturing method thereof. Background Art

[0002] Infrared emitting tubes are made of AlGaAs or GaAs PN junctions. When a forward bias current is injected into the PN junction, infrared light is generated. Its spectrum is distributed between 830nm and 950nm. Compared to GaAs, AlGaAs has higher luminous efficiency and greater output light power, enabling long-range emission. They are widely used in fields such as infrared surveillance cameras and infrared night vision devices, providing infrared light sources and helping to obtain clearer images. Due to the demands of distance and scene, higher requirements are placed on the luminous intensity and reliability of infrared LED chips. This invention aims to improve the luminous intensity and reliability of infrared LED chips through structural optimization. Summary of the Invention

[0003] The purpose of the present invention is to provide a high-reliability infrared light-emitting LED chip and a manufacturing method thereof, which can improve the chip's luminous intensity while also improving its reliability.

[0004] In order to solve the above problems, the technical solution provided by the present invention is:

[0005] The present invention provides a high-reliability infrared light-emitting LED chip, which includes a back electrode, a silicon substrate, a first bonding layer, a second bonding layer, a current spreading reflection structure, an AlGaAs light-emitting layer, an AlGaAs roughening layer, an N-type GaAs ohmic contact layer, and an annular contact electrode, which are sequentially arranged from bottom to top. A light-emitting hole is arranged in the ring of the annular contact electrode.

[0006] The current spreading reflection structure comprises a silver nanowire current spreading layer, a dielectric film layer and a mirror layer;

[0007] The upper surface of the dielectric film layer has a first groove, and the silver nanowire current spreading layer is embedded in the first groove; the lower surface of the dielectric film layer has a second groove, and the mirror layer is embedded in the second groove;

[0008] The center of the dielectric film layer has a conductive through-hole that passes through the first groove and the second groove. The conductive through-hole is located directly below the light exit hole. The surface of the mirror layer close to the dielectric film layer has a boss. The boss is completely embedded in the conductive through-hole, and the upper surface of the boss is in contact with the lower surface of the silver nanowire current spreading layer.

[0009] Furthermore, the first groove opens upward, comprises a first bottom surface and first protective walls around it, the upper end surface of the first protective wall is flush with the upper surface of the silver nanowire current spreading layer; the first bottom surface is in contact with the lower surface of the silver nanowire current spreading layer;

[0010] The second groove opens downward and includes a second bottom surface and second protective walls around it. The lower end surface of the second protective wall is flush with the lower surface of the mirror layer; the second bottom surface contacts the upper surface of the mirror layer.

[0011] Furthermore, the first groove occupies 70% to 95% of the area of ​​the dielectric film layer;

[0012] The second groove occupies 70% to 95% of the area of ​​the dielectric film layer.

[0013] Furthermore, the chip has cutting lines on its four sidewalls, and the cutting lines are etched from the upper surface of the chip to the upper surface of the second bonding layer; the chip is also provided with a passivation layer and a front external electrode from the inside to the outside.

[0014] Furthermore, the passivation layer covers the cutting streets and other areas of the upper surface of the chip except the annular contact electrode;

[0015] The material of the passivation layer is SiN, and the thickness of the passivation layer is 1 μm to 2 μm.

[0016] Furthermore, the front external electrode covers the cutting street and other areas of the chip except the light exit hole;

[0017] The front external electrode is made of Ti, Ni, Pd and Au arranged in sequence, and the thickness of the front external electrode is 4 μm to 5 μm.

[0018] Furthermore, the light exit hole is arranged at the center of the upper surface of the chip, and the aperture of the conductive through hole is less than or equal to the aperture of the light exit hole;

[0019] The upper surface of the boss adopts a planar structure, the upper surface of the boss is flush with the upper surface of the dielectric film layer, and the upper surface of the boss is in direct contact with the lower surface of the silver nanowire current spreading layer.

[0020] Furthermore, the N-type GaAs ohmic contact layer is only provided in the area covered by the annular contact electrode.

[0021] Furthermore, the silver nanowire current spreading layer is obtained by spin coating the surface of the functional layer with a silver nanowire liquid as a spin coating liquid and then annealing and curing;

[0022] The diameter of the silver wire used in the silver nanowire liquid is 20nm to 40nm; the length of the silver wire is 10μm to 20μm;

[0023] The silver nanowire concentration in the silver nanowire liquid is 10 mg / ml to 30 mg / ml;

[0024] The solvent in the silver nanowire liquid is isopropyl alcohol.

[0025] The present invention also provides a method for manufacturing the above-mentioned high-reliability infrared light-emitting LED chip, the manufacturing method comprising:

[0026] S1. Providing a GaAs substrate as an epitaxial structure growth substrate, and sequentially growing a sacrificial layer and a functional layer on the GaAs substrate by MOCVD, wherein the functional layer sequentially includes an N-type GaAs ohmic contact layer, an AlGaAs roughening layer, and an AlGaAs light-emitting layer;

[0027] S2, cleaning the epitaxial wafer with an organic cleaning solution, using negative resist photolithography to produce a patterned shape, and using spin coating to produce a silver nanowire current spreading layer on the surface of the functional layer;

[0028] S3, using a negative resist photolithography process to produce an alignment dielectric film pattern, using an optical coating machine to evaporate the dielectric film material, and using a negative resist stripping process to produce a dielectric film layer having a first groove;

[0029] S4, using negative photolithography and dry etching process to etch away the dielectric film material inside the dielectric film layer to form a second groove;

[0030] S5, using a negative photoresist stripping process to deposit a mirror metal material using a metal evaporator, and then stripping the mirror layer built into the second groove;

[0031] S6. Cleaning with an organic cleaning solution and forming a second bonding layer by electron beam evaporation;

[0032] S7, forming a first bonding layer on the surface of the silicon substrate by electron beam evaporation;

[0033] S8, laminating the first bonding layer and the second bonding layer, and placing them on a fixed graphite jig for bonding;

[0034] S9, using chemical etching to remove the GaAs substrate and etch away the sacrificial layer;

[0035] S10, using a negative photoresist to prepare a mask pattern for a ring-shaped contact electrode, and performing a lift-off process to obtain a ring-shaped contact electrode;

[0036] S11, using positive photoresist to form a cutting street mask pattern, and forming a cutting street by dry ICP etching;

[0037] S12, using positive photoresist to prepare a roughening mask pattern, and etching the surface of the light emitting area to form a rough light emitting surface;

[0038] S13, after cleaning the wafer, depositing a passivation layer by PECVD, using a positive photoresist to make a mask pattern, and dry etching away the passivation layer material above the annular contact electrode;

[0039] S14, using a negative photoresist to prepare a mask pattern for a front external electrode, sputtering or electron beam evaporating the front external electrode material, and peeling it off through a lift-off process to obtain the front external electrode;

[0040] S15, thinning the silicon substrate and evaporating a back metal to form a back electrode;

[0041] S16. Cut the wafer into individual chips by laser cutting the front side, blade cutting the back side, and splitting.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. The current-spreading and reflecting structure in this application provides excellent P-side current conduction and light reflection for the chip. The silver nanowire current-spreading layer exhibits excellent current-spreading properties and provides good electrical contact with the mirror layer, forming a P-side current channel. This simplifies the epitaxial structure, creates a highly flat mirror layer, and forms a good light-reflecting interface between the dielectric film and the mirror layer, thereby increasing light output. Furthermore, the improved dielectric film structure integrates the silver nanowire current-spreading layer and the mirror layer into grooves within the dielectric film, further guiding current toward the bottom of the light-emitting aperture and enhancing LED luminous intensity. Furthermore, the silver nanowire current-spreading layer and the mirror layer are built into the structure, providing complete protection around the mirror layer and the silver nanowire current-spreading layer, effectively improving chip reliability and structural stability.

[0044] 2. In this application, the passivation layer and the sidewalls of the cutting path are fully covered with metal. The front external electrode structure has strong corrosion resistance and high hardness, dense structure, high flatness, good wire bonding, and can perform multiple wire bonding operations to avoid water vapor erosion and light leakage in non-light-emitting areas.

[0045] 3. This application utilizes a dielectric film layer to coat the silver nanowire current spreading layer and mirror layer. This allows for a single-step formation during chip etching, preventing contact with the current spreading and mirror layers during the etching process, resulting in a high yield rate. This application also optimizes the chip structure, employing a silver nanowire current spreading layer with excellent bending properties, allowing for coating fabrication. This process is simple to operate and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0047] Figure 1 This is a schematic diagram of the structure of a high-reliability infrared light-emitting LED chip shown in some embodiments of the present application;

[0048] Figure 2 This is a schematic structural diagram of a high-reliability infrared light-emitting LED chip from another perspective shown in some embodiments of the present application;

[0049] Figure 3 This is a schematic diagram of a high-reliability infrared light-emitting LED epitaxial structure shown in some embodiments of the present application;

[0050] Figure 4 This is a schematic diagram of a structure in which a dielectric film layer and a conductive through-hole are formed on a high-reliability infrared light-emitting LED epitaxial structure according to some embodiments of the present application;

[0051] Figure 5 This is a schematic structural diagram from another perspective of forming a dielectric film layer and conductive vias on a high-reliability infrared light-emitting LED epitaxial structure according to some embodiments of the present application;

[0052] Figure 6 This is a schematic diagram of the structure of a high-reliability infrared light-emitting LED epitaxial structure bonded to a silicon substrate according to some embodiments of the present application;

[0053] Description of the drawings: 1. GaAs substrate; 2. Sacrificial layer; 3. Functional layer; 4. Current spreading reflection structure; 5. Front external electrode; 6. Silicon substrate; 7. First bonding layer; 8. Second bonding layer; 9. Ring contact electrode; 10. Passivation layer; 11. Back electrode; 12. Light output hole; 41. Silver nanowire current spreading layer; 42. Dielectric film layer; 43. Mirror layer; 44. First groove; 45. Second groove; 46. Conductive through hole; 431. Boss; 441. First bottom surface; 442. First protective wall; 451. Second bottom surface; 452. Second protective wall; 31. AlGaAs light-emitting layer; 32. AlGaAs roughening layer; 33. N-type GaAs ohmic contact layer. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0055] Unless otherwise specifically stated, the relative arrangement of the parts and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0056] In the description of this application, it should be understood that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0057] In the description of this application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of this application; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0058] The present application is further described in detail below with reference to specific embodiments:

[0059] Example 1

[0060] The high reliability infrared LED chip provided in this embodiment is an AlGaAs series infrared LED chip structure, which can be applied to infrared surveillance cameras, infrared night vision devices and other infrared LED chips with strong luminous brightness and emission distance requirements. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a high-reliability infrared light-emitting LED chip shown in some embodiments of this application. Figure 2 Schematic diagram of the structure of a high-reliability infrared light-emitting LED chip from another perspective shown in some embodiments of the present application; the chip includes, arranged from bottom to top, a back electrode 11, a silicon substrate 6, a first bonding layer 7, a second bonding layer 8, a current spreading and reflecting structure 4, an AlGaAs light-emitting layer 31, an AlGaAs roughened layer 32, an N-type GaAs ohmic contact layer 33 (the AlGaAs light-emitting layer 31, the AlGaAs roughened layer 32, and the N-type GaAs ohmic contact layer 33 constitute the infrared light-emitting LED functional layer 3), and an annular contact electrode 9. A light exit hole 12 is provided within the ring of the annular contact electrode 9. The current spreading and reflecting structure 4 includes a silver nanowire current spreading layer 41, a dielectric film layer 42, and a mirror layer 43. The upper surface of the dielectric film layer 42 has a first groove 44, and the silver nanowire current spreading layer 41 is embedded in the first groove 44; the lower surface of the dielectric film layer 42 has a second groove 45, and the mirror layer 43 is embedded in the second groove 45; the center of the dielectric film layer 42 has a conductive through-hole 46 that passes through the first groove 44 and the second groove 45, and the conductive through-hole 46 is located directly below the light output hole 12. The surface of the mirror layer 43 close to the dielectric film layer 42 has a boss 431, and the boss 431 is completely embedded in the conductive through-hole 46, and the upper surface of the boss 431 is in contact with the lower surface of the silver nanowire current spreading layer 41.

[0061] The infrared light-emitting LED chip provided in this application provides good P-side current conduction and light reflection for the chip by adopting a current expansion reflection structure 4. The silver nanowire current expansion layer 41 has a good current expansion effect and good electrical contact with the mirror layer 43, which can form a P-side current channel, simplifying the epitaxial structure. The mirror layer 43 has high flatness, and a good light reflection interface is formed between the dielectric film layer 42 and the mirror layer 43 to increase light emission. In addition, the improved dielectric film layer 42 structure integrates the silver nanowire current expansion layer 41 and the mirror layer 43 into the groove on the dielectric film layer 42, which can further guide the current to converge below the light output hole 12, thereby improving the LED luminous intensity. It also achieves the effect of internalizing the silver nanowire current expansion layer 41 and the mirror layer 43, providing complete wrapping and protection for the mirror layer 43 and the silver nanowire current expansion layer 41 structure, effectively improving the reliability and structural stability of the chip.

[0062] As a preferred embodiment, the structures of the first groove 44 and the second groove 45 are further limited. Specifically, please combine Figure 1 The first groove 44 opens upward and includes a first bottom surface 441 and surrounding first protective walls 442. The upper end surface of the first protective wall 442 is flush with the upper surface of the silver nanowire current spreading layer 41; the first bottom surface 441 contacts the lower surface of the silver nanowire current spreading layer 41; the second groove 45 opens downward and includes a second bottom surface 451 and surrounding second protective walls 452. The lower end surface of the second protective wall 452 is flush with the lower surface of the mirror layer 43; the second bottom surface 451 contacts the upper surface of the mirror layer 43. This ensures chip flatness and facilitates fabrication.

[0063] In a preferred embodiment, both the first groove 44 and the second groove 45 are disposed in the center of the dielectric film layer 42 , with the first groove 44 occupying 70% to 95% of the area of ​​the dielectric film layer 42 . This ensures a certain current spreading effect and allows the first protective wall 442 of the first groove 44 to have a certain thickness, thereby effectively covering the silver nanowire current spreading layer 41 therein. Specifically, for example, the first groove 44 occupies 80%, 85%, 90%, or 95% of the area of ​​the dielectric film layer 42 . The shape of the first groove 44 can be the same as that of the dielectric film layer 42 , with the center of the first groove 44 coinciding with the center of the dielectric film layer 42 , such that the thickness of the first protective wall 442 is substantially the same. The second groove 45 occupies 70% to 95% of the area of ​​the dielectric film layer 42 . The structure of the second groove 45 is similar to that of the first groove 44. The difference is that the mirror layer 43 in the second groove 45 is more susceptible to damage by external forces. Therefore, the second groove 45 with the above structure can reduce the damage to the mirror layer 43 during the subsequent cutting process, thereby improving the production yield.

[0064] It should be noted that the percentage of the area of ​​the dielectric film layer 42 occupied by the above-mentioned first groove 44 and second groove 45 is based on the area of ​​the dielectric film layer 42 (including the conductive through hole 46) on the finished chip; before the cutting path is produced, considering that the subsequent cutting path production will etch away a portion of the material at the edge of the dielectric film layer 42, it is necessary to calculate and reserve the loss of the dielectric film layer 42 in the production of the cutting path.

[0065] As a preferred embodiment, the chip has cutting lines on its four sidewalls, which are etched from the upper surface of the chip to the upper surface of the second bonding layer 8; the chip is also provided with a passivation layer 10 and a front external electrode 5 from the inside to the outside.

[0066] The passivation layer 10 of the present application can adopt conventional passivation materials and structures. As a preferred embodiment, the passivation layer 10 covers the cutting path and other areas of the chip surface except the annular contact electrode 9; the material of the passivation layer 10 is SiN, and the thickness of the passivation layer 10 is 1μm to 2μm.

[0067] As a preferred embodiment, the front external electrode 5 covers the scribe line and all other chip areas except the light exit aperture 12. The materials for the front external electrode 5 are Ti, Ni, Pd, and Au, arranged in that order, and the thickness of the front external electrode 5 is 4 to 5 μm. The passivation layer 10 and the sidewalls of the scribe line are fully covered with metal. The front external electrode 5 has a strong corrosion resistance and high hardness, a dense structure, high flatness, and good wire bonding performance. Multiple wire bonding operations are possible, preventing moisture erosion and light leakage in non-light-exiting areas.

[0068] As a preferred embodiment, the light exit hole 12 is arranged at the center of the upper surface of the chip; in this way, the surrounding area of ​​the light exit hole 12 can be used as a wire bonding area (the wire bonding process can be carried out in a conventional manner and will not be described in detail here). In particular, when used with high current, multiple wire bonds can be formed and evenly distributed around the light exit hole 12, which can be better used in high current scenarios. The aperture of the conductive through hole 46 is ≤ the aperture of the light exit hole 12; the upper surface of the boss 431 adopts a planar structure, the upper surface of the boss 431 is flush with the upper surface of the dielectric film layer 42, and the upper and lower surfaces of the silver nanowire current spreading layer 41 are planar, which can ensure the flatness of the upper surface of the boss 431, the chip structure has high flatness, and the interface between the boss 421 and the silver nanowire current spreading layer 41 can have a certain light reflection effect, thereby increasing the probability of light emission; and the upper surface of the boss 431 is in direct contact with the lower surface of the silver nanowire current spreading layer 41. The current channel formed by the pattern of the dielectric film layer 42 is located directly below the light emitting area, allowing the electrons and holes in the functional layer 3 to recombine directly below the light emitting area, thereby increasing the probability of light emission.

[0069] As a preferred embodiment, the N-type GaAs ohmic contact layer 33 is only provided in the area covered by the annular contact electrode 9 .

[0070] In a preferred embodiment, the silver nanowire current spreading layer 41 is formed by spin-coating a silver nanowire liquid onto the surface of the functional layer 3 and then annealing and curing. The silver wires used in the silver nanowire liquid have a diameter of 20 nm to 40 nm, a length of 10 μm to 20 μm, a silver concentration of 10 mg / ml to 30 mg / ml, and the solvent used isopropyl alcohol. Silver nanowires have excellent light transmittance due to their nanoscale size effect. As a transparent conductive material, they reduce the need for epitaxial layer material and simplify epitaxial material growth. Silver nanowires can be produced by coating, which is cost-effective.

[0071] As can be seen from the above, the high-reliability infrared LED chip provided in the embodiments of the present application has the following advantages:

[0072] 1. The current-spreading and reflective structure employed in this application provides excellent P-side current conduction and light reflection for the chip. The silver nanowire current-spreading layer exhibits excellent current-spreading properties and maintains good electrical contact with the mirror layer, forming a P-side current channel. This simplifies the epitaxial structure, creates a highly flat mirror layer, and forms a favorable light-reflecting interface between the dielectric film and the mirror layer, enhancing light output. Furthermore, the improved dielectric film structure integrates the silver nanowire current-spreading layer and the mirror layer into grooves within the dielectric film, further guiding current toward the lower portion of the light-emitting aperture and enhancing LED luminous intensity. Furthermore, the silver nanowire current-spreading layer and the mirror layer are integrated into the chip, providing a complete protective wrapping around the mirror layer and silver nanowire current-spreading layer structure, effectively improving chip reliability and structural stability.

[0073] 2. In this application, the passivation layer and the sidewalls of the cutting path are fully covered with metal. The front external electrode structure has strong corrosion resistance and high hardness, dense structure, high flatness, good wire bonding, and can perform multiple wire bonding operations to avoid water vapor erosion and light leakage in non-light-emitting areas.

[0074] Example 2

[0075] Please combine Figures 1 to 6 This embodiment provides a method for manufacturing a high-reliability infrared light-emitting LED chip, the manufacturing method comprising the following steps:

[0076] Step 1: Please combine Figure 3 , Figure 3Schematic diagram of a high-reliability infrared light-emitting LED epitaxial structure according to some embodiments of the present application. Specifically, a GaAs substrate 1 is provided as a substrate for epitaxial structure growth. On the GaAs substrate 1, a MOCVD machine is set up and a sacrificial layer 2 and a functional layer 3 are sequentially grown on the GaAs substrate 1. The sacrificial layer 2 sequentially includes an n-GaAs buffer layer and a GaInP etching stop layer. The functional layer 3 sequentially includes an N-type GaAs ohmic contact layer 33, an AlGaAs roughening layer 32, and an AlGaAs light-emitting layer 31.

[0077] Please combine the following steps 2 to 4 Figure 4 and Figure 5 ,in, Figure 4 This is a schematic diagram of a structure in which a dielectric film layer and a conductive through-hole are formed on a high-reliability infrared light-emitting LED epitaxial structure according to some embodiments of the present application; Figure 5 This is a schematic structural diagram from another perspective of forming a dielectric film layer and conductive vias on a high-reliability infrared light-emitting LED epitaxial structure according to some embodiments of the present application;

[0078] Step 2: Clean the epitaxial wafer with an organic cleaning solution, use negative photolithography to form a patterned shape of the silver nanowire current spreading layer 41, and use a spin coating method to form the silver nanowire current spreading layer 41 on the surface of the functional layer 3; as a preferred embodiment, the specific method for forming the silver nanowire current spreading layer 41 is to clean the epitaxial wafer with an organic cleaning solution, use a spin coating method, first spin coat the surface of the epitaxial wafer at a speed of 1200 r / s for 10 seconds, then spin coat the surface of the epitaxial wafer at a speed of 2000 r / s for 30 seconds, and anneal and cure in a nitrogen-filled furnace at an annealing temperature of 180° C. and an annealing time of 30 minutes. The spin coating liquid is a silver nanowire liquid containing a volatile solvent, and the negative photoresist is removed after annealing and curing;

[0079] Step 3: Using a negative resist photolithography process, an alignment dielectric film pattern is formed. The dielectric film material is evaporated using an optical coating machine, and then subjected to a negative resist stripping process to form a dielectric film layer 42 having a first groove 44. In a preferred embodiment, the dielectric film layer 42 is made of magnesium fluoride with a thickness of 6000 angstroms to 8000 angstroms.

[0080] Step 4: using negative photolithography and dry etching to etch away the dielectric film material inside the dielectric film layer 42 to form a second groove 45 , with the etching depth being based on the thickness of the mirror layer 43 to be evaporated;

[0081] Please combine the following steps 5 to 8 Figure 6 , Figure 6 This is a schematic diagram of the structure of a high-reliability infrared light-emitting LED epitaxial structure bonded to a silicon substrate according to some embodiments of the present application;

[0082] Step 5: Using a negative photoresist stripping process, a mirror metal material is deposited using a metal evaporator, and then stripped to obtain a mirror layer 43 embedded in the second groove 45. In a preferred embodiment, the mirror metal material is selected from Au or Ag, and the thickness of the mirror layer 43 is 3000 angstroms to 5000 angstroms.

[0083] Step 6: Clean with an organic cleaning solution and form a second bonding layer 8 by electron beam evaporation. The second bonding layer 8 is preferably made of Au with a thickness of 6000 angstroms to 10000 angstroms.

[0084] Step 7: After the newly removed silicon substrate 6 is cleaned with an organic solvent or acid or alkali, a first bonding layer 7 is formed by electron beam evaporation. As a preferred embodiment, the material for preparing the first bonding layer 7 is preferably Au, and its thickness is 6000 angstroms to 10000 angstroms.

[0085] Step 8: Immerse the product with the first bonding layer 7 and the product with the second bonding layer 8 in an organic solvent for cleaning. After cleaning and baking, the first bonding layer 7 and the second bonding layer 8 are placed relative to each other and placed in a fixed graphite jig. Under high temperature and high pressure, the two are bonded together for 30 minutes;

[0086] Please combine the following steps 9 to 16 Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a high-reliability infrared light-emitting LED chip shown in some embodiments of the present application; Figure 2 This is a schematic structural diagram of a high-reliability infrared light-emitting LED chip from another perspective shown in some embodiments of the present application;

[0087] Step 9: Remove the GaAs substrate 1 by chemical etching. The chemical etching solution is a mixture of ammonia and hydrogen peroxide. Observe the etching process until it is completely etched away. Then, use a mixture of hydrochloric acid and phosphoric acid to etch away the sacrificial layer 2.

[0088] Step 10: Using a negative photoresist, a mask pattern for the annular contact electrode 9 is formed. The mask pattern and the conductive via 46 pattern are overlapped with each other, and the annular contact electrode 9 is obtained by a lift-off process. The annular contact electrode 9 is then immersed in a mixed solution of phosphoric acid, hydrogen peroxide, and water to etch away the N-type GaAs ohmic contact layer 33 material outside the annular contact electrode 9.

[0089] Step 11: Use positive photoresist to make a cutting mask pattern, and use dry ICP etching to make cutting streets; use positive photoresist to make a cutting mask pattern, and use dry ICP etching to etch to the upper surface of the second bonding layer 8 to make cutting streets; the dry ICP etching power is 500W, the BCl3 flow rate is 25 sccm, the Cl2 flow rate is 5 sccm, and the N2 flow rate is 30 sccm;

[0090] Step 12: Use positive photoresist to make a roughening mask pattern, and use a mixture of nitric acid and water to etch the surface of the light-emitting area to form a rough light-emitting surface;

[0091] Step 13: After cleaning the wafer, a passivation layer 10 is deposited by PECVD. A positive photoresist is used to prepare a mask pattern, and the passivation layer 10 material above the annular contact electrode 9 is removed by dry etching. As a preferred embodiment, the passivation material is SiN, the thickness of the passivation layer 10 is 1.5 μm, and the deposition temperature of the passivation layer 10 is 260° C.

[0092] Step 14: Using a negative photoresist to prepare a mask pattern for the front external electrode 5, sputtering or electron beam evaporating the material of the front external electrode 5, and then stripping it off by a lift-off process to obtain the front external electrode 5. As a preferred embodiment, the materials for preparing the front external electrode 5 include Ti, Ni, Pd and Au arranged in sequence, and the thickness of the front external electrode 5 is 4 μm to 5 μm.

[0093] Step 15: Grind the silicon substrate 6 to a thickness of 180 μm, evaporate a back metal, and sequentially arrange Ti, Pt, and Au on the back metal, and perform high-temperature annealing at 320° C. to form a back electrode 11;

[0094] Step 16: Use laser cutting on the front side, blade cutting on the back side and splitting to cut the wafer into individual chips.

[0095] As can be seen from the above, the method for manufacturing a high-reliability infrared LED chip provided in the embodiments of the present application has the following advantages:

[0096] 1. This application utilizes a dielectric film layer to coat the silver nanowire current spreading layer and mirror layer. This allows for one-step formation during chip etching. The etching process does not contact the current spreading layer and mirror layer, resulting in a high yield rate.

[0097] 2. This application optimizes the chip structure and uses a silver nanowire current expansion layer with good bending performance. It can be manufactured by coating, and the preparation process is easy to operate and the production cost is low.

[0098] 3. Since the method for manufacturing the high-reliability infrared light-emitting LED chip provided in the embodiment of the present application obtains the high-reliability infrared light-emitting LED chip in the above-mentioned embodiment 1, it also has the advantages of the high-reliability infrared light-emitting LED chip in the above-mentioned embodiment 1, which will not be elaborated here.

[0099] For matters not described in this embodiment, please refer to the relevant description in the rest of this application.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to preferred embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present application can still be modified or some technical features can be replaced by equivalents, which should all be included in the scope of the technical solutions requested for protection in this application.

Claims

1. A high-reliability infrared light-emitting LED chip, characterized in that: The chip includes a back electrode, a silicon substrate, a first bonding layer, a second bonding layer, a current spreading reflection structure, an AlGaAs light-emitting layer, an AlGaAs roughening layer, an N-type GaAs ohmic contact layer and an annular contact electrode, which are arranged in sequence from bottom to top. A light exit hole is arranged in the ring of the annular contact electrode. The current spreading reflection structure comprises a silver nanowire current spreading layer, a dielectric film layer and a mirror layer; The upper surface of the dielectric film layer has a first groove, and the silver nanowire current spreading layer is embedded in the first groove; the lower surface of the dielectric film layer has a second groove, and the mirror layer is embedded in the second groove; The dielectric film layer has a conductive through hole at its center that passes through the first groove and the second groove. The conductive through hole is located directly below the light exit hole. The mirror layer has a boss on its surface close to the dielectric film layer. The boss is completely embedded in the conductive through hole, and the upper surface of the boss contacts the lower surface of the silver nanowire current spreading layer. The first groove opens upward, comprises a first bottom surface and first protective walls around it, the upper end surface of the first protective wall is flush with the upper surface of the silver nanowire current spreading layer; the first bottom surface is in contact with the lower surface of the silver nanowire current spreading layer; The second groove opens downward and includes a second bottom surface and second protective walls around it. The lower end surface of the second protective wall is flush with the lower surface of the mirror layer; the second bottom surface contacts the upper surface of the mirror layer.

2. A high-reliability infrared LED chip according to claim 1, characterized in that: The first groove occupies 70% to 95% of the area of ​​the dielectric film layer; The second groove occupies 70% to 95% of the area of ​​the dielectric film layer.

3. The high-reliability infrared LED chip according to claim 1, characterized in that: The chip has cutting paths on its four sidewalls, and the cutting paths are etched from the upper surface of the chip to the upper surface of the second bonding layer; the chip is also provided with a passivation layer and a front external electrode from the inside to the outside.

4. A high-reliability infrared LED chip according to claim 3, characterized in that: The passivation layer covers the cutting street and other areas of the upper surface of the chip except the annular contact electrode; The material of the passivation layer is SiN, and the thickness of the passivation layer is 1 μm to 2 μm.

5. A high-reliability infrared light-emitting LED chip according to claim 3 or 4, characterized in that: The front external electrode covers the cutting street and other areas of the chip except the light exit hole; The front external electrode is made of Ti, Ni, Pd and Au arranged in sequence, and the thickness of the front external electrode is 4 μm to 5 μm.

6. The high-reliability infrared LED chip according to claim 1, characterized in that: The light exit hole is arranged at the center of the upper surface of the chip, and the aperture of the conductive through hole is less than or equal to the aperture of the light exit hole; The upper surface of the boss adopts a planar structure, the upper surface of the boss is flush with the upper surface of the dielectric film layer, and the upper surface of the boss is in direct contact with the lower surface of the silver nanowire current spreading layer.

7. The high-reliability infrared LED chip according to claim 1, characterized in that: The N-type GaAs ohmic contact layer is only provided in the area covered by the annular contact electrode.

8. The high-reliability infrared LED chip according to claim 1, characterized in that: The silver nanowire current spreading layer is obtained by spin coating the surface of the functional layer with a silver nanowire liquid as a spin coating liquid and then annealing and curing; The diameter of the silver wire used in the silver nanowire liquid is 20nm to 40nm; the length of the silver wire is 10μm to 20μm; The silver nanowire concentration in the silver nanowire liquid is 10 mg / ml to 30 mg / ml; The solvent in the silver nanowire liquid is isopropyl alcohol.

9. A method for manufacturing a high-reliability infrared light-emitting LED chip according to any one of claims 1 to 8, characterized in that: The production method comprises: S1. Providing a GaAs substrate as an epitaxial structure growth substrate, and sequentially growing a sacrificial layer and a functional layer on the GaAs substrate by MOCVD, wherein the functional layer sequentially includes an N-type GaAs ohmic contact layer, an AlGaAs roughening layer, and an AlGaAs light-emitting layer; S2, cleaning the epitaxial wafer with an organic cleaning solution, using negative resist photolithography to produce a patterned shape, and using spin coating to produce a silver nanowire current spreading layer on the surface of the functional layer; S3, using a negative resist photolithography process to produce an alignment dielectric film pattern, using an optical coating machine to evaporate the dielectric film material, and using a negative resist stripping process to produce a dielectric film layer having a first groove; S4, using negative photolithography and dry etching process to etch away the dielectric film material inside the dielectric film layer to form a second groove; S5, using a negative photoresist stripping process to deposit a mirror metal material using a metal evaporator, and then stripping the mirror layer built into the second groove; S6. Cleaning with an organic cleaning solution and forming a second bonding layer by electron beam evaporation; S7, forming a first bonding layer on the surface of the silicon substrate by electron beam evaporation; S8, laminating the first bonding layer and the second bonding layer, and placing them on a fixed graphite jig for bonding; S9, using chemical etching to remove the GaAs substrate and etch away the sacrificial layer; S10, using a negative photoresist to make a mask pattern for the ring-shaped contact electrode, and performing a stripping process to obtain the ring-shaped contact electrode; S11, using positive photoresist to form a cutting street mask pattern, and forming a cutting street by dry ICP etching; S12, using positive photoresist to prepare a roughening mask pattern, and etching the surface of the light emitting area to form a rough light emitting surface; S13, after cleaning the wafer, depositing a passivation layer by PECVD, using a positive photoresist to make a mask pattern, and dry etching away the passivation layer material above the annular contact electrode; S14, using a negative photoresist to prepare a mask pattern for a front external electrode, sputtering or electron beam evaporating a front external electrode material, and stripping it off using a stripping process to obtain a front external electrode; S15, thinning the silicon substrate and evaporating a back metal to form a back electrode; S16. Cut the wafer into individual chips by laser cutting the front side, blade cutting the back side, and splitting.

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