A chip capacitor quality detection method and system

Abstract

The present invention discloses a chip capacitor quality detection method and system, which belong to the field of electrical performance testing. The present invention substitutes acquired signal information of a transmission test signal and signal information of a reception signal into a denoising performance evaluation model to evaluate the denoising performance, substitutes acquired signal information of the transmission test signal and signal information of the reception signal into an interception performance evaluation model to calculate interception performance abnormal values, substitutes the calculated denoising performance abnormal values ​​and interception performance abnormal values ​​into a quality analysis model to perform quality analysis of the chip capacitor, performs a quality warning of the patch capacitor according to the quality analysis result of the patch capacitor, comprehensively analyzes the overall quality of the patch capacitor based on the removal of noise information and the distortion of interception information, and improves the analysis efficiency and accuracy of the overall quality of the patch capacitor.

Description

Technical Field

[0001] The invention belongs to the field of electrical performance testing, and specifically relates to a chip capacitor quality detection method and system. Background Art

[0002] The main function of chip capacitors is to store charge and regulate current in the circuit. The specific functions include: Filtering: chip capacitors can be used in the circuit to filter out unnecessary high-frequency signals to ensure stable operation of the circuit; Coupling: chip capacitors are used to transmit or couple signals between two circuit stages or components; 3. Protection: chip capacitors can be used to eliminate noise, interference and stabilize voltage in the circuit; The working principle of chip capacitors is mainly based on its capacitance characteristics. When voltage is applied between ports, chip capacitors will store charge and release or absorb these charges when the voltage changes, so that stable current regulation and signal transmission can be achieved in the circuit, thereby ensuring the normal operation of the circuit. The size and characteristics of chip capacitors will affect their ability to store charge and transmit signals, so when selecting, they need to be selected according to specific circuit requirements;

[0003] After the chip capacitors are produced, their electrical characteristics need to be quality tested. However, the existing technology cannot comprehensively analyze the overall quality of the chip capacitors by comprehensively analyzing the removal of noise information and the distortion of intercepted information, resulting in low analysis efficiency and accuracy of the overall quality of the chip capacitors. The above problems exist in the existing technologies.

[0004] For example, a Chinese patent with the authorization publication number CN113884833B discloses a system and method for detecting capacitor welding quality, which realizes automatic detection of capacitor welding quality through tooling procedures in the production test link, greatly improving the accuracy and efficiency of detection. The system for detecting capacitor welding quality of the present invention includes an impedance detection unit and a control management unit. The circuit board is connected to the impedance detection unit and the control management unit respectively. The impedance detection unit corrects the average discharge time through the corresponding correction coefficient to obtain the corrected corresponding reference discharge time. The control management unit is used to monitor the discharge time of each capacitor of the circuit board to obtain the actual discharge time of each capacitor; then the actual discharge time of each capacitor is compared with the reference discharge time of each capacitor.

[0005] The corresponding reference discharge time is compared, and the capacitor welding condition is determined according to the comparison result. The present invention is suitable for detecting capacitors welded on circuit boards;

[0006] The above patents all have the problems raised by this background technology: the prior art is unable to comprehensively analyze the overall quality of the chip capacitors based on the removal of noise information and the distortion of intercepted information, resulting in low analysis efficiency and accuracy of the overall quality of the chip capacitors. In order to solve these problems, this application designs a chip capacitor quality detection method and system. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention proposes a chip capacitor quality detection method and system. The present invention installs a chip capacitor to be tested on a test circuit, a signal transmitting end of the test circuit continuously transmits a test signal for a set time period, a signal receiving end of the test circuit receives a received signal passing through the chip capacitor, and substitutes the acquired signal information of the transmitted test signal and the signal information of the received signal into a denoising performance evaluation model to perform denoising performance evaluation, substitutes the acquired signal information of the transmitted test signal and the signal information of the received signal into an interception performance evaluation model to calculate the interception performance outlier value, substitutes the calculated denoising performance outlier value and the interception performance outlier value into a quality analysis model to perform quality analysis of the chip capacitor, performs a quality warning of the patch capacitor according to the quality analysis result of the patch capacitor, and comprehensively analyzes the overall quality of the patch capacitor based on the removal of noise information and the distortion of interception information, thereby improving the analysis efficiency and accuracy of the overall quality of the patch capacitor.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A method for detecting the quality of a chip capacitor comprises the following specific steps:

[0010] The chip capacitor to be tested is installed on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set period of time, and the signal receiving end of the test circuit receives the receiving signal passing through the chip capacitor;

[0011] Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation model to evaluate the denoising performance;

[0012] Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to perform interception performance evaluation;

[0013] Substitute the obtained denoising performance evaluation results and interception performance evaluation results into the quality analysis model to perform quality analysis on the chip capacitors;

[0014] Provide quality warning of SMD capacitors based on the quality analysis results of SMD capacitors.

[0015] It should be specifically explained here that the step of installing the chip capacitor to be tested on the test circuit, the signal transmitting end of the test circuit continuously transmitting the test signal for a set period of time, and the signal receiving end of the test circuit receiving the received signal passing through the chip capacitor includes the following specific steps:

[0016] S11, obtaining the rated cutoff frequency of the capacitor to be tested when it works on the test circuit, and installing the capacitor to be tested between the signal transmitting end and the signal receiving end on the test circuit;

[0017] S12, the signal transmitting end of the test circuit simultaneously transmits a high-frequency signal of a set strength at least 5% higher than the rated cut-off frequency and a low-frequency signal of a set strength at least 20% lower than the rated cut-off frequency to the signal receiving end, obtains a waveform diagram of the high-frequency signal of the set strength, set as the first waveform diagram, obtains a low-frequency signal of the set strength, set as the second waveform diagram, and the output signals of the two signals after passing through the chip capacitor are received by the signal receiving end of the test circuit. It should be noted here that the low frequency and high frequency here are relative to the rated cut-off frequency;

[0018] S13. The signal output received by the signal receiving end of the tested circuit is subjected to frequency signal separation to obtain a corresponding waveform of the high-frequency signal waveform of the set strength after passing through the chip capacitor, which is set as the third waveform. Meanwhile, a corresponding waveform of the low-frequency signal waveform of the set strength after passing through the chip capacitor is obtained, which is set as the fourth waveform.

[0019] It should be specifically explained here that the step of substituting the acquired signal information of the transmitted test signal and the received signal information into the denoising performance evaluation model to perform denoising performance evaluation includes the following specific contents:

[0020] The first waveform and the third waveform obtained by the acquisition are obtained, and the signal amplitude data on the first waveform and the signal amplitude data on the third waveform are substituted into the denoising performance abnormal value calculation formula to calculate the denoising performance abnormal value, wherein the denoising performance abnormal value calculation formula is: Where T is the test duration, dt is the time integral, and t z is the set time standard value, D 1t is the amplitude value of the waveform signal at time t on the first waveform diagram, where D 2t is the amplitude value of the waveform signal at time t on the third waveform diagram.

[0021] It should be noted here that the removal of high-frequency signals through the chip capacitors is comprehensively analyzed, thereby improving the detection effect of the chip capacitor denoising performance.

[0022] It should be specifically explained here that the step of substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to perform interception performance evaluation includes the following specific steps:

[0023] S31, obtaining the obtained second waveform and the fourth waveform, substituting the obtained signal amplitude data on the second waveform and the obtained signal amplitude data on the fourth waveform into the first distortion abnormality coefficient calculation formula to calculate the first distortion abnormality coefficient, wherein the first distortion abnormality coefficient calculation formula is: Among them, D 3t is the amplitude value of the waveform signal at time t on the second waveform diagram, D 4t is the amplitude value of the waveform signal at time t on the fourth waveform diagram;

[0024] S32, substituting the obtained signal amplitude data of the second waveform and the fourth waveform into the second distortion abnormality coefficient calculation formula to calculate the second distortion abnormality coefficient, wherein the second distortion abnormality coefficient calculation formula is: Among them, exp() is the power of e, is the set signal amplitude interference value;

[0025] S33, obtaining the calculated first distortion abnormality coefficient and the second distortion abnormality coefficient and substituting them into the interception performance abnormality value calculation formula to calculate the interception performance abnormality value, the interception performance abnormality value calculation formula is: Among them, a1 is the proportion of the first distortion abnormality coefficient, a2 is the proportion of the second distortion abnormality coefficient, and a1+a2=1.

[0026] It should be specifically explained here that the step of substituting the denoising performance evaluation results and the interception performance evaluation results obtained by evaluation into the quality analysis model to perform the quality analysis of the chip capacitor includes the following specific steps:

[0027] S41. Obtain the calculated denoising performance outlier value and interception performance outlier value, substitute the denoising performance outlier value and the interception performance outlier value into the quality analysis value calculation formula to calculate the quality analysis value, wherein the quality analysis value calculation formula is: Q = Qmax(1-β1kjz1-β2kjz2), wherein β1 is the denoising performance outlier value ratio coefficient, β2 is the interception performance outlier value ratio coefficient, Q max is the maximum value of the set mass analysis value; it should be noted that the maximum value of the mass analysis value here is set according to the user's interest, preferably 100;

[0028] S42. Compare the calculated quality analysis value with the set quality analysis standard value. If the obtained quality analysis value is greater than or equal to the set quality analysis standard value, it means that the quality of the chip capacitor is qualified. If the obtained quality analysis value is less than the set quality analysis standard value, it means that the quality of the chip capacitor is unqualified.

[0029] It should be specifically explained here that the specific content of the quality warning of the SMD capacitor based on the quality analysis result of the SMD capacitor is as follows:

[0030] If the test result of the chip capacitor indicating that the quality is unqualified is obtained, an early warning of the unqualified quality of the chip capacitor will be issued to the management personnel.

[0031] It should be noted here that the quality analysis standard value, the first distortion abnormality coefficient ratio, the second distortion abnormality coefficient ratio, the interception performance abnormality value ratio coefficient and the denoising performance abnormality value ratio coefficient are obtained as follows: the signal information of the transmitted test signal and the signal information of the received signal in the process of several groups of chip capacitor experiments are obtained, and the signal information of the transmitted test signal and the signal information of the received signal are manually judged whether the chip capacitor is a product of unqualified quality, and the signal information of the transmitted test signal and the signal information of the received signal are substituted into the quality analysis value calculation formula to calculate the quality analysis value, and the calculated quality analysis value and the judgment result are imported into the fitting software, and the optimal quality analysis standard value, the first distortion abnormality coefficient ratio, the second distortion abnormality coefficient ratio, the interception performance abnormality value ratio coefficient and the denoising performance abnormality value ratio coefficient that meet the judgment accuracy are output.

[0032] A chip capacitor quality detection system is implemented based on the above-mentioned chip capacitor quality detection method, and specifically includes a signal acquisition module, a denoising performance outlier value calculation module, a retention performance outlier value calculation module, a quality analysis module, a quality warning module and a control module, wherein the signal acquisition module is used to install the chip capacitor to be tested on a test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set time period, and the signal receiving end of the test circuit receives the received signal passing through the chip capacitor, and the denoising performance outlier value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation model to perform denoising performance evaluation.

[0033] It should be specifically explained here that the interception performance outlier value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to calculate the interception performance outlier value, the quality analysis module is used to substitute the calculated denoising performance outlier value and the interception performance outlier value into the quality analysis model to perform quality analysis of the chip capacitor, and the quality warning module is used to perform quality warning of the patch capacitor based on the quality analysis results of the patch capacitor.

[0034] It should be specifically explained here that the control module is used to control the operation of the signal acquisition module, the denoising performance outlier value calculation module, the interception performance outlier value calculation module, the quality analysis module and the quality warning module.

[0035] An electronic device comprises: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0036] The processor executes the above-mentioned chip capacitor quality detection method by calling the computer program stored in the memory.

[0037] A computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes a chip capacitor quality detection method as described above.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention installs a chip capacitor to be tested on a test circuit, a signal transmitting end of the test circuit continuously transmits a test signal for a set time period, a signal receiving end of the test circuit receives a received signal passing through the chip capacitor, and substitutes the acquired signal information of the transmitted test signal and the signal information of the received signal into a denoising performance evaluation model to perform a denoising performance evaluation, substitutes the acquired signal information of the transmitted test signal and the signal information of the received signal into an interception performance evaluation model to perform an interception performance evaluation, substitutes the evaluated denoising performance evaluation results and the interception performance evaluation results into a quality analysis model to perform a quality analysis of the chip capacitor, performs a quality warning of the patch capacitor according to the quality analysis result of the patch capacitor, and comprehensively analyzes the overall quality of the patch capacitor based on the removal of noise information and the distortion of interception information, thereby improving the analysis efficiency and accuracy of the overall quality of the patch capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram of the overall process of a chip capacitor quality detection method of the present invention;

[0041] Figure 2 This is a schematic diagram of the overall framework of a chip capacitor quality detection system of the present invention;

[0042] Figure 3 Schematic diagram of a suitable test assembly for the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0044] Example 1

[0045] See also Figure 1 , an embodiment provided by the present invention: the technical problem solved by this embodiment is: the prior art cannot comprehensively analyze the overall quality of the patch capacitor by comprehensively considering the removal of noise information and the distortion of intercepted information, resulting in low analysis efficiency and accuracy of the overall quality of the patch capacitor;

[0046] A chip capacitor quality detection method is used for Figure 3 The test assembly shown is used to perform quality inspection of chip capacitors, which includes the following specific steps:

[0047] The chip capacitor to be tested is installed on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set period of time, and the signal receiving end of the test circuit receives the receiving signal passing through the chip capacitor;

[0048] Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation model to evaluate the denoising performance;

[0049] Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to calculate the interception performance outlier value;

[0050] Substitute the calculated denoising performance outlier value and interception performance outlier value into the quality analysis model to perform quality analysis on the chip capacitor;

[0051] Provide quality warning of SMD capacitors based on the quality analysis results of SMD capacitors;

[0052] In this embodiment, it should be specifically explained that the chip capacitor to be tested is installed on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set period of time, and the signal receiving end of the test circuit receives the receiving signal passing through the chip capacitor, including the following specific steps:

[0053] S11, obtaining the rated cutoff frequency of the capacitor to be tested when it works on the test circuit, and installing the capacitor to be tested between the signal transmitting end and the signal receiving end on the test circuit;

[0054] S12, the signal transmitting end of the test circuit simultaneously transmits a high-frequency signal of a set strength at least 5% higher than the rated cut-off frequency and a low-frequency signal of a set strength at least 20% lower than the rated cut-off frequency to the signal receiving end, obtains a waveform diagram of the high-frequency signal of the set strength, set as the first waveform diagram, obtains a low-frequency signal of the set strength, set as the second waveform diagram, and the output signals of the two signals after passing through the chip capacitor are received by the signal receiving end of the test circuit. It should be noted here that the low frequency and high frequency here are relative to the rated cut-off frequency;

[0055] S13, outputting the signal received by the signal receiving end of the tested circuit, separating the frequency signal, obtaining a waveform corresponding to the waveform of the high-frequency signal with set strength after passing through the patch capacitor, setting it as the third waveform, and obtaining a waveform corresponding to the waveform of the low-frequency signal with set strength after passing through the patch capacitor, setting it as the fourth waveform;

[0056] It should be specifically explained in this embodiment that the denoising performance outlier value calculation model includes the following specific contents:

[0057] The first waveform and the third waveform obtained by the acquisition are obtained, and the signal amplitude data on the first waveform and the signal amplitude data on the third waveform are substituted into the denoising performance abnormal value calculation formula to calculate the denoising performance abnormal value, wherein the denoising performance abnormal value calculation formula is: Where T is the test duration, dt is the time integral, and t z is the set time standard value, D 1t is the amplitude value of the waveform signal at time t on the first waveform diagram, where D 2t is the amplitude value of the waveform signal at time t on the third waveform diagram;

[0058] Here is a sample code to implement this process:

[0059]

[0060]

[0061] It should be noted here that the removal of high-frequency signals through the chip capacitor is comprehensively analyzed, which improves the detection effect of the chip capacitor denoising performance;

[0062] It should be specifically explained in this embodiment that substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to calculate the interception performance outlier value includes the following specific steps:

[0063] S31, obtaining the obtained second waveform and the fourth waveform, substituting the obtained signal amplitude data on the second waveform and the obtained signal amplitude data on the fourth waveform into the first distortion abnormality coefficient calculation formula to calculate the first distortion abnormality coefficient, wherein the first distortion abnormality coefficient calculation formula is: Among them, D 3t is the amplitude value of the waveform signal at time t on the second waveform diagram, D 4t is the amplitude value of the waveform signal at time t on the fourth waveform diagram;

[0064] S32, substituting the obtained signal amplitude data of the second waveform and the fourth waveform into the second distortion abnormality coefficient calculation formula to calculate the second distortion abnormality coefficient, wherein the second distortion abnormality coefficient calculation formula is: Among them, exp() is the power of e, is the set signal amplitude interference value;

[0065] S33, obtaining the calculated first distortion abnormality coefficient and the second distortion abnormality coefficient and substituting them into the interception performance abnormality value calculation formula to calculate the interception performance abnormality value, the interception performance abnormality value calculation formula is: Wherein, a1 is the proportion of the first distortion abnormal coefficient, a2 is the proportion of the second distortion abnormal coefficient, and a1+a2=1;

[0066] It should be specifically explained in this embodiment that the quality analysis model includes the following specific steps:

[0067] S41. Obtain the calculated denoising performance outlier value and interception performance outlier value, substitute the denoising performance outlier value and the interception performance outlier value into the quality analysis value calculation formula to calculate the quality analysis value, wherein the quality analysis value calculation formula is: Q = Qmax(1-β1kjz1-β2kjz2), wherein β1 is the denoising performance outlier value ratio coefficient, β2 is the interception performance outlier value ratio coefficient, Q max is the maximum value of the set mass analysis value; it should be noted that the maximum value of the mass analysis value here is set according to the user's interest, preferably 100;

[0068] S42, comparing the calculated quality analysis value with the set quality analysis standard value, if the obtained quality analysis value is greater than or equal to the set quality analysis standard value, it means that the quality of the chip capacitor is qualified, if the obtained quality analysis value is less than the set quality analysis standard value, it means that the quality of the chip capacitor is unqualified;

[0069] In this embodiment, it should be specifically explained that the specific content of the quality warning of the SMD capacitor according to the quality analysis result of the SMD capacitor is as follows:

[0070] If the test result of the chip capacitor indicating that the quality is unqualified is obtained, an early warning of the unqualified quality of the chip capacitor will be issued to the management personnel.

[0071] It should be noted that the quality analysis standard value, the first distortion abnormal coefficient ratio, the second distortion abnormal coefficient ratio, the interception performance abnormal value ratio coefficient and the denoising performance abnormal value ratio coefficient are obtained as follows: the signal information of the transmitted test signal and the signal information of the received signal in the experiment of 5000 groups of patch capacitors are obtained, and it is manually determined whether the patch capacitor is a product of unqualified quality, and the signal information of the transmitted test signal and the signal information of the received signal are substituted into the quality analysis value calculation formula to calculate the quality analysis value, and the calculated quality analysis value and the judgment result are imported into the fitting software, and the optimal quality analysis standard value, the first distortion abnormal coefficient ratio, the second distortion abnormal coefficient ratio, the interception performance abnormal value ratio coefficient and the denoising performance abnormal value ratio coefficient that meet the judgment accuracy are output;

[0072] It should be noted here that the advantages of this embodiment over the prior art are as follows: the chip capacitor to be tested is installed on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set time period, the signal receiving end of the test circuit receives the received signal passing through the chip capacitor, the signal information of the transmitted test signal and the signal information of the received signal are substituted into the denoising performance evaluation model for denoising performance evaluation, the signal information of the transmitted test signal and the signal information of the received signal are substituted into the interception performance evaluation model for interception performance evaluation, the denoising performance evaluation results and the interception performance evaluation results obtained are substituted into the quality analysis model for quality analysis of the chip capacitor, a quality warning of the patch capacitor is performed based on the quality analysis results of the patch capacitor, the overall quality of the patch capacitor is comprehensively analyzed based on the removal of noise information and the distortion of intercepted information, thereby improving the analysis efficiency and accuracy of the overall quality of the patch capacitor.

[0073] Example 2

[0074] like Figure 2As shown, a chip capacitor quality detection system is implemented based on the above-mentioned chip capacitor quality detection method, which specifically includes a signal acquisition module, a denoising performance abnormal value calculation module, a retention performance abnormal value calculation module, a quality analysis module, a quality warning module and a control module, wherein the signal acquisition module is used to install the chip capacitor to be tested on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set time period, the signal receiving end of the test circuit receives the received signal passing through the chip capacitor, and the denoising performance abnormal value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation module. The denoising performance is evaluated in the estimation model; the interception performance outlier value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to calculate the interception performance outlier value; the quality analysis module is used to substitute the calculated denoising performance outlier value and interception performance outlier value into the quality analysis model to perform quality analysis of the patch capacitor; the quality warning module is used to perform quality warning of the patch capacitor according to the quality analysis result of the patch capacitor; the control module is used to control the operation of the signal acquisition module, the denoising performance outlier value calculation module, the interception performance outlier value calculation module, the quality analysis module and the quality warning module.

[0075] Example 3

[0076] This embodiment provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0077] The processor executes the above-mentioned chip capacitor quality detection method by calling the computer program stored in the memory.

[0078] Example 4

[0079] This embodiment provides a computer-readable storage medium having a rewritable computer program stored thereon;

[0080] When the computer program runs on a computer device, the computer device executes the above-mentioned chip capacitor quality detection method.

[0081] For example, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0082] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0083] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A chip capacitor quality detection method, characterized in that: It includes the following specific steps: The chip capacitor to be tested is installed on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set period of time, and the signal receiving end of the test circuit receives the receiving signal passing through the chip capacitor; Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation model to evaluate the denoising performance; Substituting the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to perform interception performance evaluation; Substitute the obtained denoising performance evaluation results and interception performance evaluation results into the quality analysis model to perform quality analysis on the chip capacitors; Provide quality warning of SMD capacitors based on the quality analysis results of SMD capacitors; The step of installing the chip capacitor to be tested on the test circuit, the signal transmitting end of the test circuit continuously transmitting the test signal for a set period of time, and the signal receiving end of the test circuit receiving the receiving signal passing through the chip capacitor includes the following specific steps: S11, obtaining the rated cutoff frequency of the capacitor to be tested when it works on the test circuit, and installing the capacitor to be tested between the signal transmitting end and the signal receiving end on the test circuit; S12, the signal transmitting end of the test circuit simultaneously transmits a high-frequency signal of a set strength at least 5% higher than the rated cut-off frequency and a low-frequency signal of a set strength at least 20% lower than the rated cut-off frequency to the signal receiving end, obtains a waveform diagram of the high-frequency signal of the set strength, set as the first waveform diagram, obtains a low-frequency signal of the set strength, set as the second waveform diagram, and the output signals of the two signals after passing through the chip capacitor are received by the signal receiving end of the test circuit. It should be noted here that the low frequency and high frequency here are relative to the rated cut-off frequency; S13, the signal output received by the signal receiving end of the tested circuit is separated into frequency signals, and a waveform corresponding to the waveform of the high-frequency signal of the set strength after passing through the patch capacitor is obtained, which is set as the third waveform, and a waveform corresponding to the waveform of the low-frequency signal of the set strength after passing through the patch capacitor is obtained, which is set as the fourth waveform; the denoising performance abnormal value calculation model includes the following specific contents: The first waveform and the third waveform obtained by the acquisition are obtained, and the signal amplitude data on the first waveform and the signal amplitude data on the third waveform are substituted into the denoising performance abnormal value calculation formula to calculate the denoising performance abnormal value, wherein the denoising performance abnormal value calculation formula is: Where T is the test duration, dt is the time integral, and t z is the set time standard value, D 1t is the amplitude value of the waveform signal at time t on the first waveform diagram, where D 2t is the waveform signal amplitude value at time t on the third waveform diagram; the step of substituting the acquired signal information of the transmitted test signal and the received signal into the interception performance evaluation model to calculate the interception performance abnormal value includes the following specific steps: S31, obtaining the obtained second waveform and the fourth waveform, substituting the obtained signal amplitude data on the second waveform and the obtained signal amplitude data on the fourth waveform into the first distortion abnormality coefficient calculation formula to calculate the first distortion abnormality coefficient, wherein the first distortion abnormality coefficient calculation formula is: Among them, D 3t is the amplitude value of the waveform signal at time t on the second waveform diagram, D 4t is the amplitude value of the waveform signal at time t on the fourth waveform diagram; S32, substituting the obtained signal amplitude data of the second waveform and the fourth waveform into the second distortion abnormality coefficient calculation formula to calculate the second distortion abnormality coefficient, wherein the second distortion abnormality coefficient calculation formula is: Among them, exp() is the power of e, is the set signal amplitude interference value; S33, obtaining the calculated first distortion abnormality coefficient and the second distortion abnormality coefficient and substituting them into the interception performance abnormality value calculation formula to calculate the interception performance abnormality value, the interception performance abnormality value calculation formula is: Wherein, a1 is the proportion of the first distortion abnormal coefficient, a2 is the proportion of the second distortion abnormal coefficient, and a1+a2=1; the quality analysis model includes the following specific steps: S41. Obtain the calculated denoising performance outlier value and interception performance outlier value, substitute the denoising performance outlier value and the interception performance outlier value into the quality analysis value calculation formula to calculate the quality analysis value, wherein the quality analysis value calculation formula is: Q = Qmax(1-β1kjz1-β2kjz2), wherein β1 is the denoising performance outlier value ratio coefficient, β2 is the interception performance outlier value ratio coefficient, Q max The maximum value of the set quality analysis value; S42. Compare the calculated quality analysis value with the set quality analysis standard value. If the obtained quality analysis value is greater than or equal to the set quality analysis standard value, it means that the quality of the chip capacitor is qualified. If the obtained quality analysis value is less than the set quality analysis standard value, it means that the quality of the chip capacitor is unqualified.

2. A chip capacitor quality detection method as claimed in claim 1, characterized in that: The specific contents of the quality warning of the SMD capacitors according to the quality analysis results of the SMD capacitors are as follows: If the test result of the chip capacitor indicating that the quality is unqualified is obtained, an early warning of the unqualified quality of the chip capacitor will be issued to the management personnel.

3. A chip capacitor quality detection system, which is implemented based on the chip capacitor quality detection method according to any one of claims 1-2, characterized in that: It specifically includes a signal acquisition module, a denoising performance outlier value calculation module, a retention performance outlier value calculation module, a quality analysis module, a quality warning module and a control module, wherein the signal acquisition module is used to install the chip capacitor to be tested on the test circuit, the signal transmitting end of the test circuit continuously transmits the test signal for a set time period, and the signal receiving end of the test circuit receives the received signal passing through the chip capacitor, and the denoising performance outlier value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the denoising performance evaluation model to perform denoising performance evaluation.

4. A chip capacitor quality detection system as claimed in claim 3, characterized in that: The interception performance outlier value calculation module is used to substitute the acquired signal information of the transmitted test signal and the signal information of the received signal into the interception performance evaluation model to calculate the interception performance outlier value; the quality analysis module is used to substitute the calculated denoising performance outlier value and interception performance outlier value into the quality analysis model to perform quality analysis of the chip capacitor; the quality warning module is used to perform quality warning of the chip capacitor according to the quality analysis results of the chip capacitor; and the control module is used to control the operation of the signal acquisition module, the denoising performance outlier value calculation module, the interception performance outlier value calculation module, the quality analysis module and the quality warning module.

5. An electronic device comprising: A processor and a memory, wherein the memory stores a computer program that can be called by the processor; It is characterized in that the processor executes a chip capacitor quality detection method as described in any one of claims 1-2 by calling a computer program stored in the memory.

6. A computer-readable storage medium, characterized in that: Instructions are stored, and when the instructions are executed on a computer, the computer executes a chip capacitor quality detection method as described in any one of claims 1-2.

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