Multi-core consistency test method and device, electronic equipment and storage medium

Abstract

The invention provides a multi-core consistency test method and device, electronic equipment and a storage medium, and relates to the technical field of communication. Comprising the following steps: determining a plurality of test parameters and a value range of each test parameter according to a test requirement of tested equipment; generating a plurality of groups of test parameter combinations according to the value range of each test parameter; according to the multiple groups of test parameter combinations, creating a test program corresponding to each processing core in a plurality of processing cores participating in the test in the tested equipment, and deploying the test program corresponding to each processing core to each processing core; running the test program on each processing core, and controlling the corresponding processing core to perform consistency test verification by the test program according to each group of test parameter combination to obtain a test result corresponding to each group of test parameter combination; and according to the test result corresponding to each group of test parameter combination, analyzing to obtain a consistency test result between the processing cores. According to the method, the test parameter combination capable of comprehensively covering more test scenes can be generated, and the test comprehensiveness and accuracy are improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a multi-core consistency testing method, device, electronic device and storage medium. Background Art

[0002] With the development of CPU (Central Processing Unit) technology and the increasingly complex and diversified computing needs, traditional single-core processors can no longer meet the needs of all application scenarios. In this context, heterogeneous multi-core applications are increasingly attracting attention from R&D and production. However, with the increase in the number of CPUs and the increase in the internal complexity of the CPU, how to ensure the stable and efficient operation of the CPU in complex heterogeneous multi-core applications has become a topic that must be considered and requires long-term attention.

[0003] Currently, the test for multi-core consistency is performed by generating a test parameter combination, determining a test model and test-related data based on the test parameter combination, and then controlling each processing core to perform the test according to the test-related data according to the test flow of the test model.

[0004] However, the test parameter combinations generated by existing methods are relatively limited and cannot cover more test scenarios, resulting in poor accuracy of test results. Summary of the invention

[0005] The purpose of this application is to provide a multi-core consistency testing method, device, electronic device and storage medium to address the deficiencies in the above-mentioned prior art, so as to improve the comprehensiveness and analysis efficiency of multi-core consistency analysis.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a multi-core consistency testing method, including:

[0008] Determine multiple test parameters and the value range of each test parameter according to the test requirements of the device under test;

[0009] Generate multiple test parameter combinations according to the value range of each test parameter, each test parameter combination includes each of the test parameters and a value of the test parameter;

[0010] Creating, according to the plurality of test parameter combinations, a test program corresponding to each of the plurality of processing cores participating in the test in the device under test, and deploying the test program corresponding to each of the processing cores to each of the processing cores;

[0011] Running a test program on each processing core, wherein the test program controls the corresponding processing core to perform consistency test verification according to each set of test parameter combinations, and obtains a test result corresponding to each set of test parameter combinations;

[0012] According to the test results corresponding to each group of test parameter combinations, the consistency test results between the processing cores are analyzed and obtained.

[0013] Optionally, generating multiple groups of test parameter combinations according to the value range of each test parameter includes:

[0014] Determining the number of processing core combinations according to a value range of a parameter representing the number of processing cores in the multiple test parameters, wherein the processing core combination includes multiple processing cores;

[0015] Determine the number of parameter combinations that can be generated under the specified test parameters according to the value range of each test parameter, wherein the parameter combination includes: a value of multiple test parameters;

[0016] Determining iteration constraint information according to the number of processing core combinations and the number of parameter combinations;

[0017] According to the iteration constraint information and the value range of each test parameter, multiple groups of test parameter combinations are iteratively generated.

[0018] Optionally, the iteratively generating multiple groups of test parameter combinations according to the iteration constraint information and the value range of each test parameter includes:

[0019] Traversing each test parameter in each processing core, determining the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generating at least one set of test parameter combination corresponding to each iteration round;

[0020] In each iteration round, it is determined whether to stop the iteration according to the iteration constraint information. If so, each group of test parameter combinations currently generated is used as the multiple groups of test parameter combinations.

[0021] Optionally, traversing each test parameter in each processing core, determining, according to a value range of each test parameter, a combination mode of each processing core under different values ​​of each test parameter in each iteration round, and generating at least one set of test parameter combinations corresponding to each iteration round, includes:

[0022] For a current test parameter in a current processing core of a current iteration round, traverse each value of the current test parameter according to a value range of the current test parameter;

[0023] For the current value of the current test parameter traversed, determine whether the current value is the maximum value in the value range of the current test parameter;

[0024] If yes, generate a set of test parameter combinations according to the current value, and traverse the next test parameter of the current test parameter in the current processing core;

[0025] If not, a set of test parameter combinations is generated according to the current value, and the next value of the current value is traversed.

[0026] Optionally, in each iteration round, determining whether to stop iteration according to the iteration constraint information includes:

[0027] In a current iteration round, determining a total number of test parameter combinations generated in the current iteration round and all rounds before the current iteration round;

[0028] If the total number satisfies the iteration constraint information, it is determined to stop the iteration.

[0029] Optionally, creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple groups of test parameter combinations includes:

[0030] Determine a parameter representing the number of processing cores from the test parameters, and determine the number of test programs to be created according to a value range of the parameter representing the number of processing cores;

[0031] Configure the corresponding relationship between each processing core involved in the test and each test program;

[0032] According to each group of test parameter combinations, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program, a test program corresponding to each processing core participating in the test is created.

[0033] Optionally, deploying the test program corresponding to each processing core to each processing core includes:

[0034] Generate image files through hybrid heterogeneous deployment tools based on the test software corresponding to each processing core and the preset startup program;

[0035] The image file is loaded, and the test program corresponding to each processing core is deployed on each processing core based on the startup program.

[0036] Optionally, controlling the corresponding processing core to perform consistency test verification according to each group of test parameter combinations to obtain test results corresponding to each group of test parameter combinations includes:

[0037] According to each group of test parameter combinations, the first test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate the test results corresponding to each group of test parameter combinations under the first test model;

[0038] According to each group of test parameter combinations, the second test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate corresponding test results for each group of test parameter combinations under the second test model.

[0039] Optionally, analyzing the test results corresponding to each group of test parameter combinations to obtain consistency test results between the processing cores includes:

[0040] Using at least one dimension of screening strategy, data screening is performed on the test results corresponding to each group of test parameter combinations to obtain screening results under each dimension;

[0041] Data fusion analysis is performed based on the screening results in each dimension to obtain the consistency test results between each processing core.

[0042] Optionally, the filtering results under each dimension include: a first filtering result, a second filtering result and a third filtering result; the first filtering result is used to indicate a data set consisting of test results under different test models; the second filtering result is used to indicate a data set consisting of test results of inconsistent memories of each processing core; the third filtering result is used to indicate a data set consisting of test results when the processing core is in the tester processing core or in the checker processing core.

[0043] Optionally, the screening strategy of at least one dimension is adopted to screen the test results corresponding to each group of test parameter combinations to obtain the screening results under each dimension, including:

[0044] According to the type of the adopted test model, the test results corresponding to each group of test parameter combinations are screened to obtain the first screening result;

[0045] According to the success or failure of the test result, the test results corresponding to each group of test parameter combinations are screened to obtain the second screening result;

[0046] According to the processing core type of each processing core, the test results corresponding to each group of test parameter combinations are screened to obtain the third screening result.

[0047] Optionally, performing data fusion analysis according to the screening results under each dimension to obtain consistency test results between each processing core includes:

[0048] The first screening result and the second screening result are merged to obtain a first arrangement set of memory inconsistent result data sets under different test models;

[0049] Generate a first result distribution graph according to the first permutation set; the first result distribution graph is used to indicate a distribution graph of reasons for memory inconsistency under different test models;

[0050] The first screening result and the third screening result are merged to obtain a second arrangement set of result data sets between different processing cores under different test models;

[0051] generating a second result distribution graph according to the second arrangement set; the second result distribution graph is used to indicate the consistency of processing cores in different clusters under different test models;

[0052] The second screening result and the third screening result are merged to obtain a third arrangement set of result data sets of memory inconsistencies between different processing cores, the tester processing core and the checker processing core;

[0053] A third result distribution graph is generated according to the third arrangement set; the third result distribution graph is used to indicate the memory inconsistency corresponding to the processing core angle of each tester or the processing core angle of each inspector;

[0054] According to the first result distribution diagram, the second result distribution diagram and the third result distribution diagram, quantitative processing is performed to obtain the relationship between the inconsistent data results of the memory between the two processing cores and each test parameter, and a consistency test result file between the processing cores is generated.

[0055] Optionally, generating a first result distribution graph according to the first permutation set includes:

[0056] According to the memory attribute information and software consistency information of the tester core and the checker core in the first arrangement set, differential processing and model construction are performed on the first arrangement set to obtain the first result distribution map.

[0057] Optionally, generating a second result distribution graph according to the second arrangement set includes:

[0058] According to the cluster information of each processing core in the second arrangement set, the second arrangement set is differentiated and a model is constructed to generate the second result distribution map.

[0059] Optionally, generating a third result distribution graph according to the third permutation set includes:

[0060] According to the memory inconsistency information between each tester core and other checker cores in the third arrangement set, the data in the third arrangement set is merged to generate the third result distribution map.

[0061] In a second aspect, an embodiment of the present application further provides a multi-core consistency testing device, including: a determination module, a generation module, a deployment module, a test module, and an analysis module;

[0062] The determination module is used to determine multiple test parameters and the value range of each test parameter according to the test requirements of the device under test;

[0063] The generating module is used to generate multiple test parameter combinations according to the value range of each test parameter, each test parameter combination including each test parameter and a value of the test parameter;

[0064] The deployment module is used to create a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple groups of test parameter combinations, and deploy the test program corresponding to each processing core to each processing core;

[0065] The test module is used to run the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations to obtain the test results corresponding to each group of test parameter combinations;

[0066] The analysis module is used to analyze and obtain consistency test results between the processing cores according to the test results corresponding to each group of test parameter combinations.

[0067] Optionally, the generating module is specifically used to determine the number of processing core combinations according to the value range of the parameter representing the number of processing cores in the multiple test parameters, wherein the processing core combination includes multiple processing cores;

[0068] Determine the number of parameter combinations that can be generated under the specified test parameters according to the value range of each test parameter, wherein the parameter combination includes: a value of multiple test parameters;

[0069] Determining iteration constraint information according to the number of processing core combinations and the number of parameter combinations;

[0070] According to the iteration constraint information and the value range of each test parameter, multiple groups of test parameter combinations are iteratively generated.

[0071] Optionally, the generating module is specifically used to traverse each test parameter in each processing core, determine the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generate at least one set of test parameter combination corresponding to each iteration round;

[0072] In each iteration round, it is determined whether to stop the iteration according to the iteration constraint information. If so, each group of test parameter combinations currently generated is used as the multiple groups of test parameter combinations.

[0073] Optionally, the generating module is specifically configured to traverse each value of the current test parameter in the current processing core of the current iteration round traversed according to the value range of the current test parameter;

[0074] For the current value of the current test parameter traversed, determine whether the current value is the maximum value in the value range of the current test parameter;

[0075] If yes, generate a set of test parameter combinations according to the current value, and traverse the next test parameter of the current test parameter in the current processing core;

[0076] If not, a set of test parameter combinations is generated according to the current value, and the next value of the current value is traversed.

[0077] Optionally, the generating module is specifically configured to determine, in a current iteration round, a total number of test parameter combinations generated in the current iteration round and all rounds before the current iteration round;

[0078] If the total number satisfies the iteration constraint information, it is determined to stop the iteration.

[0079] Optionally, the deployment module is specifically used to determine a parameter representing the number of processing cores from the test parameters, and determine the number of test programs to be created according to a value range of the parameter representing the number of processing cores;

[0080] Configure the corresponding relationship between each processing core involved in the test and each test program;

[0081] According to each group of test parameter combinations, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program, a test program corresponding to each processing core participating in the test is created.

[0082] Optionally, the deployment module is specifically used to deploy the test program corresponding to each processing core to each processing core, including:

[0083] Generate image files through hybrid heterogeneous deployment tools based on the test software corresponding to each processing core and the preset startup program;

[0084] The image file is loaded, and the test program corresponding to each processing core is deployed on each processing core based on the startup program.

[0085] Optionally, the test module is specifically used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core according to each group of test parameter combinations, using the first test model, and generate test results corresponding to each group of test parameter combinations under the first test model;

[0086] According to each group of test parameter combinations, the second test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate corresponding test results for each group of test parameter combinations under the second test model.

[0087] Optionally, the analysis module is specifically used to adopt a screening strategy of at least one dimension to perform data screening on the test results corresponding to each group of test parameter combinations to obtain screening results under each dimension;

[0088] Data fusion analysis is performed based on the screening results in each dimension to obtain the consistency test results between each processing core.

[0089] Optionally, the filtering results under each dimension include: a first filtering result, a second filtering result and a third filtering result; the first filtering result is used to indicate a data set consisting of test results under different test models; the second filtering result is used to indicate a data set consisting of test results of inconsistent memories of each processing core; the third filtering result is used to indicate a data set consisting of test results when the processing core is in the tester processing core or in the checker processing core.

[0090] Optionally, the analysis module is specifically used to screen the test results corresponding to each group of test parameter combinations according to the type of the adopted test model to obtain the first screening result;

[0091] According to the success or failure of the test result, the test results corresponding to each group of test parameter combinations are screened to obtain the second screening result;

[0092] According to the processing core type of each processing core, the test results corresponding to each group of test parameter combinations are screened to obtain the third screening result.

[0093] Optionally, the analysis module is specifically used to merge the first screening result with the second screening result to obtain a first arrangement set of memory inconsistent result data sets under different test models;

[0094] Generate a first result distribution graph according to the first permutation set; the first result distribution graph is used to indicate a distribution graph of reasons for memory inconsistency under different test models;

[0095] The first screening result and the third screening result are merged to obtain a second arrangement set of result data sets between different processing cores under different test models;

[0096] generating a second result distribution graph according to the second arrangement set; the second result distribution graph is used to indicate the consistency of processing cores in different clusters under different test models;

[0097] The second screening result and the third screening result are merged to obtain a third arrangement set of result data sets of memory inconsistencies between different processing cores, the tester processing core and the checker processing core;

[0098] A third result distribution graph is generated according to the third arrangement set; the third result distribution graph is used to indicate the memory inconsistency corresponding to the processing core angle of each tester or the processing core angle of each inspector;

[0099] According to the first result distribution diagram, the second result distribution diagram and the third result distribution diagram, quantitative processing is performed to obtain the relationship between the inconsistent data results of the memory between the two processing cores and each test parameter, and a consistency test result file between the processing cores is generated.

[0100] Optionally, the analysis module is specifically configured to perform differential processing and model construction on the first arrangement set according to the memory attribute information and software consistency information of the tester core and the checker core in the first arrangement set to obtain the first result distribution graph.

[0101] Optionally, the analysis module is specifically configured to perform differentiation and model building on the second arrangement set according to cluster information of each processing core in the second arrangement set, so as to generate the second result distribution graph.

[0102] Optionally, the analysis module is specifically configured to fuse the data in the third arrangement set according to memory inconsistency information between each tester core and other checker cores in the third arrangement set to generate the third result distribution graph.

[0103] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to implement the multi-core consistency testing method provided in the first aspect.

[0104] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the multi-core consistency testing method provided in the first aspect is executed.

[0105] The beneficial effects of this application are:

[0106] The present application provides a multi-core consistency test method, device, electronic device and storage medium, including: determining multiple test parameters and the value range of each test parameter according to the test requirements of the device under test; generating multiple test parameter combinations according to the value range of each test parameter, each test parameter combination contains each test parameter and a value of the test parameter; creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple test parameter combinations, and deploying the test program corresponding to each processing core to each processing core; running the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each test parameter combination, and obtains the test results corresponding to each test parameter combination; according to the test results corresponding to each test parameter combination, analyzing and obtaining the consistency test results between each processing core. The method can set the test parameters and the value range of the test parameters based on the test requirements, so as to perform iterative processing according to the value range of the test parameters to generate a test parameter combination that can fully cover more test scenarios, so as to perform consistency test verification based on the test parameter combination, and improve the comprehensiveness and accuracy of the test results.

[0107] In addition, through automated data fusion and analysis, the test results can be screened and integrated from different perspectives to achieve a comprehensive understanding and analysis of memory inconsistency issues. This can quickly and accurately determine the causes of certain memory consistency issues in current heterogeneous software, thereby improving the efficiency of problem analysis and resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0109] Figure 1 A schematic diagram of a multi-core consistency test system architecture provided in an embodiment of the present application;

[0110] Figure 2 A flowchart of a multi-core consistency testing method provided in an embodiment of the present application;

[0111] Figure 3 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0112] Figure 4 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0113] Figure 5 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0114] Figure 6 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0115] Figure 7 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0116] Figure 8 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0117] Fig. 9 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0118] Fig.10 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0119] Fig.11 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0120] Fig.12 A schematic diagram of a multi-core consistency testing device provided in an embodiment of the present application;

[0121] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0122] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0123] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0124] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0125] With the development of CPU (Central Processing Unit) technology and the increasingly complex and diversified computing needs, traditional single-core processors can no longer meet the needs of all application scenarios. In this context, heterogeneous multi-core applications are increasingly attracting attention from R&D and production. However, with the increase in the number of CPU cores and the increase in the internal complexity of the CPU, how to ensure the stable and efficient operation of the CPU in complex heterogeneous multi-core applications has become a topic that must be considered and requires long-term attention.

[0126] The current status of the stability evaluation method for multi-core consistency is as follows:

[0127] 1. Method based on pre-silicon design simulation: This method is usually used in the early stages of SOC (System on Chip) design, mainly involving the design of cluster, cache and bus-level cache controllers. In the pre-silicon design stage, a simulation platform is used to verify whether the design complies with the predetermined CPU architecture rules and to perform consistency path testing. However, the disadvantage of this solution is that it relies on the real-time simulation capability of the simulation platform, resulting in low verification efficiency. In addition, due to the differences between the simulation platform and the actual hardware, some consistency indicators may not match the actual hardware. Therefore, although this method has its application value in the early stages of design, its accuracy may be affected.

[0128] 2. Post-silicon test solution based on Linux operating system: This method usually has a relatively complete test case library and can design different experimental scenarios to comprehensively test multi-core consistency. Its advantage is that it can comprehensively cover the system level and effectively evaluate various combinations of multi-core consistency. However, the disadvantage of this solution is that the use of a complex operating system may affect the real-time evaluation of memory and cache. In addition, because there may be a variety of other processes running in the Linux system, these processes may interfere with the main test indicators when performing consistency testing, thereby affecting efficiency and accuracy.

[0129] 3. Hardware-accelerated test platform solution: It combines the advantages of pre-silicon design and post-silicon testing. It simulates the behavior of multi-core processors by using hardware accelerators such as FPGA (Field-Programmable Gate Array) or custom hardware, and performs consistency testing in an environment close to the actual hardware. This solution improves the test speed and efficiency, while more accurately reflecting the consistency performance of multi-core systems in actual applications. It allows more flexible test scenario configuration, can better simulate real-world application situations, and improves the practicality of testing. However, the main disadvantage of this method is that it has a high implementation cost, requires specialized hardware equipment and high technical knowledge, and the construction and maintenance of the hardware platform may also limit its application.

[0130] With the increase in the number of cores and the various customizations for CPU architectures, existing technologies have become more complex and inefficient in multi-core consistency analysis. Specifically, 1) Pre-silicon design simulation methods are inefficient in complex multi-core environments due to limited simulation capabilities and are different from actual hardware; 2) Linux-based post-silicon testing solutions may affect the real-time and accuracy of testing due to complex system environments and background processes; 3) Although hardware-accelerated testing platforms improve efficiency, they are costly and complex to build and maintain. These factors limit the effectiveness and efficiency of existing technologies in high-core count and customized CPU architectures.

[0131] Based on this, this solution provides a multi-core consistency testing method, which can set test parameters and the value range of test parameters based on test requirements, and then perform iterative processing according to the value range of test parameters to generate test parameter combinations that can comprehensively cover more test scenarios, thereby performing consistency test verification based on the test parameter combination, which can improve the comprehensiveness and accuracy of the test results.

[0132] Figure 1 A schematic diagram of a multi-core consistency test system architecture provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the system may include: a host device, an embedded development board, and a host computer; multiple processing cores are deployed in the embedded development board, and the test personnel can set the test parameters that need to be paid attention to and the value range of each test parameter according to the test requirements; the value range of each parameter is input into the host device, and the parameters are iterated in the host device according to the value range of each parameter to generate multiple groups of test parameter combinations, and the test program is compiled based on the test parameter combination; the compiled test program is burned into the storage medium of the embedded development board through a burning tool, and the test program is loaded into each processing core participating in the test through an initialization instruction. The processing core in the embedded development board controls each processing core participating in the test to perform a consistency test based on the test program to obtain the test result. After all the consistency tests in the embedded development board are completed, the embedded development board sends the test result related data stored in the storage medium to the host computer for analysis and display. Among them, the host computer will clean and merge the data based on the test results of the consistency test and display the final analysis results. The problem of memory consistency is fully understood and analyzed, and the reasons for certain phenomena in memory consistency of the current heterogeneous software can be quickly determined.

[0133] Figure 2 A flowchart of a multi-core consistency testing method provided in an embodiment of the present application; Figure 2 As shown, the method may include:

[0134] S101. Determine multiple test parameters and a value range of each test parameter according to the test requirements of the device under test.

[0135] Testers can determine the test parameters to be concerned about during the test process and the value range of each test parameter based on the test requirements of the device under test. That is, testers need to determine which parameters the test should be based on to verify the multi-core consistency of the device under test, and what the value range of these parameters is.

[0136] In this embodiment, the test parameters and value ranges set according to the test requirements may include but are not limited to: the value range of the number of cores, the iteration range of the memory shared domain attributes, whether to perform consistency operations before checking the data, whether to perform consistency operations after writing the data, variable combinations of memory attributes, the memory address used in the test and the length of the test, selection of core test objects, test model selection, etc.

[0137] It should be noted that the “core” described in the following embodiments refers to a processing core.

[0138] S102. Generate multiple test parameter combinations according to the value range of each test parameter, each test parameter combination including each test parameter and a value of the test parameter.

[0139] Based on the set test parameters and the value range of each test parameter, the value range of each test parameter can be written into the configuration file through the editor, and the scale of the number of iterations can be determined based on the value range of each test parameter, that is, the constraints of the iteration are determined, so as to execute the iteration strategy to traverse all possible combinations of each test parameter within the value range, complete all iterations, and generate multiple groups of test parameter combinations.

[0140] The purpose of executing the iteration strategy is to ensure that the test parameters determined by the tester can fully cover all possible combinations after the consistency test begins. That is, the generated test parameter combinations can cover all test scenarios as comprehensively as possible to improve the accuracy of the test results.

[0141] It should be noted that each generated test parameter combination includes each test parameter and a value of each test parameter.

[0142] Exemplarily, a set of test parameter combinations generated may be, for example:

[0143] 1. Number of cores: 2;

[0144] 2. Shared memory attribute: internal sharing (shared between core A and core B);

[0145] 3. Check whether consistency operation is performed before data: both core A and core B require consistency operation;

[0146] 4. Whether to perform consistency operation before writing data: Both core A and core B require consistency operation;

[0147] 5. Memory attributes: cacheable, internally shared;

[0148] 6. The memory address length used in the test: address range 0x1000-0x1FFF, a total of 4KB;

[0149] 7. Confirm that the CPU acts as a tester or checker: core A acts as a tester and core B acts as a checker;

[0150] 8. Test model selection: tiled model or hybrid model.

[0151] Another set of test parameter combinations generated may be, for example:

[0152] 1. Number of cores: 4;

[0153] 2. Shared memory attributes: external sharing (core A, B, C, D sharing);

[0154] 3. Check whether consistency operation is performed before data: Core A and core B need consistency operation;

[0155] 4. Whether to perform consistency operation before writing data: Core C and core D need consistency operation;

[0156] 5. Memory attributes: non-cacheable, externally shared;

[0157] 6. Memory address length used in the test: address range 0x2000-0x3FFF, totaling 8KB;

[0158] 7. Confirm that the CPU acts as a tester or checker: core A and core C act as testers, and core B and core D act as checkers;

[0159] 8. Test model selection: tiled model or hybrid model.

[0160] It can be seen that one set of test parameter combinations includes all the set test parameters, and the values ​​of each test parameter in different test parameter combinations are not completely the same. In other words, there is no situation where the values ​​of each test parameter in two test parameter combinations are completely the same.

[0161] S103 . Create a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple test parameter combinations, and deploy the test program corresponding to each of the processing cores to each of the processing cores.

[0162] In some embodiments, since different test parameter combinations indicate different numbers of processing cores involved in the test and different processing cores involved in the test, each processing core involved in the test needs to pre-deploy a corresponding test program before the test program can be started to execute the test process during the consistency test phase.

[0163] Therefore, according to each set of test parameter combinations, a test program corresponding to each processing core participating in the test in the device under test can be created. Among them, the test programs corresponding to different processing cores may be different. This is because the test identities corresponding to different processing cores during the test process may be different. For example, the test processes to be executed by the tester processing core and the inspector processing core are different, so the corresponding deployed test programs will also be different.

[0164] Optionally, the test programs corresponding to the created processing cores may be deployed to the processing cores accordingly.

[0165] S104, running the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations, and obtains the test results corresponding to each group of test parameter combinations.

[0166] After completing the deployment of the test program, you can enter the consistency test phase, start and run the test program deployed in each processing core participating in the test, and the test program controls the corresponding processing core to perform consistency test verification according to the information indicated in each set of test parameter combinations.

[0167] Exemplarily, assuming that the test parameter combination indicates that processing core A is used as the checker processing core and processing core B is used as the tester processing core, and the target model is selected for testing, then the test program deployed in processing core A can control processing core A to perform testing according to the test process to be executed by the checker processing core under the target model, and the test program deployed in processing core B can control processing core B to perform testing according to the test process to be executed by the tester processing core under the target model.

[0168] Since different test combination parameters indicate different information, each processing core corresponding to each test parameter combination is controlled to perform consistency test verification in the above manner, and the test results corresponding to each group of test parameter combinations can be obtained.

[0169] S105 . Analyze and obtain consistency test results between the processing cores according to the test results corresponding to each group of test parameter combinations.

[0170] In some embodiments, the test results corresponding to each group of test parameter combinations can first be saved in the storage medium of the embedded development board. After all tests are completed, they can be sent uniformly from the storage medium to the host computer so that the test results can be analyzed in the host computer to obtain and display the consistency test results between the processing cores.

[0171] Alternatively, the test results corresponding to each test parameter combination may be sent to the host computer in real time after the test is obtained, so as to be uniformly analyzed in the host computer.

[0172] In summary, the multi-core consistency test method provided by this embodiment includes: determining multiple test parameters and the value range of each test parameter according to the test requirements of the device under test; generating multiple groups of test parameter combinations according to the value range of each test parameter, each group of test parameter combinations contains each test parameter and a value of the test parameter; creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple groups of test parameter combinations, and deploying the test program corresponding to each processing core to each processing core; running the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations, and obtains the test results corresponding to each group of test parameter combinations; according to the test results corresponding to each group of test parameter combinations, analyzing and obtaining the consistency test results between each processing core. This method can set the test parameters and the value range of the test parameters based on the test requirements, so as to perform iterative processing according to the value range of the test parameters to generate a test parameter combination that can fully cover more test scenarios, so as to perform consistency test verification based on the test parameter combination, which can improve the comprehensiveness and accuracy of the test results.

[0173] Figure 3 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; Optionally, in step S102, multiple groups of test parameter combinations are generated according to the value range of each test parameter, which may include:

[0174] S201 . Determine the number of processing core combinations according to a value range of a parameter representing the number of processing cores among a plurality of test parameters, wherein the processing core combination includes a plurality of processing cores.

[0175] First, a multidimensional iterator may be instantiated, so that the multidimensional iterator can generate and combine a unique test parameter combination for subsequent consistency testing based on the value range of each test parameter.

[0176] Optionally, based on the total number of processing cores deployed in the embedded development board and the value range of the parameters that characterize the number of processing cores, the total number of unique combinations that can be formed by selecting a specified number of processing cores participating in the test from the total processing cores can be calculated through an advanced combinatorial function selection method to obtain the number of processing core combinations.

[0177] For example: the total number of processing cores is 20, and the value range of the parameter representing the number of processing cores is 8; then, when the number of processing cores participating in the test is 2, it is necessary to select 2 processing cores from the 20 processing cores to obtain a processing core combination. Since there are many combinations of the selected 2 processing cores, multiple processing core combinations can be generated. Similarly, when the number of processing cores participating in the test is 3 or 4, multiple processing core combinations will also be generated, thereby determining the number of all possible processing core combinations.

[0178] S202. Determine the number of parameter combinations that can be generated under the specified test parameters according to the value range of each test parameter, wherein the parameter combination includes: one value of multiple test parameters.

[0179] Next, the number of possible parameter combinations generated under the specified test parameters in the set test parameters may be calculated. The specified test parameters may include: the type of consistency operation (whether to perform consistency operation), memory sharing domain attributes, memory attributes, and selection of core test objects (test type of processing core, checker or tester).

[0180] The number of possible parameter combinations under the above specified test parameters can be calculated in combination with a high-order power function power series.

[0181] S203: Determine iteration constraint information according to the number of processing core combinations and the number of parameter combinations.

[0182] Optionally, iteration constraint information may be determined according to the number of processing core combinations and the number of parameter combinations obtained by the above calculation, and the iteration constraint information may indicate an upper limit of test parameter combinations that can be generated by iteration.

[0183] S204. Iteratively generate multiple groups of test parameter combinations according to the iteration constraint information and the value range of each test parameter.

[0184] Optionally, based on the value range of each test parameter, through a recursive calculation strategy, all possible values ​​of each test parameter within the value range can be traversed, and multiple groups of test parameter combinations can be iteratively generated. For each test parameter, all possible values ​​will be tried.

[0185] After each round of iteration, it can be determined whether to stop the iteration based on the number of test parameter combinations currently generated and the iteration constraint information, until the iteration stop condition is met, the iteration is ended to obtain all possible test parameter combinations.

[0186] Figure 4 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; Optionally, in step S204, iteratively generating multiple groups of test parameter combinations according to the iteration constraint information and the value range of each test parameter may include:

[0187] S301, traverse each test parameter in each processing core, determine the combination method of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generate at least one group of test parameter combinations corresponding to each iteration round.

[0188] In some embodiments, each test parameter in each processing core may be traversed, and the possible combination of each processing core under different values ​​of different test parameters in each iteration round may be determined according to the value range of each test parameter, so as to generate at least one set of test parameter combinations in each iteration round. That is, multiple sets of test parameter combinations may be generated in one iteration.

[0189] S302. In each iteration round, determine whether to stop iteration according to iteration constraint information. If so, use the currently generated test parameter combinations as multiple test parameter combinations.

[0190] Optionally, after each iteration, it can be determined whether the currently generated test parameter combination has met the constraint conditions based on the iteration constraint information determined above. If so, it means that there are no more combinations that can be generated, which means that the iteration process should end, and all currently generated test parameter combinations are used as the required multiple groups of test parameter combinations; if the constraint conditions are not met, it means that there are more combinations that can be generated, and the number of currently generated test parameter combinations has not reached the upper limit, so the next round of iteration can be continued to generate more test parameter combinations.

[0191] Figure 5 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; optionally, in step S301, traversing each test parameter in each processing core, determining the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generating at least one set of test parameter combinations corresponding to each iteration round may include:

[0192] S401 , for a current test parameter in a current processing core of a current iteration round that has been traversed, traverse various values ​​of the current test parameter according to a value range of the current test parameter.

[0193] Each test parameter of each processing core can be traversed, and the value of each test parameter can be increased in sequence according to the value range of each test parameter, until each value of each processing core under each test parameter is traversed.

[0194] This embodiment is described by taking an iterative process of any iteration round. Optionally, for the current test parameter in the current processing core traversed in the current iteration round, each value of the current test parameter can be traversed in sequence according to the value range of the current test parameter.

[0195] S402: for the current value of the traversed current test parameter, determine whether the current value is the maximum value in the value range of the current test parameter.

[0196] For the current value of the current test parameter, determine whether the current value exceeds the maximum value allowed by the value range of the current test parameter.

[0197] For example: the value range of test parameter a is 8. In the current traversal, the current value of test parameter a is 4, which does not exceed 8. If the current value of test parameter a is 8, it is considered that the current value has reached the maximum allowed value.

[0198] S403: If yes, generate a set of test parameter combinations according to the current values, and traverse the next test parameter of the current test parameter in the current processing core.

[0199] In some embodiments, if the current value of the current processing core under the current test parameter exceeds the maximum value allowed by the value range of the current test parameter, it means that all values ​​of the current processing core under the current test parameter have been traversed, and a set of test parameter combinations can be generated based on the current value of the current processing core under the current test parameter.

[0200] Since the value of the current test parameter has exceeded the maximum allowed value, it is considered that the traversal of the current processing core under the current test parameter has ended, and the test parameter combinations that can be generated by the current processing core under all values ​​of the next test parameter can be traversed again. The specific implementation steps are similar to the above, that is, the next test parameter is used as the current new test parameter for traversal. It ends when all values ​​of the current processing core under all test parameters are traversed.

[0201] S404: If not, generate a set of test parameter combinations according to the current value, and traverse the next value of the current value.

[0202] In other embodiments, if the current value of the current test parameter of the current processing core does not exceed the maximum value allowed by the value range of the current test parameter, it means that a new test parameter combination can be generated. Then, a test parameter combination can be generated based on the current value of the current test parameter of the current processing core, and after the generation is completed, continue to traverse the next value of the current test parameter of the current processing core until the value exceeds the maximum value allowed by the current test parameter, and then re-execute step S403.

[0203] It is worth noting that the traversal process is repeated for each test parameter of each processing core. When the traversal reaches the last test parameter of the last processing core and all values ​​of the last test parameter have been traversed, all possible test parameter combinations have been generated and the iterative process ends.

[0204] Optionally, during the iteration process, each time a test parameter combination is generated, the test parameter combination will be used to perform a consistency test to generate a test result corresponding to the test parameter combination.

[0205] Figure 6 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; Optionally, in step S302, in each iteration round, determining whether to stop iteration according to iteration constraint information may include:

[0206] S501. In a current iteration round, determine the total number of test parameter combinations generated in the current iteration round and all rounds before the current iteration round.

[0207] In some embodiments, after each iteration, the total number of test parameter combinations generated in the current iteration round and the total number of test parameter combinations generated in all rounds before the current iteration round may be counted. For example, if the number of test parameter combinations generated in the current iteration round is 10 and the number of test parameter combinations generated in all rounds before the current iteration round is 50, then after the current iteration ends, the total number of test parameter combinations is 50.

[0208] S502: If the total number satisfies the iteration constraint information, determine to stop the iteration.

[0209] The total number can be compared with the iteration constraint information. When the total number satisfies the iteration constraint information, it is considered that the iteration stop condition is met and the iteration can be stopped.

[0210] Assume that the iteration constraint information indicates that the upper limit of the test parameter combinations is 200, and the total number of test parameter combinations after the current iteration round is 150, which does not reach the upper limit specified by the iteration constraint information, then it is considered that there are still some possible combinations that have not been traversed, and the iteration can continue; if the total number of test parameter combinations reaches the upper limit, then it is considered that all possible combinations have been traversed, and the iteration can be terminated.

[0211] Figure 7 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; optionally, in step S103, creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to multiple groups of test parameter combinations may include:

[0212] S601 . Determine a parameter representing the number of processing cores from the test parameters, and determine the number of test programs to be created according to a value range of the parameter representing the number of processing cores.

[0213] In some embodiments, the test software for the number of processing cores that need to be created can be determined based on the value range of the core number, that is, the number of test programs to be created can be determined.

[0214] S602: Configure the corresponding relationship between each processing core involved in the test and each test program.

[0215] Edit the multi-core build script in the hybrid heterogeneous deployment tool and specify which processing core each test program works on, so as to configure the corresponding relationship between each processing core involved in the test and each test program.

[0216] S603 , creating a test program corresponding to each processing core participating in the test according to each group of test parameter combinations, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program.

[0217] Use the make command to start the build. According to the combination of each group of test parameters, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program, a test program corresponding to each processing core participating in the test can be created.

[0218] In other possible ways, for each set of test parameter combinations, a test program for each processing core participating in the test in each set of test parameter combinations can be created respectively, so that according to the relevant attribute information indicated by each set of test parameter combinations, a test program for each processing core corresponding to each set of test parameter combinations is created and deployed, that is, a test program is created and deployed separately for each processing core under each test parameter combination. Since the same processing core may have corresponding test programs deployed under different test parameter combinations, all required test programs can be deployed in one processing core in the end.

[0219] Optionally, in step S103, the test program corresponding to each processing core is deployed to each processing core, including: generating an image file through a hybrid heterogeneous deployment tool according to the test software corresponding to each processing core and a preset startup program; loading the image file, and deploying the test program corresponding to each processing core to each processing core based on the startup program.

[0220] In some embodiments, a hybrid heterogeneous deployment tool can be used to generate a packaged image file based on the test software corresponding to each processing core. The image file may contain the test programs corresponding to each processing core that have been created. The packaged image file is deployed to the embedded development board by burning the file, and then the program is started. The software will deploy all images to the corresponding processing cores according to the loading logic of the hybrid heterogeneous deployment tool.

[0221] Optionally, after the deployment of the test program and the generation of the test parameter combination are completed, the test program can be started, and the consistency test process can be performed based on the test parameter combination. The above test parameter combinations will respectively indicate which processing cores in the development board serve as tester processing cores and which processing cores serve as checker processing cores. Accordingly, by parsing the test parameter combination, it is possible to determine the core in the development board that serves as the tester, that is, the tester processing core; and determine the core in the development board that serves as the checker, that is, the checker processing core. In addition, the test model used for the test can also be determined.

[0222] Among them, during the process of executing the test, the tester processing core needs to write test data to the memory address used for the test according to the memory address indicated in the test parameter combination, and the checker processing core needs to read the test data from the memory address, so as to obtain the test result based on the consistency of the test data written by the tester processing core and the test data read by the checker processing core.

[0223] It is worth noting that each set of test parameter combinations obtained must be used for consistency testing. Since the values ​​of the test parameters in different test parameter combinations are different, the tester's processing core, the inspector's processing core, the test model used, and the attribute information required for the test may all be different. Therefore, each test parameter combination can obtain corresponding test results.

[0224] Figure 8 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; optionally, in step S104, according to each group of test parameter combinations, controlling the corresponding processing core to perform consistency test verification, and obtaining the test results corresponding to each group of test parameter combinations may include:

[0225] S701. According to each group of test parameter combinations, a first test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate test results corresponding to each group of test parameter combinations under the first test model.

[0226] S702. According to each group of test parameter combinations, the second test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate corresponding test results for each group of test parameter combinations under the second test model.

[0227] In this embodiment, the test model may include: a first model or a second model. When testing based on the first model, the tester processing core and the inspector processing core read and write the test address indicated by the test parameter combination. When testing based on the second model, the test address indicated by the test parameter combination is divided into multiple address intervals, and the tester processing core and the inspector processing core read and write each address interval respectively.

[0228] In some embodiments, based on the tester processing core, checker processing core, attribute parameters required for the test, and test model indicated in the test parameter combination, the tester processing core and the checker processing core can be controlled to execute the test process corresponding to the test model to obtain the test results corresponding to the test parameter combination.

[0229] This embodiment provides two test models, the first model can also be called a tiled model, and the second model can also be called a hybrid model. In practical applications, there can also be other test models, and the test processes of different test models are different. When the first model is used for testing, the memory address used for the test indicated in the test parameter combination can be used as a complete address. The tester processing core is responsible for writing data to the memory address used for the test, and the checker processing core is responsible for reading data from the memory address used for the test, so that the test result can be obtained based on the consistency of the written data and the read data.

[0230] When using the second model for testing, the memory address used in the test indicated in the test parameter combination can first be divided into intervals to obtain multiple address intervals. Data is read and written in each address interval according to the test method of the first model mentioned above. When data reading and writing in all address intervals are completed, the final test results are obtained.

[0231] It is worth noting that no matter whether the first model or the second model is used for testing, in one test, there is not only one tester processing core and one checker processing core. There may be multiple tester processing cores and multiple checker processing cores in one test. Which processing cores serve as tester processing cores and which processing cores serve as checker processing cores are determined based on the number of cores in the test parameter combination and the two parameters of confirming the CPU as a tester or checker.

[0232] Based on the above test process, the test results corresponding to each group of test parameter combinations under the first test model and the test results corresponding to each group of test parameter combinations under the second test model can be obtained respectively.

[0233] In some embodiments, after the consistency test phase is completed, the management scheduling processing core in the embedded development board can retrieve all the test results from the storage medium and send the test results to the host computer for big data analysis in the following data format.

[0234] Exemplarily, the test result corresponding to a test parameter combination may be:

[0235] "write core:0,mem attr:NC|NON pa:0xc0000000,va:0xc0004000,length:0x4000,wm 0; check core:1,mem attr:NC|NON pa:0xc0000000,va:0xc0004000,length:0x4000,rm 0;|right|loop cnt:8|test_time_diff:24033|checker_time_diff:163686.

[0236] write core:0,mem attr:NC|NON pa:0xc0000000,va:0xc0000000,length:0x8000,wm 1; check core:1,mem attr:NC|NON pa:0xc0000000,va:0xc0000000,length:0x8000,rm 0;|right|test_time_diff:3916|checker_time_diff:20352".

[0237] Among them, write core is the processing core involved in the test; mem attr represents the memory attribute; pa represents the physical address; va represents the virtual address; length is the size of the test memory in bytes; wm represents whether to use write software consistency during the test; rm represents whether to use read software consistency during the check; check core is the checker processing core.

[0238] The host computer can merge all received test results into a table to obtain a consistency result summary table, so that based on the consistency result summary table, the consistency test results between the processing cores can be analyzed according to the following screening strategy and fusion analysis method.

[0239] Fig. 9 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; optionally, in step S105, analyzing and obtaining consistency test results between processing cores according to test results corresponding to each group of test parameter combinations may include:

[0240] S801. Use a screening strategy of at least one dimension to screen the test results corresponding to each group of test parameter combinations to obtain screening results under each dimension.

[0241] In a feasible solution, a screening strategy of at least one dimension can be adopted to screen the test results corresponding to each group of test parameter combinations, so as to perform a fusion analysis on the test results from different dimensions and different focus points, and obtain the screening results under each dimension.

[0242] S802: Perform data fusion analysis based on the screening results in each dimension to obtain consistency test results between the processing cores.

[0243] By integrating and analyzing the screening results under different dimensions, the inconsistencies between processing cores can be analyzed from different focus points, which facilitates a comprehensive understanding and analysis of memory inconsistency issues and can quickly determine the reasons for certain phenomena in memory consistency in current heterogeneous software.

[0244] Optionally, the filtering results under each dimension include: a first filtering result, a second filtering result, and a third filtering result; the first filtering result is used to indicate a data set consisting of test results under different test models; the second filtering result is used to indicate a data set consisting of test results of inconsistent memories of each processing core; the third filtering result is used to indicate a data set consisting of test results when the processing core is in the tester processing core or in the checker processing core.

[0245] In a possible implementation, the present solution screens the results from three dimensions, and obtains a first screening result, a second screening result, and a third screening result, respectively.

[0246] The first screening result is a data set composed of test results extracted based on the first model and the second model. By using the used test model as the screening condition, it is screened whether the test results of the first model and the second model under the same test parameter combination are both successful. If there are unsuccessful cases, the reason for the inconsistency can be determined through this screening strategy.

[0247] The second screening result is based on the occurrence of memory inconsistency, extracting a data set consisting of test results of memory inconsistency. In this screening method, only test results that fail the test are retained.

[0248] The third screening result is to screen the test results based on the test role played by the processing core, and extract the data set composed of the test results between different processing cores when they act as tester processing cores and checker processing cores and another processing core. This screening strategy mainly targets the test result characteristics of a specific processing core when it acts as different test roles.

[0249] Fig.10A flowchart of another multi-core consistency test method provided by an embodiment of the present application; optionally, in step S801, a screening strategy of at least one dimension is adopted to perform data screening on the test results corresponding to each group of test parameter combinations to obtain the screening results under each dimension, which may include:

[0250] S901. Screen the test results corresponding to each group of test parameter combinations according to the type of the adopted test model to obtain a first screening result.

[0251] Optionally, the test results corresponding to each group of test parameter combinations may be screened according to the type of the adopted test model, and the test results under the first model and the test results under the second model may be extracted to form a first screening result.

[0252] S902. Screen the test results corresponding to each group of test parameter combinations according to whether the test results are successful or not, and obtain a second screening result.

[0253] According to the memory consistency verification result indicated by the test result, the test results corresponding to each group of test parameter combinations are screened, and the test results whose memory consistency verification results indicated by the test result fail are extracted to form a second screening result.

[0254] S903 . Screen the test results corresponding to each group of test parameter combinations according to the processing core type of each processing core to obtain a third screening result.

[0255] According to the processing core type of each processing core participating in the test, that is, the test role played by the processing core (inspector processing core or tester processing core), different processing cores acting as tester processing cores or inspector processing cores are extracted, and the test results between them and another processing core form a third screening result.

[0256] Fig.11 A flowchart of another multi-core consistency test method provided by an embodiment of the present application; Optionally, in step S802, performing data fusion analysis according to the screening results under each dimension to obtain consistency test results between each processing core may include:

[0257] S1001. Merge the first screening result and the second screening result to obtain a first arrangement set of memory inconsistent result data sets under different test models.

[0258] By fusing the first screening result and the second screening result, a first permutation set of memory inconsistency result data sets under the first model and the second model can be obtained. That is, the first permutation set may include memory inconsistency test results caused by different test models.

[0259] S1002. Generate a first result distribution graph according to the first permutation set; the first result distribution graph is a distribution graph used to indicate reasons for memory inconsistency under different test models.

[0260] Based on the first arrangement set, data analysis and processing may be further performed to obtain a first result distribution graph, which is a multidimensional distribution graph indicating reasons for memory inconsistency under different test models.

[0261] S1003. Merge the first screening result and the third screening result to obtain a second arrangement set of result data sets between different processing cores under different test models.

[0262] By fusing the first screening result with the third screening result, a second arrangement set of result data sets between different processing cores under the first model and the second model can be obtained.

[0263] S1004. Generate a second result distribution graph according to the second arrangement set; the second result distribution graph is used to indicate the consistency of processing cores in different clusters under different test models.

[0264] Similarly, according to the second permutation set, the data in the second permutation set is analyzed and processed to obtain a second result distribution graph, which indicates a distribution graph of memory consistency of processing cores in different clusters under different test models.

[0265] S1005 , the second screening result and the third screening result are merged to obtain a third arrangement set of result data sets of memory inconsistencies between different processing cores, the tester processing core and the checker processing core.

[0266] By fusing the second screening result with the third screening result, a third arrangement set of memory inconsistency result data sets between different processing cores, the tester processing core and the checker processing core, can be obtained.

[0267] S1006. Generate a third result distribution graph according to the third arrangement set; the third result distribution graph is used to indicate the corresponding memory inconsistency under the processing core perspective of each tester or the processing core perspective of each inspector.

[0268] Based on a processing method similar to the above, a third result distribution graph may be generated according to the third arrangement set, and the third result distribution graph indicates a memory inconsistency distribution graph from the perspective of each tester's processing core or the perspective of the checker's processing core.

[0269] It is worth noting that the permutation set and distribution graph are actually different ways of displaying the results of memory inconsistency. By converting the permutation set into a distribution graph for display, you can more clearly observe the causes of memory inconsistency under different focus points.

[0270] S1007, performing quantization processing according to the first result distribution graph, the second result distribution graph and the third result distribution graph, obtaining the relationship between the memory inconsistent data results between the two processing cores and each test parameter, and generating a consistency test result file between the processing cores.

[0271] In some embodiments, based on the obtained first result distribution graph, second result distribution graph and third result distribution graph, quantitative processing can be performed to obtain a relationship table between the consistency data results between any two processing cores and the test parameters set by the tester. Finally, through an automated script, the first result distribution graph, the second result distribution graph and the third result distribution graph and the quantitative results can be integrated into a complete file, such as a PDF file, to form a tester-readable result report.

[0272] Among them, quantifying the result distribution graph means converting the visual information in the distribution graph (such as the height of a bar graph, the size of a pie chart sector, etc.) into specific numerical data for more in-depth analysis and comparison.

[0273] Optionally, you can specify what specific numerical information you want to obtain from the distribution map. Then extract the data from the distribution map, clean and organize the data, and organize the data into a format that is easy to analyze, such as a table or database. Based on the analysis goals, calculate the required quantitative indicators. Use the quantitative data for more in-depth analysis.

[0274] It should be noted that the results of quantitative processing may be affected by factors such as the accuracy of the distribution map, the data extraction method and the selection of quantitative indicators.

[0275] Optionally, in step S1002, generating a first result distribution map according to the first permutation set may include: performing differential processing and model construction on the first permutation set according to memory attribute information and software consistency information of the tester core and the checker core in the first permutation set to obtain the first result distribution map.

[0276] In some embodiments, the test results in the first permutation set may be differentially processed for the case where the tester processing core and the checker processing core have the same memory attributes and software consistency.

[0277] Optionally, the test results of the tester's processing core and the checker's processing core with the same memory attributes and software consistency can be compared to calculate the difference value, which can include key indicators such as memory usage, access speed, error rate, etc.

[0278] Next, a model is constructed for the first permutation set based on the result after differential processing. The data set information model of the first permutation set can be defined according to the test objectives and data characteristics. The information model may include data attributes, relationships, constraints, etc. The differential data is organized according to the information model, and data structures such as data tables and relationship diagrams are established. The organized data is verified to ensure the correctness and consistency of the data.

[0279] Then, according to the test objectives and data characteristics, select appropriate dimensions for multidimensional analysis. Dimensions can include test environment, test time, test type, memory attributes, etc. Aggregate the differentiated data and calculate the statistical values ​​under each dimension. Statistical values ​​can include mean, standard deviation, maximum, minimum, etc. Use data visualization tools (such as Excel, Tableau, Power BI, etc.) to draw multidimensional distribution graphs. Multidimensional distribution graphs can include but are not limited to bar charts, line charts, scatter plots, heat maps, etc. Mark the causes and distribution of memory inconsistencies in the graph.

[0280] Optionally, in step S1004, generating a second result distribution map according to the second permutation set may include: performing differentiation and model construction on the second permutation set according to cluster information of each processing core in the second permutation set to generate the second result distribution map.

[0281] Optionally, the second permutation set is differentiated and modeled in the scenario where the processing cores in the second permutation set are in different clusters or the same cluster. The specific data differentiation and modeling process can refer to the processing of the first permutation set, which will not be repeated here.

[0282] Optionally, in step S1006, generating a third result distribution map according to the third arrangement set may include: fusing data in the third arrangement set according to memory inconsistency information between each tester core and other checker cores in the third arrangement set to generate the third result distribution map.

[0283] In some embodiments, the inconsistent results of different tester processing cores and multiple inspector processing cores in the third arrangement set are fused to produce a corresponding inconsistency distribution map from the perspective of each tester processing core or the inspector processing core, that is, a third result distribution map.

[0284] It is worth noting that the above process of performing data differentiation and model construction or data fusion based on the obtained permutation set and generating a distribution graph is to achieve the conversion of the data format, and finally convert the analysis results into the form of a distribution graph for display, so that the tester can more clearly understand the cause of memory inconsistency. The specific conversion method or processing method can be implemented by referring to the existing technology.

[0285] The multi-core consistency test method provided by this method includes three stages: the test program creation and deployment stage, the consistency test stage, and the test result analysis and display stage. The tester only needs to complete the confirmation of the basic test parameter value range in the early stage to generate a multi-dimensional and comprehensive memory consistency analysis result, which greatly improves the verification efficiency compared with the existing scheme; and through the analysis and display of big data, a comprehensive understanding and analysis of memory consistency issues can be achieved, and the reasons for certain phenomena in memory consistency of current heterogeneous software can be quickly determined. Overall, this method not only optimizes the development and deployment process, but also improves the efficiency of problem analysis and resolution, which is of great significance to promoting the depth and breadth of memory consistency analysis.

[0286] In summary, the multi-core consistency test method provided by this embodiment includes: determining multiple test parameters and the value range of each test parameter according to the test requirements of the device under test; generating multiple groups of test parameter combinations according to the value range of each test parameter, each group of test parameter combinations contains each test parameter and a value of the test parameter; creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple groups of test parameter combinations, and deploying the test program corresponding to each processing core to each processing core; running the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations, and obtains the test results corresponding to each group of test parameter combinations; according to the test results corresponding to each group of test parameter combinations, analyzing and obtaining the consistency test results between each processing core. This method can set the test parameters and the value range of the test parameters based on the test requirements, so as to perform iterative processing according to the value range of the test parameters to generate a test parameter combination that can fully cover more test scenarios, so as to perform consistency test verification based on the test parameter combination, which can improve the comprehensiveness and accuracy of the test results.

[0287] In addition, through automated data fusion and analysis, the test results can be screened and integrated from different perspectives to achieve a comprehensive understanding and analysis of memory inconsistency issues. This can quickly and accurately determine the causes of certain memory consistency issues in current heterogeneous software, thereby improving the efficiency of problem analysis and resolution.

[0288] The following describes the apparatus, device, storage medium, etc. used to execute the multi-core consistency test method provided in this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0289] Fig.12Schematic diagram of a multi-core consistency test device provided in an embodiment of the present application, the functions implemented by the multi-core consistency test device correspond to the steps performed by the above method. The device can be a device deployed in the above multi-core consistency test system. Fig.12 As shown, the apparatus may include: a determination module 120, a generation module 121, a deployment module 122, a testing module 123, and an analysis module 124;

[0290] A determination module 120, configured to determine a plurality of test parameters and a value range of each test parameter according to the test requirements of the device under test;

[0291] A generating module 121, for generating a plurality of test parameter combinations according to the value range of each test parameter, each test parameter combination including each test parameter and a value of the test parameter;

[0292] A deployment module 122, for creating a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple test parameter combinations, and deploying the test program corresponding to each of the processing cores to each of the processing cores;

[0293] The test module 123 is used to run the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations, and obtains the test results corresponding to each group of test parameter combinations;

[0294] The analysis module 124 is used to analyze and obtain consistency test results between the processing cores according to the test results corresponding to each group of test parameter combinations.

[0295] Optionally, the generating module 121 is specifically configured to determine the number of processing core combinations according to a value range of a parameter representing the number of processing cores in the plurality of test parameters, wherein the processing core combination includes a plurality of processing cores;

[0296] Determine the number of parameter combinations that can be generated under the specified test parameters according to the value range of each test parameter, wherein the parameter combination includes: a value of multiple test parameters;

[0297] Determine iteration constraint information according to the number of processing core combinations and the number of parameter combinations;

[0298] According to the iteration constraint information and the value range of each test parameter, multiple groups of test parameter combinations are iteratively generated.

[0299] Optionally, the generating module 121 is specifically used to traverse each test parameter in each processing core, determine the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generate at least one set of test parameter combination corresponding to each iteration round;

[0300] In each iteration round, it is determined whether to stop the iteration according to the iteration constraint information. If so, each group of test parameter combinations currently generated is used as multiple groups of test parameter combinations.

[0301] Optionally, the generating module 121 is specifically configured to traverse various values ​​of the current test parameter according to the value range of the current test parameter for the current test parameter in the current processing core of the current iteration round traversed;

[0302] For the current value of the current test parameter traversed, determine whether the current value is the maximum value in the value range of the current test parameter;

[0303] If yes, a set of test parameter combinations is generated based on the current values, and the next test parameter of the current test parameter in the current processing core is traversed;

[0304] If not, a set of test parameter combinations is generated based on the current value, and the next value of the current value is traversed.

[0305] Optionally, the generating module 121 is specifically configured to determine, in a current iteration round, a total number of test parameter combinations generated in the current iteration round and all rounds before the current iteration round;

[0306] If the total number satisfies the iteration constraint information, it is determined to stop the iteration.

[0307] Optionally, the deployment module 122 is specifically configured to determine a parameter representing the number of processing cores from the test parameters, and determine the number of test programs to be created according to a value range of the parameter representing the number of processing cores;

[0308] Configure the corresponding relationship between each processing core involved in the test and each test program;

[0309] According to each group of test parameter combinations, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program, a test program corresponding to each processing core participating in the test is created.

[0310] Optionally, the deployment module 122 is specifically configured to deploy the test program corresponding to each processing core to each processing core, including:

[0311] Generate image files through hybrid heterogeneous deployment tools based on the test software corresponding to each processing core and the preset startup program;

[0312] The image file is loaded, and the test program corresponding to each processing core is deployed to each processing core based on the startup program.

[0313] Optionally, the test module 123 is specifically configured to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core according to each group of test parameter combinations, using the first test model, and generate test results corresponding to each group of test parameter combinations under the first test model;

[0314] According to each group of test parameter combinations, the second test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate corresponding test results for each group of test parameter combinations under the second test model.

[0315] Optionally, the analysis module 124 is specifically configured to adopt a screening strategy of at least one dimension to screen the test results corresponding to each group of test parameter combinations to obtain screening results under each dimension;

[0316] Data fusion analysis is performed based on the screening results in each dimension to obtain the consistency test results between each processing core.

[0317] Optionally, the filtering results under each dimension include: a first filtering result, a second filtering result, and a third filtering result; the first filtering result is used to indicate a data set consisting of test results under different test models; the second filtering result is used to indicate a data set consisting of test results of inconsistent memories of each processing core; the third filtering result is used to indicate a data set consisting of test results when the processing core is in the tester processing core or in the checker processing core.

[0318] Optionally, the analysis module 124 is specifically used to screen the test results corresponding to each group of test parameter combinations according to the type of the adopted test model to obtain a first screening result;

[0319] According to the success or failure of the test result, the test results corresponding to each group of test parameter combinations are screened to obtain a second screening result;

[0320] According to the processing core type of each processing core, the test results corresponding to each group of test parameter combinations are screened to obtain a third screening result.

[0321] Optionally, the analysis module 124 is specifically used to merge the first screening result with the second screening result to obtain a first arrangement set of memory inconsistent result data sets under different test models;

[0322] Generate a first result distribution graph according to the first permutation set; the first result distribution graph is used to indicate a distribution graph of reasons for memory inconsistency under different test models;

[0323] The first screening result and the third screening result are merged to obtain a second arrangement set of result data sets between different processing cores under different test models;

[0324] Generating a second result distribution graph according to the second arrangement set; the second result distribution graph is used to indicate the consistency of processing cores in different clusters under different test models;

[0325] The second screening result and the third screening result are merged to obtain a third arrangement set of result data sets of memory inconsistencies between different processing cores, where the tester processing core and the checker processing core have memory inconsistencies;

[0326] Generate a third result distribution graph according to the third arrangement set; the third result distribution graph is used to indicate the memory inconsistency corresponding to the processing core angle of each tester or the processing core angle of each inspector;

[0327] According to the first result distribution graph, the second result distribution graph and the third result distribution graph, quantitative processing is performed to obtain the relationship between the inconsistent data results of the memory between the two processing cores and each test parameter, and a consistency test result file between the processing cores is generated.

[0328] Optionally, the analysis module 124 is specifically configured to perform differential processing and model building on the first permutation set according to the memory attribute information and software consistency information of the tester core and the checker core in the first permutation set to obtain a first result distribution graph.

[0329] Optionally, the analysis module 124 is specifically configured to perform differentiation and model building on the second arrangement set according to cluster information of each processing core in the second arrangement set, so as to generate a second result distribution graph.

[0330] Optionally, the analysis module 124 is specifically configured to fuse the data in the third arrangement set according to the memory inconsistency information between each tester core and other checker cores in the third arrangement set to generate a third result distribution graph.

[0331] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0332] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0333] The above modules can be connected or communicated with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, a ZigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. Those skilled in the art will clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.

[0334] Fig.13 A structural schematic diagram of an electronic device provided in an embodiment of the present application, the device may be a computing device with data processing function, and the device may be a device in the above-mentioned multi-core consistency test system.

[0335] The device may include: a processor 801 and a storage medium 802 .

[0336] The storage medium 802 is used to store programs, and the processor 801 calls the programs stored in the storage medium 802 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0337] Among them, the storage medium 802 stores program code, and when the program code is executed by the processor 801, the processor 801 executes various steps in the multi-core consistency testing method according to various exemplary embodiments of the present application described in the above "Exemplary Method" section of this specification.

[0338] Processor 801 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor can be executed.

[0339] Storage medium 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Storage medium may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type storage medium, random access storage medium (Random Access Memory, RAM), static random access storage medium (Static Random Access Memory, SRAM), programmable read-only storage medium (Programmable Read Only Memory, PROM), read-only storage medium (Read Only Memory, ROM), electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic storage medium, disk, optical disk, etc. Storage medium is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The storage medium 802 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0340] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0341] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0342] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0343] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0344] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only storage medium (English: Read-Only Memory, referred to as: ROM), random access storage medium (English: Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program code.

Claims

1. A multi-core consistency testing method, characterized in that: include: Determine multiple test parameters and the value range of each test parameter according to the test requirements of the device under test; Generate multiple test parameter combinations according to the value range of each test parameter, each test parameter combination includes each of the test parameters and a value of the test parameter; Creating, according to the plurality of test parameter combinations, a test program corresponding to each of the plurality of processing cores participating in the test in the device under test, and deploying the test program corresponding to each of the processing cores to each of the processing cores; Running a test program on each processing core, wherein the test program controls the corresponding processing core to perform consistency test verification according to each set of test parameter combinations, and obtains a test result corresponding to each set of test parameter combinations; According to the test results corresponding to each group of test parameter combinations, the consistency test results between the processing cores are analyzed and obtained.

2. The method according to claim 1, characterized in that: The generating of multiple test parameter combinations according to the value range of each test parameter includes: Determining the number of processing core combinations according to a value range of a parameter representing the number of processing cores in the multiple test parameters, wherein the processing core combination includes multiple processing cores; Determine the number of parameter combinations that can be generated under the specified test parameters according to the value range of each test parameter, wherein the parameter combination includes: a value of multiple test parameters; Determining iteration constraint information according to the number of processing core combinations and the number of parameter combinations; According to the iteration constraint information and the value range of each test parameter, multiple groups of test parameter combinations are iteratively generated.

3. The method according to claim 2, characterized in that The iterative generation of multiple groups of test parameter combinations according to the iteration constraint information and the value range of each test parameter includes: Traversing each test parameter in each processing core, determining the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generating at least one set of test parameter combination corresponding to each iteration round; In each iteration round, it is determined whether to stop the iteration according to the iteration constraint information. If so, each group of test parameter combinations currently generated is used as the multiple groups of test parameter combinations.

4. The method according to claim 3, characterized in that: The traversing each test parameter in each processing core, determining the combination mode of each processing core under different values ​​of each test parameter in each iteration round according to the value range of each test parameter, and generating at least one group of test parameter combinations corresponding to each iteration round, includes: For a current test parameter in a current processing core of a current iteration round, traverse each value of the current test parameter according to a value range of the current test parameter; For the current value of the current test parameter traversed, determine whether the current value is the maximum value in the value range of the current test parameter; If yes, generate a set of test parameter combinations according to the current value, and traverse the next test parameter of the current test parameter in the current processing core; If not, a set of test parameter combinations is generated according to the current value, and the next value of the current value is traversed.

5. The method according to claim 3, characterized in that: In each iteration round, determining whether to stop iteration according to the iteration constraint information includes: In a current iteration round, determining a total number of test parameter combinations generated in the current iteration round and all rounds before the current iteration round; If the total number satisfies the iteration constraint information, it is determined to stop the iteration.

6. The method according to claim 1, characterized in that The step of creating a test program corresponding to each of the plurality of processing cores participating in the test in the device under test according to the plurality of groups of test parameter combinations includes: Determine a parameter representing the number of processing cores from the test parameters, and determine the number of test programs to be created according to a value range of the parameter representing the number of processing cores; Configure the corresponding relationship between each processing core involved in the test and each test program; According to each group of test parameter combinations, the number of test programs to be created, and the correspondence between each processing core participating in the test and each test program, a test program corresponding to each processing core participating in the test is created.

7. The method according to claim 1, characterized in that The step of deploying the test program corresponding to each processing core to each processing core includes: Generate image files through hybrid heterogeneous deployment tools based on the test software corresponding to each processing core and the preset startup program; The image file is loaded, and the test program corresponding to each processing core is deployed on each processing core based on the startup program.

8. The method according to claim 1, characterized in that: According to each group of test parameter combinations, controlling the corresponding processing core to perform consistency test verification to obtain the test results corresponding to each group of test parameter combinations includes: According to each group of test parameter combinations, the first test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate the test results corresponding to each group of test parameter combinations under the first test model; According to each group of test parameter combinations, the second test model is used to control the corresponding processing core to perform consistency test verification when it is in the tester processing core or the checker processing core, and generate corresponding test results for each group of test parameter combinations under the second test model.

9. The method according to claim 8, characterized in that The analysis of the test results corresponding to each group of test parameter combinations to obtain the consistency test results between the processing cores includes: Using at least one dimension of screening strategy, data screening is performed on the test results corresponding to each group of test parameter combinations to obtain screening results under each dimension; Data fusion analysis is performed based on the screening results in each dimension to obtain the consistency test results between each processing core.

10. The method according to claim 9, characterized in that The screening results under each dimension include: a first screening result, a second screening result and a third screening result; the first screening result is used to indicate a data set consisting of test results under different test models; the second screening result is used to indicate a data set consisting of test results of inconsistent memories of each processing core; the third screening result is used to indicate a data set consisting of test results when the processing core is in the tester processing core or in the checker processing core.

11. The method according to claim 10, characterized in that The screening strategy of at least one dimension is adopted to screen the test results corresponding to each group of test parameter combinations to obtain the screening results under each dimension, including: According to the type of the adopted test model, the test results corresponding to each group of test parameter combinations are screened to obtain the first screening result; According to the success or failure of the test result, the test results corresponding to each group of test parameter combinations are screened to obtain the second screening result; According to the processing core type of each processing core, the test results corresponding to each group of test parameter combinations are screened to obtain the third screening result.

12. The method according to claim 10, characterized in that The data fusion analysis is performed according to the screening results under each dimension to obtain the consistency test results between the processing cores, including: The first screening result and the second screening result are merged to obtain a first arrangement set of memory inconsistent result data sets under different test models; Generate a first result distribution graph according to the first permutation set; the first result distribution graph is used to indicate a distribution graph of reasons for memory inconsistency under different test models; The first screening result and the third screening result are merged to obtain a second arrangement set of result data sets between different processing cores under different test models; generating a second result distribution graph according to the second arrangement set; the second result distribution graph is used to indicate the consistency of processing cores in different clusters under different test models; The second screening result and the third screening result are merged to obtain a third arrangement set of result data sets of memory inconsistencies between different processing cores, the tester processing core and the checker processing core; Generate a third result distribution graph according to the third arrangement set; the third result distribution graph is used to indicate the memory inconsistency corresponding to the processing core angle of each tester or the processing core angle of each inspector; According to the first result distribution diagram, the second result distribution diagram and the third result distribution diagram, quantitative processing is performed to obtain the relationship between the inconsistent data results of the memory between the two processing cores and each test parameter, and a consistency test result file between the processing cores is generated.

13. The method according to claim 12, characterized in that Generating a first result distribution graph according to the first arrangement set includes: According to the memory attribute information and software consistency information of the tester core and the checker core in the first arrangement set, differential processing and model construction are performed on the first arrangement set to obtain the first result distribution map.

14. The method according to claim 12, characterized in that Generating a second result distribution graph according to the second arrangement set includes: According to the cluster information of each processing core in the second arrangement set, the second arrangement set is differentiated and a model is constructed to generate the second result distribution map.

15. The method according to claim 12, characterized in that Generating a third result distribution graph according to the third permutation set includes: According to the memory inconsistency information between each tester core and other checker cores in the third arrangement set, the data in the third arrangement set is merged to generate the third result distribution map.

16. A multi-core consistency testing device, characterized in that: include: Identify modules, generate modules, deploy modules, test modules, and analyze modules; The determination module is used to determine multiple test parameters and the value range of each test parameter according to the test requirements of the device under test; The generating module is used to generate multiple test parameter combinations according to the value range of each test parameter, each test parameter combination including each test parameter and a value of the test parameter; The deployment module is used to create a test program corresponding to each of the multiple processing cores participating in the test in the device under test according to the multiple groups of test parameter combinations, and deploy the test program corresponding to each processing core to each processing core; The test module is used to run the test program on each processing core, and the test program controls the corresponding processing core to perform consistency test verification according to each group of test parameter combinations to obtain the test results corresponding to each group of test parameter combinations; The analysis module is used to analyze and obtain consistency test results between the processing cores according to the test results corresponding to each group of test parameter combinations.

17. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the multi-core consistency testing method as described in any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the multi-core consistency testing method according to any one of claims 1 to 15 is implemented.

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