Data write method and memory controller

Abstract

The application provides a memory controller and a data writing method. The data writing method comprises: obtaining and storing a first instruction sequence comprising a plurality of write instructions into a buffer memory; determining a plurality of first write instructions satisfying a preset condition according to first information and second information of the write instructions; arranging the plurality of first write instructions in ascending order to form a second instruction sequence; and sequentially executing each first write instruction according to the second instruction sequence to write sequential write data into a rewritable non-volatile memory module. In this way, the plurality of write data corresponding to the sequential write instructions can be sequentially written into the rewritable non-volatile memory module, so as to effectively perform the sequential write operation required by the host system, thereby reducing the random write operation caused by multi-threading and improving the overall data access capability of the storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and in particular, to a data write method for a non-volatile memory and a memory controller using the same. BACKGROUND

[0002] A non-volatile memory module storage device is a slave device that needs to be sent a command by a host system to process data. In order to improve performance, the operating system of the host system introduces a multi-threading technique.

[0003] However, the multi-threading technique causes the write commands sent by the host system to the non-volatile memory module storage device to be executed randomly, and the performance of the non-volatile memory module storage device decreases when processing random writes.

[0004] Therefore, there is an urgent need for a memory controller and a data write method to solve the above problems. SUMMARY

[0005] The present application aims to solve the above problems and avoid write data that should be written using sequential write data from becoming written using a random write operation (non-sequential write operation) due to multiple processing threads.

[0006] One or more embodiments of the present disclosure provide a data write method applied to control a storage device configured with a rewritable non-volatile memory module. The storage device includes a memory interface control circuit coupled to the rewritable non-volatile memory module, a buffer memory, and a processor coupled to the memory interface control circuit and the buffer memory, wherein the processor is further coupled to a connection interface circuit of the storage device to be coupled to a host system, the method includes: obtaining and storing a first instruction sequence to the buffer memory, wherein the first instruction sequence includes a plurality of write instructions, each of the write instructions includes first information and second information, the first information includes a sequential tag used to indicate a thread number of the corresponding write instruction, and the second information includes a logical address and a data size; determining a plurality of first write instructions satisfying a predetermined condition from the plurality of write instructions according to the first information and the second information, wherein the plurality of first write instructions respectively correspond to a plurality of first write data obtained by dividing sequential write data; obtaining the plurality of first write instructions and arranging the plurality of first write instructions in ascending order to form a second instruction sequence, wherein a first arrangement order of the plurality of first write instructions in the first instruction sequence is different from a second arrangement order of the plurality of first write instructions in the second instruction sequence; and sequentially executing the plurality of first write instructions according to the second instruction sequence to write the sequential write data to the rewritable non-volatile memory module.

[0007] In an embodiment of the present disclosure, wherein the step of arranging the plurality of first write instructions in ascending order to form the second instruction sequence includes: obtaining a first instruction and a second instruction from the plurality of first write instructions, wherein the first instruction corresponds to a first logical address and the second instruction corresponds to a second logical address; arranging the first instruction and the second instruction in ascending order according to the first logical address and the second logical address to obtain a second sub-instruction sequence; sequentially obtaining remaining write instructions and updating the second sub-instruction sequence according to the logical addresses corresponding to the remaining write instructions until each of the first write instructions in the plurality of first write instructions is obtained to obtain the second instruction sequence, wherein the remaining write instructions are one or more of the first write instructions in the plurality of first write instructions that are not arranged in ascending order, and the remaining write instructions include one or more.

[0008] In an embodiment of the present application, the remaining write instructions include a third instruction corresponding to a third logical address, when the second logical address is greater than the first logical address, the remaining write instructions are sequentially obtained, and the step of updating the second instruction sequence according to the logical address corresponding to the remaining write instructions includes: if the third logical address is greater than the second logical address, inserting the third instruction at the end of the second instruction sequence to obtain a third instruction sequence; if the third logical address is less than the first logical address, inserting the third instruction at the beginning of the second instruction sequence to obtain the third instruction sequence; and if the third logical address is greater than the first logical address and less than the second logical address, inserting the third instruction between the first instruction and the second instruction to obtain the third instruction sequence.

[0009] In an embodiment of the present application, the step of obtaining and storing the first instruction sequence to the buffer memory includes: obtaining the write instructions from the host system, wherein the write instructions are sent by a plurality of processing threads of the host system respectively; forming the first instruction sequence according to the receiving time of the write instructions; and storing the first instruction sequence to the buffer memory.

[0010] In an embodiment of the present application, the method further includes removing the first write instructions obtained from the first instruction sequence, and executing the second instruction sequence to write the sequential write data corresponding to the sequential write instructions to the rewritable non-volatile memory module.

[0011] In an embodiment of the present application, the step of determining the first write instructions satisfying the preset condition from the write instructions according to the first information and the second information includes: identifying the thread number of each write instruction according to the first information; identifying the logical address and the data size of each write instruction according to the second information; and determining the first write instructions satisfying the preset condition according to the thread number, the logical address and the data size, wherein the preset condition includes that the logical addresses of the first write instructions are continuous, the first thread numbers of the first write instructions sorted according to the logical addresses are continuous and in ascending order, and the sum of the first write data sizes corresponding to the first write instructions is the same as a predetermined stored data size.

[0012] In an embodiment of the present application, wherein the thread numbers corresponding to the plurality of first write instructions in the second instruction sequence are consecutive and arranged in ascending order, the sum of the data sizes corresponding to the plurality of first write instructions in the second instruction sequence is the predetermined stored data size, and the first logical addresses corresponding to the plurality of first write instructions in the second instruction sequence are consecutive.

[0013] In an embodiment of the present application, wherein the step of sequentially executing the plurality of first write instructions according to the second instruction sequence to write the sequential write data to the rewritable non-volatile memory module comprises setting a sequence status register according to the second arrangement order to indicate the host system to perform a sequential write operation in the second arrangement order.

[0014] In an embodiment of the present application, wherein the step of obtaining the plurality of first write instructions comprises judging whether the plurality of first write instructions allow an overwrite write operation, wherein if the write operation is allowed to be overwritten, the plurality of first write instructions are not obtained; and if the write operation is not allowed to be overwritten, the plurality of first write instructions are obtained and the ascending arrangement is performed on the plurality of first write instructions to obtain the second instruction sequence.

[0015] One or more embodiments of the present application further provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes a memory interface control circuit coupled to the rewritable non-volatile memory module, a buffer memory, and a processor. The processor is coupled to the memory interface control circuit and the buffer memory, and further coupled to a connection interface circuit of the storage device for coupling to a host system. The processor is configured to: acquire and store a first instruction sequence to the buffer memory, wherein the first instruction sequence includes a plurality of write instructions, each of the write instructions includes first information and second information, the first information includes a sequential flag for indicating a thread number of a corresponding write instruction, and the second information includes a logical address and a data size; determine a plurality of first write instructions satisfying a predetermined condition from the plurality of write instructions according to the first information and the second information, wherein the plurality of first write instructions respectively correspond to first write data obtained by splitting sequential write data; acquire the plurality of first write instructions and arrange the plurality of first write instructions in ascending order to form a second instruction sequence, wherein a first arrangement order of the plurality of first write instructions in the first instruction sequence is different from a second arrangement order of the plurality of first write instructions in the second instruction sequence; and sequentially execute the plurality of first write instructions according to the second instruction sequence to write the sequential write data to the rewritable non-volatile memory module.

[0016] Based on the above, the memory controller and the data write method used by the embodiments of the present application can actively reorder the plurality of write instructions acquired by the plurality of threads of the host system when the plurality of write instructions corresponding to the sequential write instructions are not sequentially issued, and perform a sequential write operation according to the arrangement order of the reordered plurality of write instructions. In this way, the problem that the conventional storage device and the memory controller cannot perform the sequential write operation expected by the host system can be solved, and the plurality of write data corresponding to the sequential write instructions can be sequentially written into the rewritable non-volatile memory module, so that the sequential write operation required by the host system can be effectively performed, thereby reducing the random write operation caused by the plurality of threads and improving the overall data access capability of the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1Block diagram of a host system and a storage device according to an embodiment of the present invention;

[0019] Figure 2 Flowchart of a data write method according to an embodiment of the present invention;

[0020] Figure 3 Diagram of dispatching sequential write data of sequential write instructions to multiple processing threads;

[0021] Figure 4 Diagram of updating a first instruction sequence according to multiple write instructions obtained from multiple processing threads of a host system according to an embodiment of the present invention;

[0022] Figure 5 Diagram of performing a data write operation according to a first instruction sequence according to an embodiment of the present invention;

[0023] Figure 6 Diagram of performing a sequential write operation according to reordered multiple write instructions of corresponding sequential write instructions according to an embodiment of the present invention;

[0024] Figure 7 Diagram of a reordering operation according to an embodiment of the present invention;

[0025] Figure 8 Diagram of performing a sequential write operation via treating write data corresponding to reordered multiple write instructions as sequential write data according to another embodiment of the present invention;

[0026] Figure 9 Diagram of performing a sequential write operation according to a first instruction sequence having reordered multiple write instructions according to an embodiment of the present invention.

[0027] BRIEF DESCRIPTION OF DRAWINGS

[0028] 10: host system

[0029] 20: storage device

[0030] 110, 211: processor

[0031] 120: host memory

[0032] 130: data transfer interface circuitry

[0033] 210: memory controller

[0034] 212: data management circuitry

[0035] 213: memory interface control circuitry

[0036] 214: buffer memory

[0037] 220: rewritable non-volatile memory module

[0038] 230: connection interface circuit

[0039] S210, S220, S230, S240, S250, S260: flow steps of data writing method

[0040] D31, D81: sequentially written data

[0041] D311-D314: first written data

[0042] D411: written data

[0043] A31, A311, A312, A313, A314: arrows

[0044] A41, A42, A43, A44: arrows

[0045] A6, A42, A43, A44: arrows

[0046] OQ(1), OQ(2), OQ(3), OQ(4), OQ(5), OQ(6): instruction sequences

[0047] T1, T2, T3, T4, T5: time points

[0048] R51, R52, R53, R54, R55: instruction acquisition

[0049] W51, W52, W53, W54, W55: write operations

[0050] R61, R62, R63, R64: instruction acquisition

[0051] W61, W62, W63, W64: write operations

[0052] R71, R72, R73, R74: instruction acquisition

[0053] A6, A7, A81, A9: arrows

[0054] W81: write operation

[0055] W91, W92, W93, W94, W95: write operations DETAILED DESCRIPTION

[0056] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0057] Figure 1 A block diagram of a host system and a storage device according to an embodiment of the present application is shown. Referring to Figure 1 The host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 and a host memory 120, a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are coupled to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0058] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220 and a connection interface circuit 230. The storage controller 210 includes a processor 211, a data management circuit 212 and a memory interface control circuit 213.

[0059] In this embodiment, the host system 10 is coupled to the storage device 20 through the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0060] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be coupled to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board can also be coupled to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like via a system bus.

[0061] In the present embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuit 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0062] In addition, in another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0063] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. However, it must be understood that the present application is not limited thereto, and the host memory 120 can also be other suitable memory.

[0064] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware or firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0065] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operated, the control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in the present embodiment, the control instructions / program codes can also be executed to perform instruction scheduling operations to implement the instruction scheduling method provided by the present application. The control instructions / program codes corresponding to the instruction scheduling method can also be implemented as a circuit unit in hardware form to implement the instruction scheduling method provided by the present application.

[0066] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, and the present application is not limited thereto.

[0067] In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0068] The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to accept instructions from the processor 211 to perform data transfer. For example, data is fetched from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the fetched data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). The fetched data can also be temporarily stored in the buffer memory 214. For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0069] The memory interface control circuit 213 is configured to accept instructions from the processor 211 to perform write (also referred to as programming), read, or erase (also referred to as erasure) operations on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0070] In addition, data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 sends corresponding instruction sequences to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform corresponding operations. For example, the instruction sequences can include write instruction sequences (also referred to as write instructions) to instruct writing of data, read instruction sequences (also referred to as read instructions) to instruct reading of data, erase instruction sequences (also referred to as erase instructions) to instruct erasing of data, and corresponding instruction sequences to instruct various memory operations. The instruction sequences can include one or more signals, or data on a bus. The signals or data can include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, a physical address, etc. is included.

[0071] In one embodiment, the memory controller 210 further comprises a buffer memory 214. The buffer memory 214 is coupled to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220 or other system data (e.g., instruction sequences storing various instructions) for managing the storage device 20 so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 214.

[0072] The rewritable non-volatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used to store data written by the host system 10.

[0073] Figure 2 A flowchart of a data write method according to an embodiment of the present application is shown. Please refer to FIG. 2. Figure 2 As shown in FIG. 2, the steps of the data write method specifically include: Figure 2

[0074] In step S210, the processor 211 obtains a first instruction sequence from the host system and stores the first instruction sequence to the buffer memory, wherein the first instruction sequence comprises a plurality of write instructions, each of the write instructions comprises first information and second information, the first information comprises a sequential tag indicating a thread number of the write instruction corresponding to the write instruction, and the second information comprises a logical address and a data size.

[0075] In the present embodiment, the processor 110 comprises a plurality of processing threads (Threads) capable of parallel operation, each of which can independently process data operations. In one embodiment, a sequential write data from the host system 10 can be written into the storage device 20 by issuing a sequential write instruction to the storage device 20.

[0076] In addition, in order to speed up the related operations and resource allocation of the sequential write data, the processor 110 can process the data of multiple parts of the sequential write data in parallel through multiple processing threads. That is, the processor 110 can divide the sequential write data into multiple write data and assign them to multiple processing threads, so that the multiple processing threads issue write instructions to the storage device 20 after processing the write data they are responsible for, thereby writing the write data that the multiple processing threads are respectively responsible for processing.

[0077] In one embodiment, the processor obtains the plurality of write instructions from the host system, wherein the write instructions are respectively sent via a plurality of processing threads of the host system; forms the first instruction sequence according to the receiving time of the plurality of write instructions; and stores the first instruction sequence to the buffer memory. ​

[0078] Figure 3 An illustration of dispatching sequential write data of a sequential write instruction to multiple processing threads. For example, refer to Figure 3 In one embodiment, assume that the host system 10 wants the storage device 20 to write sequential write data D31 (the host system's 10 operating system has written this sequential write data at consecutive logical addresses), and the processor 110 has 4 processing threads 111-114. According to the number of processing threads 111-114, the sequential write data D31 is split into 4 pieces of first write data D311, D312, D313, D314.

[0079] Next, as shown by arrow A31, the 4 pieces of first write data D311, D312, D313, D314 and related metadata (e.g., logical addresses and data sizes) are dispatched by the processor 110 to the 4 processing threads 111-114 of the processor 110. That is, the processing thread 111 is responsible for generating a first write instruction C311 to write the first write data D311; the processing thread 112 is responsible for generating a first write instruction C312 to write the first write data D312; the processing thread 113 is responsible for generating a first write instruction C313 to write the first write data D313; and the processing thread 114 is responsible for generating a first write instruction C314 to write the first write data D314.

[0080] The host system 10 expects to want to write data that is sequential, but because of the multiple processing threads, and each processing thread has independence, the processor 110 cannot control whether the order of the instructions issued to the storage device 20 is in the expected order, resulting in the order of the write instructions of the host system 10 received by the storage device 20 not being the optimal sequential order (equivalent to the order of the locations of the first write data D311, D312, D313, D314 within the sequential write data D31).

[0081] Figure 4 An illustration of updating a first instruction sequence according to a plurality of write instructions obtained from a plurality of processing threads of a host system according to an embodiment of the present application. For example, refer to Figure 4, it is assumed that the processing thread 113 first sends the first write instruction C313 to the storage device 20, and the processor 211, upon obtaining the first write instruction C313, stores the first write instruction C313 in the first instruction sequence OQ(l). Next, as shown by an arrow A41, the processing thread 111 sends the first write instruction C311 to the storage device 20, and the processor 211, upon obtaining the first write instruction C311, stores the first write instruction C311 in the first instruction sequence OQ(l) to become the first instruction sequence OQ(2). Depending on the time of obtaining the first write instruction C311 and the time of obtaining the first write instruction C313, the processor 211 arranges the first write instruction C311 after the first write instruction C313.

[0082] Next, as shown by an arrow A42, the processing thread 114 sends the first write instruction C314 to the storage device 20, and the processor 211, upon obtaining the first write instruction C314, stores the first write instruction C314 in the first instruction sequence OQ(2) to become the first instruction sequence OQ(3). Depending on the time of obtaining the first write instruction C314 and the time of obtaining the first write instruction C311, the processor 211 arranges the first write instruction C314 after the first write instruction C311.

[0083] Next, as shown by an arrow A43, the processing thread 111 sends the write instruction C411 (not corresponding to the write instruction of the sequential write data D31) to the storage device 20, and the processor 211, upon obtaining the write instruction C411, stores the first write instruction C411 in the first instruction sequence OQ(3) to become the first instruction sequence OQ(4). Depending on the time of obtaining the first write instruction C411 and the time of obtaining the first write instruction C314, the processor 211 arranges the first write instruction C411 after the first write instruction C314.

[0084] Next, as shown by an arrow A44, the processing thread 112 sends the first write instruction C312 to the storage device 20, and the processor 211, upon obtaining the first write instruction C312, stores the first write instruction C312 in the first instruction sequence OQ(4) to become the first instruction sequence OQ(5). Depending on the time of obtaining the first write instruction C312 and the time of obtaining the first write instruction C411, the processor 211 arranges the first write instruction C312 after the first write instruction C411. Note that the above-described first instruction sequences OQ(l) to OQ(5) are stored and updated in the buffer memory 214.

[0085] Please return to Figure 2, and then, in step S220, a plurality of first write instructions satisfying a preset condition are determined from the plurality of write instructions according to the first information and the second information, wherein the plurality of first write instructions respectively correspond to first write data obtained by splitting the sequential write data.

[0086] In an embodiment, the step of determining the plurality of first write instructions satisfying the preset condition from the plurality of write instructions according to the first information and the second information comprises: identifying the thread number of each write instruction according to the first information; identifying the logical address and the data size of each write instruction according to the second information; and determining the plurality of first write instructions satisfying the preset condition according to the thread number, the logical address and the data size, wherein the preset condition comprises: the logical addresses of the plurality of first write instructions are continuous, the plurality of first thread numbers of the plurality of first write instructions sorted according to the logical addresses are continuous and arranged in ascending order, and the sum of the sizes of the first write data respectively corresponding to the plurality of first write instructions is the same as the predetermined stored data size.

[0087] For example, in the example of FIG. 6, the processor 211 can identify the number of each write instruction according to the first information, wherein the first information comprises a sequential mark indicating the thread number of the write instruction corresponding to the sequential write instruction, as shown in FIG. 6. Figure 4 Figure 4 According to the first information, the processor 211 can identify the thread numbers of the plurality of write instructions in the first instruction sequence OQ(5): C313, C311, C314, C411, C312, as shown in FIG. 6. The write instructions C313, C311, C314, C312 corresponding to the same sequential write instruction (or sequential write data) in the plurality of write instructions are C313, C311, C314, C312.

[0088] Further, according to the second information, the processor 211 can identify the starting logical address and the data size of the first write data D311 corresponding to the first write instruction C311, and calculate the ending logical address of the first write data D311.

[0089] Then, the processor 211 can identify the starting logical address and the data size of the first write data D312 corresponding to the first write instruction C312, determine that the first write data D312 will be connected after the first write data D311 according to the starting logical address of the first write data D312, and calculate the ending logical address of the first write data D312. In this way, the processor 211 can identify that the first write data D311-D314 are continuous data connected in sequence and belong to the same sequential write data D31, and the thread numbers of the write instructions C311-C314 of the first write data D311-D314 are arranged in sequence (in ascending order). For example, as shown in FIG. 6. Figure 3 ​The arrangement order of the thread numbers corresponds to the processing threads 111-114 that process the first write data D311-D314.

[0090] In addition, the processor 211 can also identify a second arrangement order of the first write data D311-D314 within the sequential write data D31. The second arrangement order is equal to the arrangement order of the thread numbers of the write instructions C311-C314 corresponding to the first write data D311-D314. In another embodiment, the processor 211 further determines whether the total data size of the first write data D311-D314 is equal to a predetermined stored data size (e.g., 4096 bytes).

[0091] Figure 5 An exemplary diagram of performing data write operations according to a first instruction sequence is shown in accordance with an embodiment of the present application. For example, referring to Figure 5 Suppose that the current first instruction sequence OQ(5) has five first write instructions C313, C311, C314, C411, C312 arranged in sequence. In a conventional data write method, as shown by instruction fetch R51, the processor 211 directly fetches the write instructions in the first instruction sequence OQ(5) in sequence without first determining whether there are multiple write instructions corresponding to the same sequential write data and fetching the multiple write instructions corresponding to the same sequential write data first. For example, in the conventional approach, the processor 211 first fetches the first write instruction C313 according to the arrangement order of the first write instruction C313 in the first instruction sequence. Similarly, as shown by instruction fetches R52-R55, the subsequent first write instructions C311, C314, C411, C312 are fetched in sequence.

[0092] In addition, in the conventional write method, the processor 211 performs the corresponding write operations in sequence according to the order in which the first write instructions are fetched. For example, as shown by write operation W51, the first write instruction C313 that is fetched first is executed first to write the corresponding first write data D313 to the rewritable non-volatile memory module 220 at time Tl; then, as shown by write operation W52, the first write instruction C311 that is fetched is executed to write the corresponding first write data D311 to the rewritable non-volatile memory module 220 at time T2. Similarly, as shown by write operation W55, the first write instruction C312 that is fetched is executed last to write the corresponding first write data D312 to the rewritable non-volatile memory module 220 at time T5.

[0093] Please refer back to Figure 2In step S230, the first write instructions are obtained and arranged in ascending order to form a second instruction sequence, wherein the first arrangement order of the first write instructions in the first instruction sequence is different from the second arrangement order of the first write instructions in the second instruction sequence.

[0094] It can be noted that, by the conventional data writing method, the first write data D311-D314 corresponding to the sequential write data D31 are not sequentially written, which is different from the sequential write operation expected by the host system 10. That is, by the conventional data writing method, although multiple processing threads can be utilized to speed up the data writing process, the sequential write operation cannot be guaranteed to occur.

[0095] Therefore, in one or more embodiments of the present application, the write instructions corresponding to the same sequential write data are identified and obtained first, and a reordering operation is performed on the write instructions corresponding to the sequential write data to obtain reordered write instructions, so that the sequential write data can be sequentially written by executing the reordered write instructions. In this way, the sequential write data can be properly written to the rewritable non-volatile memory module 220 through the sequential write operation as expected by the host system 10.

[0096] In this embodiment, the processor 211 obtains the write instructions from the instruction sequence based on the principle of giving priority to the write instructions stored earlier in the instruction sequence.

[0097] Then, please return to Figure 2 In step S240, each of the first write instructions is executed in sequence according to the second instruction sequence to write the sequential write data to the rewritable non-volatile memory module 220.

[0098] Figure 6 A schematic diagram of performing a sequential write operation according to the reordered write instructions corresponding to the sequential write instructions according to an embodiment of the present application is shown. For example, please refer to Figure 6 Suppose that the first instruction sequence OQ(5) stores five write instructions C313, C311, C314, C411, C312, and the write data of the first write instructions C313, C311, C314, C312 each comes from the same sequential write data D31 (as described above with respect to Figure 3In this example, as indicated by instruction fetches R61-R64, the processor 211 sequentially fetches the first write instructions C313, C311, C314, C312 in the order of their arrangement in the first instruction sequence OQ(5) (also referred to as a first arrangement order) after recognizing that the first write instructions C313, C311, C314, C312 correspond to the same sequentially written data. For example, the first write instructions C313, C311, C314, C312 are fetched in the order of #1, #2, #3, #4, respectively.

[0099] Next, as indicated by arrow A6, the processor 211 determines the order (also referred to as a second arrangement order) of the first write data D313, D311, D314, D312 corresponding to the first write instructions C313, C311, C314, C312 in the sequentially written data D31 according to the second information, and reorders the first write instructions C313, C311, C314, C312 in the order, i.e., the first write instructions C313, C311, C314, C312 are rearranged to the first write instructions C311, C312, C313, C314 based on the second arrangement order.

[0100] After obtaining the reordered first write instructions C311, C312, C313, C314, the processor 211 sequentially executes the first write instructions C311, C312, C313, C314 to write the corresponding first write data D311, D312, D313, D314 to the rewritable non-volatile memory module 220 via sequential write operations, as indicated by write operations W61-W64.

[0101] In an embodiment, the plurality of first write instructions are arranged in ascending order to form a second instruction sequence, including: fetching a first instruction and a second instruction from the plurality of first write instructions, wherein the first instruction corresponds to a first logical address and the second instruction corresponds to a second logical address; arranging the first instruction and the second instruction in the ascending order according to the first logical address and the second logical address to obtain a second sub-instruction sequence; sequentially fetching a remaining write instruction, and updating the second sub-instruction sequence according to a logical address corresponding to the remaining write instruction until each of the plurality of first write instructions is fetched, to obtain the second instruction sequence, wherein the remaining write instruction is one or more of the plurality of first write instructions that are not arranged in the ascending order.

[0102] Specifically, two write instructions (for example, a first instruction and a second instruction) are randomly obtained from the current plurality of first write instructions; further, according to first logical addresses and second logical addresses corresponding to the first instruction and the second instruction respectively, ascending arrangement is performed to obtain a first sub-instruction sequence.

[0103] For example, if the first logical address of the first instruction is less than the second logical address of the second instruction, the first sub-instruction sequence sorting result is: the first instruction, the second instruction, otherwise, the first sub-instruction sequence sorting result is: the second instruction, the first instruction.

[0104] Further, the remaining write instructions are continuously obtained, and the second sub-instruction sequence is updated according to the logical addresses corresponding to the remaining write instructions (that is, the remaining write instructions are inserted into the second sub-instruction sequence to obtain a second instruction sequence). Wherein, the second arrangement order of the second instruction sequence is arranged in ascending order according to the logical address corresponding to each first write instruction.

[0105] In this way, through the embodiments provided in the examples of the present application, the logical addresses of each first write instruction are sorted in ascending order, the plurality of first write instructions are sorted and processed to obtain a second instruction sequence. Thus, the first write instruction to be processed is sorted in a logical address continuous manner, then the second instruction sequence is executed in sequence, and finally the continuous storage of the data to be written is ensured, the utilization rate of the storage space is improved, and the write performance of the memory controller is improved.

[0106] In a possible example, the remaining write instructions include a third instruction, the third instruction corresponds to a third logical address, when the second logical address is greater than the first logical address, the sequentially obtaining the remaining write instructions and updating the second sub-instruction sequence according to the logical addresses corresponding to the remaining write instructions includes: if the third logical address is greater than the second logical address, the third instruction is inserted into the tail of the second sub-instruction sequence to obtain a third sub-instruction sequence; or, if the third logical address is less than the first logical address, the third instruction is inserted into the head of the second sub-instruction sequence to obtain the third instruction sequence; or, if the third logical address is greater than the first logical address and less than the second logical address, the third instruction is inserted between the first instruction and the second instruction to obtain the third instruction sequence.

[0107] For example, the third instruction is continuously obtained from the plurality of remaining first write instructions. According to the comparison result of the third logical address corresponding to the third instruction with the first logical address and the second logical address respectively, the third instruction is inserted into the first sub-instruction sequence to obtain the second sub-instruction sequence.

[0108] Specifically, the second sub-instruction sequence is taken as the first instruction, and the second instruction is taken as an example. If the third logical address corresponding to the third instruction is less than the first logical address, the third instruction is inserted into the head position of the second sub-instruction sequence, and an updated second sub-instruction sequence is obtained as: the third instruction, the first instruction, and the second instruction. If the third logical address is greater than the first logical address and less than the second logical address, the updated second sub-instruction sequence is: the first instruction, the third instruction, and the second instruction. If the third logical address is greater than the second logical address, the updated second sub-instruction sequence is: the first instruction, the second instruction, and the third instruction. The above process is repeated until each of the plurality of first write instructions is inserted into the second sub-instruction sequence, and a final second instruction sequence is obtained.

[0109] Specifically, Figure 7 A schematic diagram of the reordering operation according to an embodiment of the present application is shown. For example, refer to Figure 7 It is assumed that the four first write instructions C313, C311, C314, and C312 corresponding to the same sequential write data D31 have been identified, which are arranged according to a first arrangement order.

[0110] As shown in instruction obtaining R71, the processor 211 first obtains a first first write instruction C313, and sets the order of the first write instruction C313 as #1. Next, as shown in instruction obtaining R72, the processor 211 obtains a second first write instruction C311, determines that the first write instruction C311 should be arranged in front of the first write instruction C313 according to the logical addresses of the first write instructions C313 and C311, and sets the order of the first write instruction C311 as #1 and the order of the first write instruction C313 as #2. Next, as shown in instruction obtaining R73, the processor 211 obtains a third first write instruction C314, determines that the first write instruction C314 should be arranged behind the first write instruction C313 according to the logical addresses of the first write instructions C314 and C313, and sets the order of the first write instruction C314 as #3. Next, as shown in instruction obtaining R74, the processor 211 obtains a fourth first write instruction C312, determines that the first write instruction C312 should be arranged behind the first write instruction C311 and in front of the first write instruction C313 according to the logical addresses of the first write instructions C312, C313 and C311, and sets the order of the first write instruction C312 as #2, the order of the first write instruction C313 as #3, and the order of the first write instruction C314 as #4. As shown by arrow A7, when there is no first write instruction that has not been reordered among all the first write instructions that have been obtained, the processor 211 determines that the reordering operation corresponding to the first write instructions C313, C311, C314 and C312 has been completed, and obtains the second write instructions C311, C312, C313 and C314 in the second arrangement order.

[0111] In an embodiment, the processor 211 further stores the plurality of second write instructions into a second instruction sequence in the buffer memory, and executes the second instruction sequence to write the sequential write data corresponding to the sequential write instructions into the rewritable non-volatile memory module 220.

[0112] It is to be noted that the plurality of second write instructions herein represent the plurality of first write instructions after being arranged in ascending order, i.e. the second write instructions are essentially the determined first write instructions.

[0113] In another embodiment, the processor 211 further combines the first write data of the plurality of second write instructions into sequential write data, and generates a corresponding sequential write instruction to cause the combined sequential write data to be written into the rewritable non-volatile memory module 220 via a sequential write operation by executing the generated sequential write instruction.

[0114] Figure 8This is a schematic diagram illustrating a sequential write operation performed by treating the write data corresponding to a plurality of reordered write instructions as sequential write data, according to another embodiment of the present invention. For example, please refer to... Figure 8 , continuing Figure 6 For example, after receiving the reordered first write instructions C311 to C314 (also called the second write instructions C311 to C314), as shown by arrow A81, the processor 211 combines the first write data D311 to D314 corresponding to the first write instructions C311 to C314 into a complete sequential write data D81. Then, as shown in write operation W81, the processor 211 performs a sequential write operation to write the sequential write data D81 to the rewritable non-volatile memory module 220.

[0115] Through sequential write operations, processor 211 can more efficiently manage / allocate multiple consecutive physical addresses provided to the first write data D311–D314 and their corresponding logical addresses. For example, mapping information can be recorded using only one set of logical address-to-physical address fields.

[0116] Furthermore, because the physical addresses are contiguous, the processor 211 can perform read operations on the first written data D311–D314 more efficiently. For example, sequential reads are faster and more efficient than random reads.

[0117] In one embodiment, the processor 211 removes a plurality of first write instructions from a first instruction pair and executes a second instruction sequence to write the sequential write data corresponding to the sequential write instructions into the rewritable nonvolatile memory module 220.

[0118] Figure 9 This is a schematic diagram illustrating the execution of a sequential write operation based on a first instruction sequence having a plurality of reordered write instructions, according to an embodiment of the present invention. For example, please refer to... Figure 9 , continuing Figure 6 For example, after obtaining the reordered first write instructions C311 to C314 (also referred to as the second write instructions C311 to C314), as shown by arrow A9, the processor 211 stores the second write instructions C311 to C314 into the first instruction sequence OQ (5) to obtain the first instruction sequence OQ (6) (e.g., the second write instructions C311 to C314 are stored after the remaining write instruction C411 in the first instruction sequence). In this embodiment, the first write instructions C313, C311, C314, and C312, which were originally in the first instruction sequence OQ (5), have been removed during the previous instruction fetching.

[0119] Next, as shown in the write operation W91-W9, the processor 211 sequentially executes the write instructions C411, C311, C312, C313, C314 in the first instruction sequence OQ(6) to write the corresponding write data to the rewritable non-volatile memory module 220.

[0120] It is reminded that in another embodiment, the second write instructions C311-C314 are inserted before the remaining write instruction C411 due to the need for priority processing.

[0121] Through the above embodiments, it is equivalent to that the first instruction sequence OQ(6) is arranged, which can avoid that the write data that should be sequentially written is written to the rewritable non-volatile memory module in a discrete / non-sequential / random manner, so as to reduce the discreteness of the written data through the execution of the arranged first instruction sequence, effectively enhancing the data management efficiency of the storage device 20. In addition, the storage space consumed by the first instruction sequence can also be simplified, and the space utilization of the buffer memory is improved.

[0122] In an embodiment, the processor 211 determines whether the obtained first write instruction allows the overwrite operation when obtaining each first write instruction. If the obtained first write instruction allows the overwrite operation, it is determined that the obtained first write instruction does not need to perform the reordering operation; and if the obtained first write instruction does not allow the overwrite operation, it is determined that the obtained first write instruction needs to perform the reordering operation. For example, the write instruction can include an overwrite flag. When the overwrite flag is set to a first value (such as 1), it indicates that there is an overwrite between different threads (allowing the overwrite operation). That is, before performing the reordering operation, it is detected whether the overwrite operation is allowed. If yes, the risk of data disorder is avoided, and the processor 211 does not perform the reordering operation.

[0123] In the example of Figure 9 Through the above embodiments, it is equivalent to that the first instruction sequence OQ(6) is arranged, which can avoid that the write data that should be sequentially written is written to the rewritable non-volatile memory module in a discrete / non-sequential / random manner, so as to reduce the discreteness of the written data through the execution of the arranged first instruction sequence, effectively enhancing the data management efficiency of the storage device 20.

[0124] In one embodiment, the processor 211 determines whether the fetched first write instruction allows an overwrite operation when fetching each first write instruction. If the fetched first write instruction allows an overwrite operation, the fetched first write instruction is determined to not require a reordering operation; and if the fetched first write instruction does not allow an overwrite operation, the fetched first write instruction is determined to require a reordering operation. For example, an overwrite flag can be included in the write instruction. When the overwrite flag is set to a first value (e.g., 1), it indicates that there is an overwrite between different threads (allowing an overwrite operation). That is, before performing a reordering operation, it is detected whether an overwrite operation is allowed. If so, the risk of data corruption is avoided, and the processor 211 does not perform a reordering operation.

[0125] In one embodiment, before performing the plurality of first write instructions according to the second arrangement order to write the sequential write data of the corresponding sequential write instruction to the rewritable non-volatile memory module 220, the processor 211 sets a queue status register (QSR) according to the second arrangement order to notify the host system 10 that a sequential write operation is to be performed according to the second arrangement order.

[0126] The queue status register (QSR) carries the status of tasks at a specific point in the instruction sequence. The host system 10 can read this register through the response of the EMMC (Embedded MultiMediaCard) to the SEND_QUEUE_STATUS command (CMD13, bit

[15] = "1"). The parameter of R1 will be the value of the 32-bit queue status register (QSR). Each bit in the QSR represents the ID of the task corresponding to the bit index. If bit QSR[i] = "0", the queued task with task ID i is not ready for execution. The host system 10 is responsible for tracking the status of the task to determine whether the task has been queued and suspended, or whether the task ID is not used. If bit QSR[i] = "1", it is determined that the queued task with task ID i is ready for execution.

[0127] In short, via the data write method provided by the present embodiment, the storage device 20 still actually performs data write according to the write instruction issued by the host system 10, so after the processor 211 helps reorder, the operation of setting the queue status register is still needed to inform the host system 10 of the sequential write operation to be performed. Then, the storage device 20 can truly implement sequential write according to the reordered data write order.

[0128] It should be noted that in the above-mentioned embodiments, the processor 110 has 4 processing threads, but the present application is not limited thereto. For example, in other embodiments, the processor 110 can have more (e.g., 8) or fewer processing threads, and the number of split write data and write instructions will also correspond to the number of processing threads.

[0129] Based on the above, the storage device, the memory controller and the data writing method provided by the embodiments of the present application can actively reorder the plurality of write instructions corresponding to the sequential write instructions respectively issued by the plurality of threads of the host system in a non-sequential manner, to perform a sequential write operation according to the arrangement order of the reordered plurality of write instructions. In this way, the problem that the conventional storage device, the memory controller and the data writing method cannot perform the sequential write operation expected by the host system can be solved, and the plurality of write data corresponding to the sequential write instructions can be sequentially written into the rewritable non-volatile memory module, so as to effectively perform the sequential write operation required by the host system, thereby reducing the random write operation caused by the plurality of threads and improving the overall data access capability of the storage device.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that, An application for controlling a storage device configured with a rewritable non-volatile memory module, the storage device including a memory interface control circuit for coupling to the rewritable non-volatile memory module; Buffer memory; The method includes a processor coupled to the memory interface control circuitry and the buffer memory, wherein the processor is further coupled to the connection interface circuitry of the storage device for coupling to a host system. Acquire and store a first instruction sequence into the buffer memory, wherein the first instruction sequence includes multiple write instructions, each write instruction includes first information and second information, the first information includes a sequence marker, the sequence marker is used to indicate the thread number that sent the corresponding write instruction, and the second information includes a logical address and a data size; Based on the first information and the second information, a plurality of first write instructions that meet preset conditions are determined from the plurality of write instructions, wherein the plurality of first write instructions correspond to a plurality of first write data, and the plurality of first write data are obtained by segmenting sequentially written data, wherein the preset conditions include: the logical addresses between the plurality of first write instructions are continuous, and the plurality of first thread numbers of the plurality of first write instructions sorted based on the logical addresses are continuous and arranged in ascending order; Obtain the plurality of first write instructions and arrange the plurality of first write instructions in ascending order to form a second instruction sequence, wherein the first arrangement order of the plurality of first write instructions in the first instruction sequence is different from the second arrangement order in the second instruction sequence; and The plurality of first write instructions are executed sequentially according to the second instruction sequence to write the sequential write data into the rewritable non-volatile memory module.

2. The data writing method according to claim 1, characterized in that, The step of arranging the plurality of first write instructions in ascending order to form the second instruction sequence includes: Obtain a first instruction and a second instruction from the plurality of first write instructions, wherein the first instruction corresponds to a first logical address and the second instruction corresponds to a second logical address; Based on the first logical address and the second logical address, the first instruction and the second instruction are arranged in ascending order to obtain a second sub-instruction sequence; and The remaining write instructions are sequentially obtained, and the second sub-instruction sequence is updated according to the logical address corresponding to the remaining write instructions, until each of the plurality of first write instructions is obtained, thus obtaining the second instruction sequence. The remaining write instructions are the first write instructions in the plurality of first write instructions that have not been executed in ascending order, and the remaining write instructions include one or more.

3. The data writing method according to claim 2, characterized in that, The remaining write instructions include a third instruction, which corresponds to a third logical address. When the second logical address is greater than the first logical address, the steps of sequentially acquiring the remaining write instructions and updating the second sub-instruction sequence according to the logical address corresponding to the remaining write instructions include: If the third logical address is greater than the second logical address, then the third instruction is inserted into the tail of the second sub-instruction sequence to obtain the third sub-instruction sequence; If the third logical address is less than the first logical address, then the third instruction is inserted at the head of the second sub-instruction sequence queue to obtain the third instruction sequence; and If the third logical address is greater than the first logical address and less than the second logical address, then the third instruction is inserted between the first instruction and the second instruction to obtain the third instruction sequence.

4. The data writing method according to claim 1, characterized in that, The step of acquiring and storing the first instruction sequence to the buffer memory includes: The plurality of write instructions are obtained from the host system, wherein the write instructions are sent respectively via a plurality of processing threads of the host system; Based on the reception time of the plurality of write instructions, a first instruction sequence is formed; and The first instruction sequence is stored in the buffer memory.

5. The data writing method according to claim 1, characterized in that, The method further includes: Remove the acquired plurality of first write instructions from the first instruction sequence and execute the second instruction sequence to write the sequential write data corresponding to the sequential write instructions into the rewritable nonvolatile memory module.

6. The data writing method according to claim 1, characterized in that, The step of determining the plurality of first write instructions that satisfy the preset conditions from the plurality of write instructions based on the first information and the second information includes: Based on the first information, identify the thread number of each write instruction; Based on the second information, identify the logical address and data size of each write instruction; and Based on the thread number, the logical address, and the data size, a plurality of first write instructions that satisfy the preset conditions are determined. The preset condition further includes: the sum of the sizes of the first write data corresponding to the plurality of first write instructions is the same as the predetermined storage data size.

7. The data writing method according to claim 1, characterized in that, The thread numbers corresponding to the plurality of first write instructions in the second instruction sequence are consecutive and arranged in ascending order. The sum of the data sizes corresponding to the plurality of first write instructions in the second instruction sequence is the predetermined data size to be stored, and The first logical addresses corresponding to the plurality of first write instructions in the second instruction sequence are consecutive.

8. The data writing method according to claim 1, characterized in that, The steps prior to executing the plurality of first write instructions sequentially according to the second instruction sequence to write the sequentially written data into the rewritable non-volatile memory module include: The sequence status register is set according to the second arrangement order to instruct the host system to perform sequential write operations in the second arrangement order.

9. The data writing method according to claim 1, characterized in that, The steps prior to obtaining the plurality of first write instructions include: Determine whether the plurality of first write instructions allow overwrite operations, wherein If overwriting the write operation is permitted, then the plurality of first write instructions are not acquired; If overwriting the write operation is not allowed, then the plurality of first write instructions are obtained, and the plurality of first write instructions are sorted in ascending order to obtain the second instruction sequence.

10. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is used to couple to the rewritable non-volatile memory module; Buffer memory; and The processor is coupled to the memory interface control circuit and the buffer memory, wherein the processor is further coupled to the connection interface circuit of the storage device for coupling to the host system. The processor is configured to: Acquire and store a first instruction sequence into the buffer memory, wherein the first instruction sequence includes multiple write instructions, each write instruction includes first information and second information, the first information includes a sequence marker, the sequence marker is used to indicate the thread number that sent the corresponding write instruction, and the second information includes a logical address and a data size; Based on the first information and the second information, a plurality of first write instructions that meet preset conditions are determined from the plurality of write instructions, wherein the plurality of first write instructions correspond to first write data respectively, and the plurality of first write data are obtained by segmenting sequential write data, wherein the preset conditions include: the logical addresses between the plurality of first write instructions are continuous, and the plurality of first thread numbers of the plurality of first write instructions sorted based on the logical addresses are continuous and arranged in ascending order. Obtain the plurality of first write instructions and arrange the plurality of first write instructions in ascending order to form a second instruction sequence, wherein the first arrangement order of the plurality of first write instructions in the first instruction sequence is different from the second arrangement order in the second instruction sequence; and The plurality of first write instructions are executed sequentially according to the second instruction sequence to write the sequential write data into the rewritable non-volatile memory module.

11. The memory controller according to claim 10, characterized in that, The step of arranging the plurality of first write instructions in ascending order to form a second instruction sequence includes: Obtain a first instruction and a second instruction from the plurality of first write instructions, wherein the first instruction corresponds to a first logical address and the second instruction corresponds to a second logical address; Based on the first logical address and the second logical address, the first instruction and the second instruction are arranged in ascending order to obtain a second sub-instruction sequence; and The remaining write instructions are sequentially obtained, and the second sub-instruction sequence is updated according to the logical address corresponding to the remaining write instructions, until each of the plurality of first write instructions is obtained, thus obtaining the second instruction sequence. The remaining write instructions are the first write instructions in the plurality of first write instructions that have not been executed in ascending order, and the remaining write instructions include one or more.

12. The memory controller according to claim 11, characterized in that, The remaining write instructions include a third instruction, which corresponds to a third logical address. When the second logical address is greater than the first logical address, the steps of sequentially acquiring the remaining write instructions and updating the second sub-instruction sequence according to the logical address corresponding to the remaining write instructions include: If the third logical address is greater than the second logical address, then the third instruction is inserted into the tail of the second sub-instruction sequence to obtain the third sub-instruction sequence; If the third logical address is less than the first logical address, then the third instruction is inserted at the head of the second sub-instruction sequence queue to obtain the third instruction sequence; and If the third logical address is greater than the first logical address and less than the second logical address, then the third instruction is inserted between the first instruction and the second instruction to obtain the third instruction sequence.

13. The memory controller according to claim 10, characterized in that, The step of acquiring and storing the first instruction sequence to the buffer memory includes: The processor obtains the plurality of write instructions from the host system, wherein the write instructions are sent respectively via a plurality of processing threads of the host system; Based on the reception time of the plurality of write instructions, a first instruction sequence is formed; and The first instruction sequence is stored in the buffer memory.

14. The memory controller according to claim 10, characterized in that, in The processor removes the acquired plurality of first write instructions from the first instruction sequence and executes the second instruction sequence to write the sequential write data corresponding to the sequential write instructions into the rewritable non-volatile memory module.

15. The memory controller according to claim 10, characterized in that, The step of determining the plurality of first write instructions that satisfy the preset conditions from the plurality of write instructions based on the first information and the second information includes: Based on the first information, identify the thread number of each write instruction; Based on the second information, identify the logical address and data size of each write instruction; and Based on the thread number, the logical address, and the data size, a plurality of first write instructions that satisfy the preset conditions are determined. The preset condition further includes: the sum of the sizes of the first write data corresponding to the plurality of first write instructions is the same as the predetermined storage data size.

16. The memory controller according to claim 10, characterized in that, The thread numbers corresponding to the plurality of first write instructions in the second instruction sequence are consecutive and arranged in ascending order. The sum of the data sizes corresponding to the plurality of first write instructions in the second instruction sequence is the predetermined data size to be stored, and The first logical addresses corresponding to the plurality of first write instructions in the second instruction sequence are consecutive.

17. The memory controller according to claim 10, characterized in that, The steps prior to executing the plurality of first write instructions sequentially according to the second instruction sequence to write the sequentially written data into the rewritable non-volatile memory module include: The processor sets the sequence status register according to the second arrangement order to instruct the host system to perform sequential write operations in the second arrangement order.

18. The memory controller according to claim 10, characterized in that, The steps prior to obtaining the plurality of first write instructions include: The processor determines whether the plurality of first write instructions allow overwrite operations, wherein If overwriting the write operation is permitted, the processor does not acquire the plurality of first write instructions; If overwriting the write operation is not allowed, the processor obtains the plurality of first write instructions and performs the ascending sorting on the plurality of first write instructions to obtain the second instruction sequence.

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