Semiconductor devices

Abstract

The present invention discloses a semiconductor device, which includes: a semiconductor substrate, which has a first main surface and a second main surface, and the first main surface and the second main surface are arranged at intervals in the vertical direction; a drift layer, which is arranged between the first main surface and the second main surface; a base layer, which is arranged on the side of the drift layer facing the first main surface; a groove, which penetrates the base layer from the first main surface and reaches the drift layer; a collector layer, which is located on the side of the drift layer facing the second main surface; a buffer layer, which is located between the drift layer and the collector layer, and a avoidance area is arranged in the buffer layer; a first floating layer, which is arranged in the avoidance area, and the two sides in the vertical direction are respectively in contact with the drift layer and the first collector layer. Therefore, by arranging the first floating layer in the buffer layer, the semiconductor device can be accelerated to enter bipolar conduction, so that the voltage foldback phenomenon can be effectively suppressed or even eliminated when the semiconductor device is forwardly conducted.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In the prior art, in the initial forward conduction stage of a reverse-conducting insulated gate bipolar transistor, there is a positive feedback process in which the current increases continuously and the resistance decreases continuously during the conversion process of the device from a unipolar conduction state to a bipolar conduction state, which is called the voltage foldback phenomenon. The voltage foldback phenomenon slows down the turn-on speed of the reverse-conducting insulated gate bipolar transistor device, and in severe cases, it may cause the reverse-conducting insulated gate bipolar transistor device to be unable to turn on, causing damage to the reliability and performance of the device.

[0003] In the related art, in order to eliminate the voltage foldback phenomenon in the reverse conducting insulated gate bipolar transistor, a common method is to increase the width of the P-type collector region. However, an excessively large P-type collector region will cause uneven current distribution inside the device, thereby reducing the voltage resistance of the device. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can effectively suppress the voltage foldback phenomenon.

[0005] According to an embodiment of the present invention, a semiconductor device comprises: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a vertical direction; a drift layer of a first conductivity type, the drift layer being arranged on the semiconductor substrate and located between the first main surface and the second main surface; a base layer of a second conductivity type, the base layer being arranged on a side of the drift layer facing the first main surface, and a surface of the base layer on a side away from the drift layer constituting a part of the first main surface; an emitter metal layer, the emitter metal layer being arranged on the first main surface; a groove, the depth direction of the groove penetrating the base layer from the first main surface and reaching the drift layer, the groove being multiple, and the multiple grooves being spaced apart in a horizontal direction; a collector layer, the collector layer comprising a first collector layer of a second conductivity type and a second collector layer of a first conductivity type, the semiconductor substrate comprising an insulated gate bipolar transistor region and a fast recovery diode region, the insulated gate bipolar transistor region being circumferentially arranged on the outside of the fast recovery diode region, the first collector A polar layer is arranged on a side of the drift layer facing the second main surface, a side of the first collector layer away from the drift layer constitutes at least a part of the second main surface, and the first collector layer is located in the insulated gate bipolar transistor region; the second collector layer is arranged on a side of the drift layer facing the second main surface, a side of the second collector layer away from the drift layer constitutes at least a part of the second main surface, and the second collector layer is located in the fast recovery diode region; a collector metal layer, the collector metal layer is arranged on the second main surface; a buffer layer of a first conductivity type, the buffer layer is arranged on a side of the drift layer facing the second main surface and located in the insulated gate bipolar transistor region, the buffer layer is located between the drift layer and the first collector layer, two sides of the buffer layer in a vertical direction are in contact with the drift layer and the first collector layer respectively, and an avoidance region is arranged in the buffer layer; a first floating layer of a second conductivity type, the first floating layer is arranged in the avoidance region, and two sides of the first floating layer in a vertical direction are in contact with the drift layer and the first collector layer respectively.

[0006] Therefore, by providing the first floating layer in the buffer layer, the semiconductor device can be accelerated to enter bipolar conduction, so that the voltage foldback phenomenon can be effectively suppressed or even eliminated when the semiconductor device is forward-conducted.

[0007] In some examples of the present invention, the buffer layer includes a first sub-buffer layer and a second sub-buffer layer, the first sub-buffer layer and the second sub-buffer layer are arranged at intervals in the horizontal direction to form the avoidance area, and the first floating layer is arranged between the first sub-buffer layer and the second sub-buffer layer, wherein the horizontal direction and the vertical direction are perpendicular to each other.

[0008] In some examples of the present invention, the first sub-buffer layer and the second sub-buffer layer have equal sizes in horizontal directions, and the first floating layer corresponds to the plurality of trenches in the insulated gate bipolar transistor region.

[0009] In some examples of the present invention, the side of the first floating layer facing the first main surface is flush with the side of the buffer layer facing the first main surface, and the side of the first floating layer facing the second main surface is flush with the side of the buffer layer facing the second main surface.

[0010] In some examples of the present invention, the semiconductor device also includes a second floating layer of a second conductivity type, the second floating layer is arranged in the drift layer and is located in the fast recovery diode region, the depth direction of the second floating layer extends from a side of the drift layer adjacent to the second main surface toward the first main surface, and the second floating layer is in contact with the second collector layer.

[0011] In some examples of the present invention, there are a plurality of the second floating layers, and the plurality of the second floating layers are spaced apart by the drift layer.

[0012] In some examples of the present invention, a doping concentration of ions of the second conductivity type in the first floating layer is less than a doping concentration of ions of the second conductivity type in the first collector layer.

[0013] In some examples of the present invention, the semiconductor device also includes a first dielectric isolation layer, which is arranged between the insulated gate bipolar transistor region and the fast recovery diode region, and the depth direction of the first dielectric isolation layer extends from the second main surface toward the first main surface, and the first dielectric isolation layer penetrates the collector layer and reaches the drift layer.

[0014] In some examples of the present invention, one end of the first dielectric isolation layer adjacent to the first main surface protrudes beyond one end of the second floating layer adjacent to the first main surface.

[0015] In some examples of the present invention, the semiconductor device also includes a second dielectric isolation layer, the collector metal layer includes a first collector metal layer and a second collector metal layer, the first collector metal layer is located in the insulated gate bipolar transistor region, the second collector metal layer is arranged in the fast recovery diode region, the first collector metal layer and the second collector metal layer are spaced apart, and the second dielectric isolation layer is arranged between the first collector metal layer and the second collector metal layer and corresponds to the first dielectric isolation layer.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0020] Figure 3 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0022] Figure 5 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 6 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0024] Figure 7 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figure 8 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Fig. 9 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Fig.10 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Fig.11 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Fig.12 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Fig.13 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Reference numerals:

[0032] 100. Semiconductor devices;

[0033] 1. semiconductor substrate; 101. first main surface; 102. second main surface; 103. insulated gate bipolar transistor region; 104. fast recovery diode region;

[0034] 2. Drift layer; 3. Base layer; 4. Emitter metal layer;

[0035] 5. trench; 501. gate; 502. gate oxide layer;

[0036] 6. Collector layer; 601. First collector layer; 602. Second collector layer;

[0037] 7. Collector metal layer; 701. First collector metal layer; 702. Second collector metal layer;

[0038] 8. Buffer layer; 801. First sub-buffer layer; 802. Second sub-buffer layer; 803. Avoidance area;

[0039] 9. First floating layer; 10. Second floating layer; 11. First dielectric isolation layer; 12. Second dielectric isolation layer;

[0040] 13. Gate pad; 14. Emitter region; 15. Contact hole region; 16. Carrier storage layer. DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0042] Reference below Figure 1-Figure 13 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description. Similarly, the first conductivity type can also be set to P type and the second conductivity type can be set to N type.

[0043] Combination Figure 1As shown, the semiconductor device 100 according to the present invention may mainly include: a semiconductor substrate 1, a drift layer 2 of a first conductive type, a base layer 3 of a second conductive type, an emitter metal layer 4, a groove 5, a collector layer 6, a collector metal layer 7, a buffer layer 8 of a first conductive type and a first floating layer 9 of a second conductive type, wherein the semiconductor substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in the vertical direction, which can provide a stable and reliable setting position for other structures in the semiconductor device 100.

[0044] In the embodiment of the present invention, the drift layer 2 of the first conductivity type is arranged in the semiconductor substrate 1 and is located between the first main surface 101 and the second main surface 102, so that a transmission channel can be provided for the current in the semiconductor device 100. The semiconductor device 100 has an insulated gate bipolar transistor region 103 and a fast recovery diode region 104. The insulated gate bipolar transistor region 103 and the fast recovery diode region 104 are reversely connected in parallel in the semiconductor device 100, so that the insulated gate bipolar transistor has a reverse conduction function. The insulated gate bipolar transistor region 103 is circumferentially arranged on the outside of the fast recovery diode region 104, and is spaced from the fast recovery diode region 104. The transition region is located between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103, which can prevent the currents flowing through the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 from affecting each other, thereby ensuring the normal operation of the reverse conducting insulated gate bipolar transistor.

[0045] Furthermore, the base layer 3 is arranged on the side of the drift layer 2 facing the first main surface 101, the surface of the base layer 3 away from the drift layer 2 constitutes a part of the first main surface 101, the emitter metal layer 4 is arranged on the first main surface 101, and the collector metal layer 7 is arranged on the second main surface 102. The base layer 3 is also provided with an emitter region 14 and a contact hole region 15, wherein the emitter region 14 and the contact hole region 15 both constitute at least a part of the first main surface 101, and the emitter region 14 is electrically connected to the emitter metal layer 4 so that the emitter region 14 and the emitter metal layer 4 have the same potential.

[0046] In the embodiment of the present invention, the depth direction of the groove 5 penetrates the base layer 3 from the first main surface 101 and reaches the drift layer 2, so that the electron flow channel in the insulated gate bipolar transistor region 103 can be normally opened. In addition, there are multiple grooves 5, and the multiple grooves 5 are arranged at intervals in the horizontal direction. It should be noted that the depth direction of the groove 5 in the embodiment of the present invention is Figure 1 The vertical direction in .

[0047] In an embodiment of the present invention, a groove 5 is provided in the insulated gate bipolar transistor region 103. The groove 5 in this region is an active groove, and an active gate is provided inside the groove. The active groove can extend the active gate of the insulated gate bipolar transistor region 103 from the first main surface 101 to the drift layer 2. The active gate is electrically connected to the gate pad 13 of the semiconductor device 100, so that the active gate and the gate pad 13 can have the same potential.

[0048] In the active trench, the active gate is spaced apart from the inner wall of the active trench, an active gate insulating film is arranged between the active gate and the active trench, and the active gate is arranged opposite to the emitter region 14, the base layer 3 and the first drift layer 2 through the active gate insulating film, so as to ensure the normal operation of the insulated gate bipolar transistor region 103.

[0049] In the semiconductor device 100 of the embodiment of the present invention, a groove 5 is provided in both the fast recovery diode region 104 and the transition region. The groove 5 in this region is a virtual groove, a virtual gate is provided inside the virtual groove, the virtual gate and the inner wall of the virtual groove are spaced apart, and a virtual gate insulating film is provided between the virtual gate and the virtual groove.

[0050] In the embodiment of the present invention, the collector layer 6 includes a first collector layer 601 of the second conductivity type and a second collector layer 602 of the first conductivity type, the first collector layer 601 is arranged on the side of the first drift layer 2 facing the second main surface 102, the side of the first collector layer 601 away from the drift layer 2 constitutes at least part of the second main surface 102, and the first collector layer 601 is located in the insulated gate bipolar transistor region 103. The second collector layer 602 is arranged on the side of the second drift layer 2 facing the second main surface 102, the side of the second collector layer 602 away from the drift layer 2 constitutes at least part of the second main surface 102, and the second collector layer 602 is located in the fast recovery diode region 104. In this way, the basic structure of the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 can be formed, and the forward conduction characteristics of the insulated gate bipolar transistor region 103 and the reverse recovery characteristics of the fast recovery diode region 104 can be guaranteed.

[0051] Furthermore, a buffer layer 8 of the first conductive type is arranged on the side of the drift layer 2 facing the second main surface 102 and is located in the insulated gate bipolar transistor region 103. The buffer layer 8 is located between the drift layer 2 and the first collector layer 601. The two sides of the buffer layer 8 in the vertical direction are respectively in contact with the drift layer 2 and the first collector layer 601. In this way, when the semiconductor device 100 is forward-conducted, the buffer layer 8 can block the diffusion of the carrier depletion region.

[0052] According to an embodiment of the present invention, at the initial forward conduction stage of the reverse conducting insulated gate bipolar transistor, after the gate voltage opens the channel on the active gate side of the semiconductor device 100, the carriers flow vertically from the emitter region 14 of the first conductive type through the drift layer 2, reach the first collector layer 601 on the side close to the drift layer 2, and finally flow out from the second collector layer 602 in the fast recovery diode region 104. In this process, only electrons, one type of carrier, participate in conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a unipolar conduction state.

[0053] In the unipolar conduction state, a voltage drop will be generated on the carrier flow path. When this voltage drop is greater than the built-in potential of the PN junction formed by the first collector layer 601 and the drift layer 2, the PN junction formed by the second conductive type first collector layer 601 and the first conductive type drift layer 2 is turned on, and holes are injected into the drift layer 2 by the first collector layer 601, and then flow out from the base layer 3 after passing through the drift layer 2. In this process, two types of carriers, electrons and holes, participate in the conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a bipolar conduction state.

[0054] During the process of the reverse conducting insulated gate bipolar transistor switching from the unipolar conduction state and the bipolar conduction state, due to the injection of a large amount of holes, the reverse conducting insulated gate bipolar transistor will produce a conductivity modulation effect, resulting in a decrease in the on-resistance of the semiconductor device 100. At this time, there is a negative resistance region in the current-voltage output characteristic curve of the semiconductor device 100 where the current increases and the voltage decreases, which is called the voltage foldback phenomenon.

[0055] Furthermore, combined with Fig. 9 As shown, a buffer layer 8 is provided with an escape region 803, a first floating layer 9 of the second conductivity type is provided in the escape region 803, and both sides of the first floating layer 9 in the vertical direction are in contact with the drift layer 2 and the first collector layer 601, respectively. In this way, in the process of forward conduction of the insulated gate bipolar transistor region 103, the PN junction formed by the first floating layer 9 and the drift layer 2 is easier to conduct than the PN junction formed by the first collector layer 601 and the drift layer 2. As a result, the reverse-conducting insulated gate bipolar transistor can be accelerated from the unipolar conduction state to the bipolar conduction state, thereby reducing or even eliminating the voltage foldback phenomenon.

[0056] Combination Figure 1As shown, the buffer layer 8 includes a first sub-buffer layer 801 and a second sub-buffer layer 802, the first sub-buffer layer 801 and the second sub-buffer layer 802 are arranged at intervals in the horizontal direction to form an avoidance area 803, and the first floating layer 9 is arranged between the first sub-buffer layer 801 and the second sub-buffer layer 802, wherein the horizontal direction and the vertical direction are perpendicular to each other. In this way, the first sub-buffer layer 801, the second sub-buffer layer 802 and the first floating layer 9 can be respectively in contact with the drift layer 2 and the first collector layer 601 in the vertical direction, so that not only can the buffer layer 8 cut off the carrier depletion region, but also can ensure that the first floating layer 9 and the drift layer 2 form a PN junction that is easier to conduct.

[0057] According to some embodiments of the present invention, Figure 1 and Fig. 9 As shown, the first sub-buffer layer 801 and the second sub-buffer layer 802 have the same size in the horizontal direction, and the first floating layer 9 corresponds to the multiple trenches 5 in the insulated gate bipolar transistor region 103. Specifically, when the avoidance region 803 is formed between the first sub-buffer layer 801 and the second sub-buffer layer 802, the first sub-buffer layer 801 and the second sub-buffer layer 802 have the same size in the horizontal direction, so that the uniformity of the first sub-buffer layer 801 and the second sub-buffer layer 802 on both sides of the first floating layer 9 can be ensured. In the semiconductor device 100, the buffer layer 8 prevents the expansion of the carrier depletion region, which is not only conducive to improving the switching speed of the semiconductor device 100, but also allows the insulated gate bipolar transistor region 103 to maintain a low on-state voltage drop.

[0058] Furthermore, when the semiconductor device 100 is forward-conducted, an electron flow channel is formed along the depth direction of the groove 5 to carry the main current. In the embodiment of the present invention, the first floating layer 9 corresponds to the plurality of grooves 5 in the insulated gate bipolar transistor region 103, so that the first floating layer 9 corresponds to the formed flow channel, so that the side of the first floating layer 9 close to the drift layer 2 bears the main large current. Such a configuration is conducive to accelerating the opening of the PN junction formed by the first floating layer 9 and the drift layer 2, and can effectively suppress or even eliminate the voltage foldback phenomenon.

[0059] Combination Figure 1As shown, the side of the first floating layer 9 facing the first main surface 101 is flush with the side of the buffer layer 8 facing the first main surface 101, and the side of the first floating layer 9 facing the second main surface 102 is flush with the side of the buffer layer 8 facing the second main surface 102. With such an arrangement, both sides of the first floating layer 9 in the vertical direction can be kept flush with both sides of the buffer layer 8 in the vertical direction, which not only facilitates the manufacture of the first floating layer 9, but also ensures that both sides of the first floating layer 9 in the vertical direction and both sides of the buffer layer 8 in the vertical direction can be in contact with the drift layer 2 and the first collector layer 601 respectively, so as to improve the turn-off speed and reliability of the semiconductor device 100.

[0060] Combination Figure 1 As shown, the semiconductor device 100 further includes a second floating layer 10 of a second conductivity type, the second floating layer 10 is disposed in the drift layer 2, the depth direction of the second floating layer 10 extends from the side of the drift layer 2 adjacent to the second main surface 102 toward the first main surface 101, and the second floating layer 10 is in contact with the second collector layer 602. It should be noted that the depth direction of the second floating layer 10 in the embodiment of the present invention is Figure 1 The vertical direction in .

[0061] Specifically, when the semiconductor device 100 is forward-conducted, the second floating layer 10 can provide an electron barrier to block electrons from flowing from the side of the first collector layer 601 close to the drift layer 2 to the side of the second collector layer 602 close to the drift layer 2. This can concentrate the current on the first collector layer 601, thereby increasing the resistance on the first collector layer 601 and allowing the device to quickly enter bipolar conduction, thereby suppressing the voltage foldback phenomenon.

[0062] Furthermore, when the semiconductor device 100 is reverse recovered, the second floating layer 10 can also control the hole injection efficiency of the second collector layer 602 into the second drift layer 2, thereby improving the softness of the reverse conducting insulated gate bipolar transistor during the reverse recovery process and avoiding voltage overshoot during reverse recovery.

[0063] In an embodiment of the present invention, the doping concentration of the second floating layer 10 of the second conductivity type is low-concentration doping. This is because the doping concentration of the drift layer 2 of the first conductivity type in the fast recovery diode region 104 is also low-concentration doping. If the doping concentration of the second floating layer 10 is too high, it will affect the opening of the fast recovery diode region 104.

[0064] Combination Figure 1As shown, there are multiple second floating layers 10, and the multiple second floating layers 10 are arranged at intervals through the drift layer 2. In this way, the side of the second collector layer 602 facing the first main surface 101 can at least partially contact the drift layer 2, so that there is a current gap in the fast recovery diode region 104, so that the second collector layer 602 can normally extract charges from the second drift layer 2 during the device shutdown process.

[0065] According to the embodiment of the present invention, the doping concentration of the second conductive type ions of the first floating layer 9 is less than the doping concentration of the second conductive type ions of the first collector layer 601. With this arrangement, compared with the PN junction formed by the first collector layer 601 and the drift layer 2, the built-in potential of the PN junction formed by the first floating layer 9 and the drift layer 2 is lower, and under the same voltage drop, the PN junction on one side of the first floating layer 9 is easier to open, which can effectively suppress the voltage foldback phenomenon when the insulated gate bipolar transistor region 103 is forward-conducted.

[0066] Combination Figure 1 As shown, the semiconductor device 100 further includes a first dielectric isolation layer 11, which is disposed between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104. The depth direction of the first dielectric isolation layer 11 extends from the second main surface 102 toward the first main surface 101, and the first dielectric isolation layer 11 penetrates the collector layer 6 and reaches the drift layer 2. It should be noted that the depth direction of the first dielectric isolation layer 11 in the embodiment of the present invention is Figure 1 The vertical direction in .

[0067] Specifically, after the gate voltage opens the channel, the carriers reach the side of the first collector layer 601 close to the drift layer 2 from the emitter region 14. At this time, the first dielectric isolation layer 11 can block the carriers on the side of the first collector layer 601 close to the drift layer 2 in the vertical direction from flowing to the side of the second collector layer 602 close to the drift layer 2. This can increase the resistance of the first collector layer 601 on the side close to the drift layer 2 in the vertical direction, thereby increasing the voltage drop on the carrier flow path on the side of the first collector layer 601 on the side close to the drift layer 2 in the vertical direction, and thus speeding up the bipolar conduction rate of the insulated gate bipolar transistor region 103, so that the insulated gate bipolar transistor region 103 quickly enters the bipolar conduction state from the unipolar conduction state, so as to reduce or even eliminate the voltage foldback phenomenon.

[0068] According to an embodiment of the present invention, the first dielectric isolation layer 11 is a silicon dioxide isolation layer. Specifically, the first dielectric isolation layer 11 is provided with a silicon dioxide isolation layer, which can effectively block the carriers on the side of the collector layer 6 close to the drift layer 2 from the insulated gate bipolar transistor region 103 to the fast recovery diode region 104, so that the resistance of the first collector layer 601 in the insulated gate bipolar transistor region 103 close to the drift layer 2 can be increased to increase the voltage drop on the carrier flow path, thereby enabling the semiconductor device 100 to quickly enter bipolar conduction from unipolar conduction, so as to reduce or even eliminate the voltage foldback phenomenon in the semiconductor device 100.

[0069] Combination Figure 1 As shown, one end of the first dielectric isolation layer 11 adjacent to the first main surface 101 protrudes from one end of the second floating layer 10 adjacent to the first main surface 101. While the second floating layer 10 is in contact with the second collector layer 602, a silicon dioxide isolation layer is provided between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103, so as to prevent the floating layer from contacting the second collector layer 602 and affecting the withstand voltage of the device.

[0070] Combination Figure 1 As shown, the semiconductor device 100 also includes a second dielectric isolation layer 12, the collector metal layer 7 includes a first collector metal layer 701 and a second collector metal layer 702, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103, the second collector metal layer 702 is arranged in the fast recovery diode region 104, and the first collector metal layer 701 and the second collector metal layer 702 are arranged at intervals.

[0071] Specifically, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103 to form the basic structure of the insulated gate bipolar transistor region 103. The second collector metal layer 702 is located in the fast recovery diode region 104 to form the basic structure of the fast recovery diode region 104. The second dielectric isolation layer 12 is disposed between the first collector metal layer 701 and the second collector metal layer 702, and corresponds to the first dielectric isolation layer 11.

[0072] In the embodiment of the present invention, the second dielectric isolation layer 12 is a silicon dioxide isolation layer, and the second dielectric isolation layer 12 and the first dielectric isolation layer 11 are integrally manufactured during the production process of the semiconductor device 100, so that the silicon dioxide isolation layer constitutes at least a portion of the second main surface 102 of the semiconductor device 100. When the semiconductor device 100 is operating, the first collector metal layer 701 and the second collector metal layer 702 have the same potential.

[0073] Combine the following Figure 2-Figure 13 A method for manufacturing the semiconductor device 100 according to an embodiment of the present invention is described.

[0074] According to an embodiment of the present invention, a substrate of a semiconductor device 100 is provided, wherein a drift layer 2 of a first conductivity type is used as the substrate, and the substrate has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are arranged at intervals in a vertical direction. The semiconductor device 100 is manufactured based on the substrate.

[0075] Furthermore, a groove 5 is etched on the substrate by photolithography and etching, a gate oxide layer 502 is first deposited in the groove 5 to cover the inner wall of the groove 5, and then a gate 501 metal is deposited in the groove 5. The gate 501 metal includes but is not limited to polysilicon.

[0076] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 near the first main surface 101 to form a base layer 3. A carrier storage layer 16 is formed on one side of the drift layer 2 near the base layer 3.

[0077] Furthermore, ions of the first conductivity type are implanted on the base layer 3 to form an emitter region 14 . The emitter region 14 is located on at least one side of the trench 5 in a horizontal direction and constitutes at least a portion of the first main surface 101 .

[0078] Furthermore, ions of the first conductivity type are implanted on the base layer 3 to form a contact hole region 15 . The contact hole region 15 constitutes at least a portion of the first main surface 101 and is spaced apart from the trench 5 in the horizontal direction.

[0079] Furthermore, a dielectric layer is deposited on the first main surface 101 of the substrate, and the dielectric layer is etched to form contact holes, a gate pad 13 and an emitter metal layer 4 at positions corresponding to the gate 501, the emitter region 14 and the contact hole region 15 on the dielectric layer, wherein the gate pad 13 is electrically connected to the active gate, and the emitter metal layer 4 is electrically connected to the emitter region 14.

[0080] Furthermore, etching is performed on the side of the substrate facing the second main surface 102 to form a groove between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 , and silicon dioxide is deposited in the groove to form a first dielectric isolation layer 11 .

[0081] Further, ions of the first conductivity type are implanted in the drift layer 2 in the IGBT region 103 near the second main surface 102 to form a first sub-buffer layer 801 and a second sub-buffer layer 802, and an escape region 803 is formed between the first sub-buffer layer 801 and the second sub-buffer layer 802. Then, ions of the second conductivity type are implanted in the escape region 803 to form a first floating layer 9.

[0082] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 in the fast recovery diode region 104 near the second main surface 102 to form a plurality of second floating layers 10 that are spaced apart.

[0083] Further, ions of the second conductivity type are implanted on the side of the buffer layer 8 and the first floating layer 9 facing the second main surface 102 to form a first collector layer 601, wherein the ion doping concentration of the first floating layer 9 is less than the ion doping concentration of the first collector layer 601. Ions of the first conductivity type are implanted on the side of the second floating layer 10 facing the second main surface 102 to form a second collector layer 602.

[0084] Further, a collector metal is deposited on the side of the second main surface 102 of the substrate away from the collector layer 6 to form a first collector metal layer 701 in the insulated gate bipolar transistor region 103 and a second collector metal layer 702 in the fast recovery diode region 104. Further, silicon dioxide is deposited between the first collector metal layer 701 and the second collector metal layer 702 to form a second dielectric isolation layer 12. At this point, the second dielectric isolation layer 12 and the first dielectric isolation layer 11 are an integrated silicon dioxide isolation layer. At this point, the semiconductor device 100 of the embodiment of the present invention is completed.

[0085] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0086] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0087] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate (1) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101), wherein the first main surface (101) and the second main surface (102) are arranged at intervals in a vertical direction; A drift layer (2) of a first conductivity type, the drift layer (2) being arranged on the semiconductor substrate (1) and located between the first main surface (101) and the second main surface (102); A base layer (3) of a second conductivity type, the base layer (3) being arranged on a side of the drift layer (2) facing the first main surface (101), and a surface of the base layer (3) on a side away from the drift layer (2) constituting a part of the first main surface (101); An emitter metal layer (4), the emitter metal layer (4) being arranged on the first main surface (101); A groove (5), wherein the depth direction of the groove (5) penetrates the base layer (3) from the first main surface (101) and reaches the drift layer (2), and there are a plurality of grooves (5), and the plurality of grooves (5) are arranged at intervals in the horizontal direction; a collector layer (6), the collector layer (6) comprising a first collector layer (601) of a second conductivity type and a second collector layer (602) of a first conductivity type; the semiconductor substrate (1) comprising an insulated gate bipolar transistor region (103) and a fast recovery diode region (104); the insulated gate bipolar transistor region (103) is circumferentially arranged outside the fast recovery diode region (104); the first collector layer (601) is arranged on a side of the drift layer (2) facing the second main surface (102); a side of the first collector layer (601) away from the drift layer (2) constitutes at least a portion of the second main surface (102); and the first collector layer (601) is located in the insulated gate bipolar transistor region (103); The second collector layer (602) is arranged on a side of the drift layer (2) facing the second main surface (102), a side of the second collector layer (602) away from the drift layer (2) constitutes at least a part of the second main surface (102), and the second collector layer (602) is located in the fast recovery diode region (104); A collector metal layer (7), the collector metal layer (7) being arranged on the second main surface (102); a buffer layer (8) of a first conductivity type, the buffer layer (8) being arranged on a side of the drift layer (2) facing the second main surface (102) and located in the insulated gate bipolar transistor region (103), the buffer layer (8) being located between the drift layer (2) and the first collector layer (601), the two sides of the buffer layer (8) in a vertical direction being in contact with the drift layer (2) and the first collector layer (601) respectively, and a avoidance region (803) being arranged in the buffer layer (8); a first floating layer (9) of a second conductivity type, the first floating layer (9) being arranged in the avoidance area (803), and two sides of the first floating layer (9) in a vertical direction being in contact with the drift layer (2) and the first collector layer (601) respectively; The buffer layer (8) comprises a first sub-buffer layer (801) and a second sub-buffer layer (802), wherein the first sub-buffer layer (801) and the second sub-buffer layer (802) are arranged at intervals in the horizontal direction to form the avoidance area (803), and the first floating layer (9) is arranged between the first sub-buffer layer (801) and the second sub-buffer layer (802), wherein the horizontal direction and the vertical direction are perpendicular to each other.

2. The semiconductor device according to claim 1, wherein: The first sub-buffer layer (801) and the second sub-buffer layer (802) have the same size in the horizontal direction, and the first floating layer (9) corresponds to the multiple trenches (5) in the insulated gate bipolar transistor region (103).

3. The semiconductor device according to claim 1, wherein: The side of the first floating layer (9) facing the first main surface (101) is flush with the side of the buffer layer (8) facing the first main surface (101), and the side of the first floating layer (9) facing the second main surface (102) is flush with the side of the buffer layer (8) facing the second main surface (102).

4. The semiconductor device according to claim 1, wherein: It also includes a second floating layer (10) of a second conductivity type, the second floating layer (10) being arranged in the drift layer (2) and located in the fast recovery diode region (104), the second floating layer (10) extending in a depth direction from a side of the drift layer (2) adjacent to the second main surface (102) toward the first main surface (101), and the second floating layer (10) being in contact with the second collector layer (602).

5. The semiconductor device according to claim 4, wherein: There are a plurality of the second floating layers (10), and the plurality of the second floating layers (10) are arranged at intervals through the drift layer (2).

6. The semiconductor device according to claim 4, wherein: The doping concentration of the second conductive type ions of the first floating layer (9) is lower than the doping concentration of the second conductive type ions of the first collector layer (601).

7. The semiconductor device according to claim 4, wherein: The invention also comprises a first dielectric isolation layer (11), wherein the first dielectric isolation layer (11) is arranged between the insulated gate bipolar transistor region (103) and the fast recovery diode region (104), wherein the first dielectric isolation layer (11) extends in a depth direction from the second main surface (102) toward the first main surface (101), and wherein the first dielectric isolation layer (11) penetrates the collector layer (6) and reaches the drift layer (2).

8. The semiconductor device according to claim 7, wherein: One end of the first dielectric isolation layer (11) adjacent to the first main surface (101) protrudes beyond one end of the second floating layer (10) adjacent to the first main surface (101).

9. The semiconductor device according to claim 7, wherein: It also includes a second dielectric isolation layer (12), the collector metal layer (7) includes a first collector metal layer (701) and a second collector metal layer (702), the first collector metal layer (701) is located in the insulated gate bipolar transistor region (103), the second collector metal layer (702) is arranged in the fast recovery diode region (104), the first collector metal layer (701) and the second collector metal layer (702) are arranged at intervals, and the second dielectric isolation layer (12) is arranged between the first collector metal layer (701) and the second collector metal layer (702) and corresponds to the first dielectric isolation layer (11).

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