Terminal structure of power semiconductor device, manufacturing method and power semiconductor device

Abstract

A terminal structure, a manufacturing method and a power semiconductor device of a power semiconductor device, belonging to the technical field of semiconductor devices. The P base region in the terminal structure is a JTE structure; the terminal structure is a negative bevel structure. Wherein, the JTE structure includes a plurality of continuous JTE regions, the doping concentration of the JTE region at the surface position is continuous, and the doping concentration at the bottom of the JTE region, the junction between the JTE region and the active region, and the junction between the JTE regions is discontinuous. The terminal structure of the present invention adopts a composite terminal structure of JTE and a grinding table, and utilizes the JTE structure to reduce the charge of the P base region in the terminal region, widen the edge depletion layer, and reduce the surface electric field strength; at the same time, the JTE modulates the electric field in the body, reduces the electric field concentration, further reduces the surface electric field strength, increases the breakdown voltage, and reduces the terminal size.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly, to a junction terminal structure of a power semiconductor device, a manufacturing method and a power semiconductor device. Background Art

[0002] Integrated Gate Commutated Thyristor (IGCT) is a new type of semiconductor switching device, which integrates the gate drive circuit and the gate commutated thyristor (GCT) into a whole. The gate commutated thyristor (GCT) is a new type of power semiconductor device based on the GTO structure. It not only has the same high blocking capability and low on-state voltage drop as GTO, but also has the same switching performance as IGBT, that is, it is the result of GTO and IGBT complementing each other. It is an ideal megawatt-level, medium and high voltage switching device, widely used in voltage source inverters, current source inverters, choppers, static circuit breakers and many other topology circuits.

[0003] The GCT chip is a whole wafer structure, consisting of an active area, a gate contact ring area, and a terminal structure. Figure 1 The gate contact ring is located between the active areas of the chip or outside the active area, responsible for the transmission of gate signals and the derivation of the turn-off current; the active area is located inside the chip, responsible for the flow of the GCT chip; the terminal structure surrounds the outermost part of the chip to reduce the electric field concentration at the edge of the active area, widen the width of the depletion layer, and increase the breakdown voltage of the device. When the chip area is constant, the longer the terminal structure size, the smaller the area occupied by the active area, and the lower the flow capacity, so people have been committed to reducing the terminal size.

[0004] GCT chips usually adopt a table terminal structure similar to that of ordinary thyristors, see Figure 2 The P base region of the entire terminal area and the P base region of the active area are formed by full-surface general injection. Before the corner is ground, the concentration of the P base region is the same on any horizontal plane. Figure 4 , the line graph marked with the color of the conventional structure shows that the concentration is a straight line on the same horizontal plane. A typical negative bevel shape terminal is as follows Figure 2 As shown in , its main working principle is to use the bevel shape to widen the depletion region of the bevel surface, thereby reducing the surface electric field and increasing the blocking voltage. The table terminal structure is formed by mechanical grinding process, and the manufacturing process is relatively mature, but its high temperature leakage current is large and the terminal size is large.

[0005] In view of the above problems, in the prior art, one solution adopts planar VLD technology, in which a region with impurity concentration gradually decreasing from the main junction position to the terminal end is injected into the edge of the main junction to assist in sharing the electric field of the terminal part, so as to achieve the effect of improving the reverse blocking capability of the device. Compared with the negative slope device, the terminal area is small and the utilization area of ​​the active area of ​​the silicon wafer is increased.

[0006] In the prior art, another solution is to adopt a stepped trench-field limiting ring structure composite terminal structure. The field limiting ring of the terminal structure is formed simultaneously with the main junction. Almost all the boron diffusion area is removed by chemical corrosion or plasma etching (ICP) technology to make the terminal part into a step shape. The field limiting ring is used to penetrate to effectively disperse the electric field concentration near the main junction. At the same time, the heavily doped P+ base region on the field limiting ring is removed, the charge amount of the space charge region is effectively controlled, and its depletion layer is forced to expand further to reduce the surface electric field and increase the terminal breakdown voltage.

[0007] In the prior art, another solution is to adopt a lateral variable doping-JTE (junction terminal extension) composite terminal structure. On the outside of the main junction of the active area, a resistance area, a lateral variable doping area and a junction terminal extension area are arranged in sequence, and the lateral variable doping area and the junction terminal extension area overlap with each other, so that the doping concentration at the end of the composite terminal structure is increased and the curvature radius is increased, which can not only reduce the electric field strength on the surface of the terminal structure and increase the terminal breakdown voltage, but also inhibit the influence of the charge in the passivation film of the terminal structure on its surface, thereby improving the stability of the withstand voltage.

[0008] For example, a Chinese patent with publication number CN218730801U discloses a silicon carbide composite terminal structure, wherein a bevel etched area is provided on the epitaxial layer; a mask structure is deposited on the surface of the bevel etched area; the high side of the bevel etched area is the active area of ​​the silicon carbide device, and the low side of the bevel etched area is the edge area of ​​the silicon carbide device; a junction terminal extension structure and a field limiting ring structure are provided on the bevel etched area.

[0009] For another example, a Chinese patent application with publication number CN115377189A discloses a terminal structure of a silicon carbide device and a method for preparing the same. By setting a P-type ion implantation region in a bevel etched region and setting an N+ implantation cutoff ring at the terminal edge on the bevel etched region side, the implantation depth of the terminal structure of the silicon carbide device can be deepened. The bevel etched terminal technology can also make the electric field distribution tend to be flat, effectively reducing the local electric field on the device surface and improving the reliability and stability of the device. Summary of the invention

[0010] The invention discloses a terminal structure of a power semiconductor device, thereby reducing the size of the terminal structure, making the active area larger, and improving the breakdown voltage of the power semiconductor device.

[0011] According to one aspect of the present invention, a terminal structure of a power semiconductor device is provided, wherein the P base region in the terminal structure is a JTE structure; and the terminal structure is a negative bevel structure. The JTE structure includes a plurality of continuous JTE regions, the doping concentration of the JTE region at the surface position is continuous, and the doping concentration at the bottom of the JTE region, the junction between the JTE region and the active region, and the junction between the JTE regions is discontinuous.

[0012] According to another aspect of the present invention, a terminal structure of a power semiconductor device is provided, wherein the P base region and the P anode region in the terminal structure are both JTE structures; the terminal structure is a double negative bevel structure. The JTE structure includes a plurality of continuous JTE regions, the doping concentration of the JTE region at the surface position is continuous, and the doping concentration at the bottom of the JTE region, the junction between the JTE region and the active region, and the junction between the JTE regions is discontinuous.

[0013] Preferably, the junction depth of the JTE region is consistent with the junction depth of the P base region or the P anode region of the active region.

[0014] Preferably, the junction depth of the JTE region decreases gradually toward the edge of the terminal structure.

[0015] Preferably, in the same horizontal plane, the doping concentrations inside different JTE regions are the same.

[0016] Preferably, on the same horizontal plane, different JTE regions have different internal doping concentrations, which gradually decrease toward the terminal edge.

[0017] Preferably, the doping concentration of the JTE region is 5E11-5E14 cm -2 , the junction depth ranges from 90 to 170μm.

[0018] Preferably, the doping element is aluminum or gallium.

[0019] According to another aspect of the present invention, a vertically structured semiconductor device is provided. The vertically structured semiconductor device includes a source region and a terminal region. The terminal region adopts the above-mentioned terminal structure.

[0020] Preferably, the semiconductor device is a common thyristor, a turn-off thyristor, a gate-commutated thyristor, an integrated gate-commutated thyristor or other device with beveled edge terminals.

[0021] According to another aspect of the present invention, a power device is provided, wherein the power device adopts the above-mentioned semiconductor device.

[0022] According to another aspect of the present invention, there is provided a method for manufacturing the terminal structure of the above-mentioned power semiconductor device, characterized in that the manufacturing method comprises the following steps: using a photolithography mask to complete the doping of the terminal structure to form a JTE region; after completing the manufacturing of the remaining structures of the power semiconductor device, grinding the terminal structure to form a negative bevel structure.

[0023] Preferably, the JTE region is formed by photolithography-ion implantation-high temperature junction pushing.

[0024] Preferably, photolithography is used to leak out windows in the active area and the terminal area that need to be implanted, and then ion implantation is performed, with an implantation dose of 5E11-5E14cm -2 Finally, high temperature knot pushing is carried out, and the knot pushing depth is 90 to 170 μm.

[0025] Preferably, the JTE region and the active region are implanted simultaneously, and the concentration and depth of the JTE region are controlled by a photolithography mask.

[0026] Preferably, a pre-diffusion-etching-diffusion method is adopted.

[0027] Preferably, a closed-tube diffusion method is used to pre-diffuse a certain depth of P-type doping layer on the front and back sides of the chip, the depth is 2-10μm, and the part of the terminal area that is not wanted to be injected is etched away by photolithography with the help of a photolithography mask. The etching depth is slightly greater than the deposition thickness of 1-2μm, and then high-temperature diffusion is performed, and the diffusion junction depth is 90~170μm.

[0028] Preferably, the width of the implantation window and the implantation interval of the photolithography mask are determined according to the junction depth and diffusion concentration of the JTE region and the length of the negative bevel structure.

[0029] Preferably, the total size of the implantation window and implantation interval of the photolithography mask corresponding to the JTE region is kept constant, and the implantation interval gradually increases toward the edge of the chip.

[0030] The terminal structure of the power semiconductor device according to the present invention adopts a composite terminal structure of JTE and a polished table, and the JTE structure is used to reduce the charge of the P base region in the terminal area, widen the width of the depletion layer at the edge of the bevel, and reduce the surface electric field strength; at the same time, the JTE modulates the electric field in the body, reduces the electric field concentration, further reduces the surface electric field strength, increases the breakdown voltage, reduces the terminal size, and solves the problem of large size of the table terminal structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A top view of an existing GCT chip;

[0032] Figure 2 It is a schematic diagram of the terminal structure of an existing power semiconductor device;

[0033] Figure 3A is a schematic diagram of a terminal structure of a power semiconductor device according to an embodiment of the present invention, wherein a photolithography mask is schematically shown;

[0034] Figure 3B A schematic diagram of a terminal structure of a power semiconductor device according to another embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of the doping concentration of the terminal structure of the power semiconductor device;

[0036] Figure 5 is a schematic diagram of a photolithography mask for a power semiconductor device according to another embodiment of the present invention, wherein the shaded portion represents an implantation window;

[0037] Figure 6 A comparison diagram of electric field distribution between a conventional terminal structure and the terminal structure of the present application;

[0038] Figure 7 A schematic diagram of the terminal structure of the reverse-blocking IGBT structure according to the present invention;

[0039] Figure 8 The schematic diagram shows the principle of reducing the surface electric field by the terminal structure of the present invention. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0041] like Figure 3A and 3B As shown, in the terminal structure of the power semiconductor device according to the present invention, the active area is P+ anode area, N-type buffer layer, N-drift area, P base area, P+ base area and N+ emitter area from anode to cathode. The terminal structure is P+ anode area, N-type buffer layer, N-drift area, P base area from anode to cathode. According to an embodiment of the present invention, the side of the terminal structure is a negative bevel structure, that is, a part of the P base area and the N-drift area is eliminated. The P base area of ​​the terminal structure is a JTE structure, including one or more continuous JTE areas (for example, JTE1, JTE2, JTE3, etc.). Figure 3A , Figure 3B and Figure 7Three JTE regions, namely JTE1, JTE2 and JTE3, are shown in the figure. According to the present invention, the number of JTE regions can be more. The JTE region is formed by a photolithography mask. The width of the injection window and the injection interval of the photolithography mask are determined according to the junction depth and diffusion concentration of the JTE region and the length of the negative bevel structure. Specifically, there is a certain interval width between the injection window of the JTE region and the injection window of the P base region of the active region, and the interval width is determined according to the junction depth of the P base region of the terminal structure. Exemplarily, for a P base region with a depth of 150μm, the width of the injection window can be set to 100-150μm to ensure that the concentration at the surface and near the surface of the JTE region can be connected, but it is discontinuous at the bottom of the JTE region, at the junction of the active region and the JTE region, and at the junction between the JTE regions, see. Figure 4 .

[0042] The JTE region is formed mainly by means of a photolithography mask. Figure 3A The photolithography mask shown is for Figure 3A The JTE junction depth in the active area is the same as the P base region in the active area. It is sufficient to open a window in the injection area, that is, to open as many windows as there are injection areas, so that the junction depth of the JTE area is consistent with the junction depth of the P base region in the active area. In this case, the doping distribution of the JTE area on the same horizontal plane can be seen in Figure 4 The line graph marked with the patent structure color shows the concentration distribution of the terminal JTE region. In the same horizontal plane, the internal doping concentration of different JTE regions is the same.

[0043] Preferably, as another embodiment, see Figure 3B , different JTE regions have different internal doping concentrations. Figure 4 , the line graph marked with the color of the patent optimized structure shows the concentration distribution of the JTE region on the same horizontal plane. Among them, on the same horizontal plane, the internal doping concentration of different JTE regions is different, and gradually decreases toward the edge of the terminal. According to this embodiment, it is possible to further reduce the charge of the P base region in the terminal area and increase the expansion of the depletion layer in the edge area. According to the terminal structure of this embodiment, the photolithography mask is set to keep the total size of the injection window and the injection interval (that is, the spacing between the injection windows) constant, and the injection interval gradually increases toward the edge of the chip, see Figure 5 In this way, the junction depth H of the JTE region decreases gradually toward the edge of the termination region, see Figure 3B .

[0044] According to another embodiment of the present invention, Figure 7As shown, the terminal structure combining negative bevel and JTE is suitable for a reverse resistance device with a symmetrical structure. In the reverse resistance device, the terminal structure includes P+ anode region, P anode region, N-drift region, and P base region from anode to cathode in sequence. The side of the terminal structure is a double negative bevel structure that eliminates a portion of the P+ anode region, the P anode region, the P base region, and the N-drift region, and the P anode region and the P base region of the terminal structure are both JTE structures. In the aforementioned embodiment, the JTE region is formed in the P base region, and in this embodiment, the JTE region is also formed in the P anode region. The JTE structure is used to reduce the charge of the P anode region in the terminal region, widen the edge depletion layer, and reduce the surface electric field strength; at the same time, the JTE modulates the electric field in the body, reduces the electric field concentration, further reduces the surface electric field strength, increases the breakdown voltage, and reduces the terminal size. Moreover, the negative bevel structure widens the depletion region in the P anode region, thereby reducing the surface electric field and increasing the blocking voltage. Therefore, in the above-mentioned embodiment, the description of the P base region is applicable to the description related to the P anode region in this embodiment.

[0045] like Figure 8 As shown, according to the present invention, the bevel terminal structure improves the breakdown voltage mainly by reducing the edge electric field, and the large concentration gradient diffusion junction and the small negative bevel angle are combined to achieve the reduction of the surface electric field. Figure 8 In, W S is the width of the depletion layer extending along the surface; W p is the depletion layer width on the diffusion side of the junction; W N is the depletion layer width on one side of the drift region. Considering the effect of the bevel angle on the depletion layer at the edge, in order to obtain the charge balance between the P side and the N side of the PN junction, the depletion layer of the N-type region will shrink at the edge until it is pinned to the PN junction. At the same time, the depletion layer of the P-type region will expand at the edge to compensate for the removed charge (represented by Q1 in the figure). The depletion layer expansion near the edge of the P-type region is manifested as a triangle with an area of ​​Q2, and its area is equal to the removed charge Q1. The introduction of the JTE structure and the reasonable setting of its position reduce the charge of the P base region in the terminal region compared to the conventional terminal region P base region full injection direct angle grinding structure, so the depletion layer will further expand along the surface of the P base region, making the depletion layer width W at the surface S Furthermore, the JTE structure can also modulate the electric field in the body, making the electric field distribution in the body more uniform, reducing the maximum electric field in the body, and also reducing the impact on the surface electric field accordingly. Figure 6 As shown, the electric field strength of the conventional structure and the patented structure at the same breakdown voltage is that the electric field strength of the conventional structure is more concentrated and greater, while the electric field strength of the patented structure is relatively uniform.

[0046] According to the present invention, a terminal structure of a power semiconductor device and a manufacturing method thereof are provided. The manufacturing method of the terminal structure of a power semiconductor device according to the present invention mainly adjusts the process according to the substrate material and the structure of the power semiconductor device. Exemplarily, taking a silicon substrate as an example, the manufacturing method of the terminal structure of a power semiconductor device is further described.

[0047] Substrate selection and pretreatment: Select an N-type substrate with a suitable voltage level and chemically clean its surface. The substrate concentration doping range is 5E11-1E14cm -3 , thickness 200-1700μm.

[0048] Back FS layer formation: formed by epitaxy or implantation, where the back FS layer doping concentration ranges from 1E15-5E16cm -3 , thickness 10-50μm. For the reverse resistance type device with symmetrical structure, this step of the process flow is omitted.

[0049] Formation of P base region and terminal JTE region: Method 1: Use photolithography-ion implantation-high temperature junction pushing. Use photolithography to leak out the windows that need to be implanted in the active area and terminal area, and then perform ion implantation, with an implantation dose of 5E11~5E14cm -2 The implanted element can be aluminum or gallium, and finally a high-temperature push junction is performed, with a junction depth of 90 to 170 μm. The terminal JTE region and the active region P base region are implanted simultaneously, and the JTE region is controlled by a photolithography mask. For a structure with the same JTE junction depth and active region P base region, the photolithography mask design is as follows: Figure 3A As shown, it is sufficient to open a window in the injection area, that is, several windows are opened for several injection areas. For the structure of the JTE where the junction depth decreases gradually toward the edge, the photolithography mask design adopts the total size of the injection window and the injection interval to remain constant, and the injection interval gradually increases toward the edge of the chip. Method 2: Use the pre-diffusion-etching-diffusion method. A closed-tube diffusion method is used to pre-diffusion a certain depth of P-type doping layer on the front and back of the chip. The diffusion depth is 2-10μm, and the diffusion element can be aluminum or gallium. Then, the P-type doping layer on the back is removed by etching or single-sided polishing (for reverse-blocking devices with symmetrical structures, this step is omitted). With the help of the photolithography mask, the part of the terminal area that is not to be injected is etched away by the photolithography etching method. The etching depth is slightly greater than the deposition thickness of 1-2μm, and then high-temperature diffusion is performed, and the diffusion junction depth is 90-170μm. For the requirements of the photolithography mask, the same design concept as the first method is still maintained.

[0050] P+ base region formation: The P+ base region is formed by ion implantation and push junction method, with a concentration range of 1E16-1E20cm -3 , junction depth 10-50μm, and the implanted element can be boron.

[0051] N+ emitter region pre-diffusion: The N+ emitter region is formed by pre-diffusion, with a junction depth of 5-10μm, and the impurity element can be phosphorus.

[0052] N+ emitter mesa etching and N+ emitter formation: Photolithography window opening, wet or dry process or a combination of both to etch the N+ source mesa, forming the N+ source mesa, and then diffuse to form the N+ source region, with a concentration range of 1E18-1E21cm -3 , junction depth 10-30μm.

[0053] Anode P+ emitter formation: The anode P+ emitter is formed by ion implantation and push junction method, with a concentration range of 5E16-1E20cm -3 , junction depth 1-20μm, and the implanted element can be boron.

[0054] Formation and etching of oxide layer: The oxide layer is formed by chemical vapor deposition, and the cathode electrode and gate electrode contact windows are photoetched.

[0055] Formation of cathode and gate electrodes: metal deposition and photolithography are performed by evaporation or sputtering to form cathode and gate electrodes. The material may be Al or a composite metal layer of Al and other materials.

[0056] Formation of the anode electrode: metal deposition and photolithography are performed by evaporation or sputtering to form the anode electrode. The material may be Al or a composite metal layer of Al and other materials.

[0057] Formation of the front passivation layer: using at least one material selected from the group consisting of polyimide (PI), amorphous hydrogenated carbon (aC:H, also known as diamond-like carbon DLC) or an inorganic-organic composite material, polyparaxylene and a phenolic resin containing polymer particles.

[0058] Terminal shaping and passivation protection: The terminal is subjected to angle grinding, cleaning, passivation, rounding, etc. to complete terminal shaping and passivation protection.

[0059] The present invention also relates to a semiconductor device with a vertical structure. The semiconductor device with a vertical structure comprises a source region and a terminal region, and the terminal region adopts the above-mentioned terminal structure. The semiconductor device with a vertical structure is, for example, a common thyristor, a turn-off thyristor, a gate-commutated thyristor, an integrated gate-commutated thyristor or other devices with beveled edge terminals.

[0060] The present invention also relates to a power device, which uses the vertical structure semiconductor device mentioned above. The power device is made of silicon substrate material or silicon carbide, gallium nitride and other materials.

[0061] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A terminal structure of a power semiconductor device, characterized in that: The P base region in the terminal structure is a JTE structure; the terminal structure is a negative bevel structure, The JTE structure includes a plurality of continuous JTE regions, the doping concentration of the JTE region at the surface is continuous, and the doping concentration at the bottom of the JTE region, at the junction of the JTE region and the active region, and at the junction between the JTE regions is discontinuous; Wherein, the junction depth of the JTE region is consistent with the junction depth of the P base region or the P anode region of the active region; or the junction depth of the JTE region decreases successively toward the edge direction of the terminal structure; On the same horizontal plane, the doping concentrations inside different JTE regions are the same; or on the same horizontal plane, the doping concentrations inside different JTE regions are different and gradually decrease toward the terminal edge.

2. A terminal structure of a power semiconductor device, characterized in that: The P base region and the P anode region in the terminal structure are both JTE structures; the terminal structure is a double negative bevel structure, The JTE structure includes a plurality of continuous JTE regions, the doping concentration of the JTE region at the surface is continuous, and the doping concentration at the bottom of the JTE region, at the junction of the JTE region and the active region, and at the junction between the JTE regions is discontinuous; Wherein, the junction depth of the JTE region is consistent with the junction depth of the P base region or the P anode region of the active region; or the junction depth of the JTE region decreases successively toward the edge direction of the terminal structure; On the same horizontal plane, the doping concentrations inside different JTE regions are the same; or on the same horizontal plane, the doping concentrations inside different JTE regions are different and gradually decrease toward the terminal edge.

3. The terminal structure of a power semiconductor device according to claim 1 or 2, characterized in that: The doping concentration of the JTE region is 5E11~5E14cm -2 , the junction depth ranges from 90 to 170 μm.

4. The terminal structure of a power semiconductor device according to claim 1 or 2, characterized in that: The doping element is aluminum or gallium.

5. A vertically structured semiconductor device, characterized in that: The vertically structured semiconductor device comprises a source region and a terminal region, and the terminal region adopts a terminal structure as claimed in any one of claims 1 to 4.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device is a common thyristor, a turn-off thyristor, a gate-commutated thyristor, an integrated gate-commutated thyristor or other device with a beveled edge terminal.

7. A power device, characterized in that: The power device adopts the semiconductor device as claimed in claim 5 or 6.

8. A method for manufacturing a terminal structure of a power semiconductor device according to any one of claims 1 to 5, characterized in that: The manufacturing method comprises the following steps: Using a photolithography mask, doping of the terminal structure is completed to form a JTE region; After the remaining structures of the power semiconductor device are manufactured, the terminal structure is ground to form a negative bevel structure.

9. The manufacturing method according to claim 8, characterized in that: The JTE region is formed by photolithography-ion implantation-high temperature junction pushing.

10. The manufacturing method according to claim 9, characterized in that: Use photolithography to leak out the windows that need to be injected in the active area and terminal area, and then perform ion implantation with an implantation dose of 5E11~5E14cm -2 Finally, high temperature knot pushing is carried out, and the knot pushing depth is 90~170μm.

11. The manufacturing method according to claim 10, characterized in that: The JTE region and the active region are implanted simultaneously, and the concentration and depth of the JTE region are controlled by a photolithography mask.

12. The manufacturing method according to claim 8, characterized in that: The pre-diffusion-etching-diffusion method is adopted.

13. The manufacturing method according to claim 12, characterized in that: A closed-tube diffusion method is used to pre-diffuse a certain depth of P-type doping layer on the front and back sides of the chip, with a depth of 2-10μm. The part of the terminal area that is not wanted to be injected is etched away using a photolithography mask and a photolithography etching method. The etching depth is slightly greater than the deposition thickness of 1-2μm, and then high-temperature diffusion is performed, with a diffusion junction depth of 90~170μm.

14. The manufacturing method according to claim 8, characterized in that: The width of the implantation window and the implantation interval of the photolithography mask are determined according to the junction depth and diffusion concentration of the JTE region and the length of the negative bevel structure.

15. The manufacturing method according to claim 8, characterized in that: The total size of the implantation window and implantation interval of the photolithography mask corresponding to the JTE region remains constant, and the implantation interval gradually increases toward the edge of the chip.

16. The manufacturing method according to claim 8, characterized in that: The doping element is aluminum or gallium.

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