Control Method, Voltage Prediction System, and Computer-Readable Storage Medium

Abstract

The present application discloses a control method, a voltage prediction system, and a computer-readable storage medium. The method includes: receiving an operation instruction for the phase change memory, obtaining status information based on the operation instruction; generating a relevant address based on the operation instruction and the status information; and operating the phase change memory based on the relevant address. By the above method, when an operation instruction is received, a relevant address is generated based on the operation instruction and the status information, so as to operate the phase change memory through the relevant address, improve the stability of the relevant address of the phase change memory, reduce crosstalk, and improve the stability of the phase change memory.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a control method, a voltage prediction system, and a computer-readable storage medium. Background Art

[0002] Phase Change Memory (PCM) has excellent characteristics such as high integration, low power consumption, and non-volatility, and is one of the storage media for non-volatile memory. Among them, during the operation of the phase change memory, the relevant addresses related to the operation process in the phase change memory may be unstable, resulting in crosstalk. Summary of the Invention

[0003] In view of the above problems, this application provides a control method, a voltage prediction system, and a computer-readable storage medium.

[0004] In a first aspect, this application provides a control method for a phase change memory, including:

[0005] Receiving an operation instruction for the phase change memory, and obtaining status information based on the operation instruction;

[0006] Generating a relevant address based on the operation instruction and the status information;

[0007] Operating the phase change memory based on the relevant address.

[0008] In some embodiments, the operation instruction includes a read instruction, and the relevant address includes a first relevant address; the step of obtaining status information based on the operation instruction includes:

[0009] Obtaining a read address from the read instruction, and obtaining an address wear value corresponding to the read address, where the status information includes the address wear value;

[0010] The step of generating a relevant address based on the operation instruction and the status information includes:

[0011] Generating the first relevant address based on the read address and the address wear value;

[0012] The step of operating the phase change memory based on the relevant address includes:

[0013] Writing to the phase change memory based on the first relevant address.

[0014] In some embodiments, the operation instruction includes a read instruction, and the method further includes:

[0015] Obtaining a predicted voltage based on the status information, where the status information further includes: temperature information of the read address;

[0016] Read the phase change memory based on the read instruction and the predicted voltage.

[0017] In some embodiments, the method further includes:

[0018] Obtain a plurality of preset voltage levels, and the predicted voltage corresponds to one of the plurality of preset voltage levels;

[0019] In response to a failed read of the phase change memory, switch the preset voltage level;

[0020] Update the predicted voltage based on the switched preset voltage level and the status information;

[0021] Read the phase change memory based on the read instruction and the updated predicted voltage.

[0022] In some embodiments, the step of switching the preset voltage level in response to a failed read of the phase change memory includes:

[0023] In response to a failed read of the phase change memory, count the number of failed reads of the phase change memory;

[0024] In response to the number being less than a preset number, switch the preset voltage level.

[0025] In some embodiments, the operation instruction includes a write instruction, and the relevant address includes a second relevant address; the step of obtaining status information based on the operation instruction includes:

[0026] Obtain a write address from the write instruction, and obtain an address wear value corresponding to the write address;

[0027] The step of generating a relevant address based on the operation instruction and the status information includes:

[0028] Generate the second relevant address based on the write address and the address wear value;

[0029] The step of operating the phase change memory based on the relevant address includes:

[0030] Write to the phase change memory based on the second relevant address.

[0031] In some embodiments, the method further includes:

[0032] Perform equalization processing on the write data corresponding to the write instruction;

[0033] Write the equalized write data into the phase change memory.

[0034] Second aspect, the present application provides a voltage prediction system, including:

[0035] A status information generation module, configured to receive an operation instruction for the phase change memory from a reading and writing device, and obtain status information based on the operation instruction;

[0036] An address prediction module, respectively connected to the status information generation module and the phase change memory, the address prediction module is configured to generate a relevant address based on the operation instruction and the status information, and operate the phase change memory based on the relevant address.

[0037] In some embodiments, the operation instruction includes a read instruction, and the voltage prediction system further includes a voltage prediction module, respectively connected to the status information generation module and the phase change memory, the voltage prediction module is configured to obtain a predicted voltage based on the status information, and read the phase change memory based on the read instruction and the predicted voltage.

[0038] Third aspect, the present application provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and the computer program can implement the above control method when being executed by a processor.

[0039] Differing from the prior art: The present application receives an operation instruction for the phase change memory, obtains status information based on the operation instruction; generates a relevant address based on the operation instruction and the status information; operates the phase change memory based on the relevant address. By the above method, a relevant address is generated based on the operation instruction and the status information when the operation instruction is received, so as to operate the phase change memory through the relevant address, improve the stability of the relevant address of the phase change memory, reduce crosstalk, and improve the stability of the phase change memory. Description of the Drawings

[0040] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered as a limitation to the present application. Moreover, in all the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0041] Figure 1 is a schematic flowchart of an embodiment of the control method of the phase change memory of the present application;

[0042] Figure 2 is Figure 1 a schematic framework diagram of an embodiment of the voltage prediction system in

[0043] Figure 3 is a schematic flowchart of another embodiment of the control method of the phase change memory of the present application;

[0044] Figure 4 is a schematic flowchart of another embodiment of the control method for the phase change memory of the present application;

[0045] Figure 5 is Figure 4 a schematic flowchart of an embodiment of step S304 in

[0046] Figure 6 is a schematic flowchart of yet another embodiment of the control method for the phase change memory of the present application;

[0047] Figure 7 is a schematic framework diagram of an embodiment of the computer-readable storage medium of the present application. Detailed Embodiments

[0048] Hereinafter, embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and thus are only examples and should not be used to limit the protection scope of the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above accompanying drawings are intended to cover non-exclusive inclusion.

[0050] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0051] Referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0052] In the description of the embodiments of the present application, the term "a plurality of" refers to two or more (including two). Similarly, "a plurality of groups" refers to two or more groups (including two groups), and "a plurality of pieces" refers to two or more pieces (including two pieces).

[0053] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0054] Please refer to Figure 1 and Figure 2 as shown in Figure 1 is a schematic flowchart of an embodiment of the control method of the phase change memory of the present application; Figure 2 is Figure 1 a schematic framework diagram of an embodiment of the voltage prediction system in . The control method of this embodiment is used to read or write to the phase change memory 20, and can be applied to the voltage prediction system 10. The voltage prediction system 10 is connected to the phase change memory 20, and the voltage prediction system 10 is also connected to the reading and writing device 30.

[0055] Optionally, the voltage prediction system 10 can be set in a CXL (Compute Express Link, high-speed interconnect technology) controller chip. The CXL controller chip is set between the CPU (Central Processing Unit) in the computer system and the phase change memory 20, and is used to control the CPU to read or write to the phase change memory 20.

[0056] The control method of this embodiment includes the following steps:

[0057] S101: Receive an operation instruction for the phase change memory 20, and obtain status information based on the operation instruction.

[0058] Receiving an operation instruction for the phase change memory 20 means that the voltage prediction system 10 receives an operation instruction from the reading and writing device 30. For example, the reading and writing device 30 is connected to the voltage prediction system 10 through a reading and writing bus, and the reading and writing device 30 sends an operation instruction to the voltage prediction system 10. Among them, the operation instruction includes a read instruction and a write instruction. The read instruction means that the reading and writing device 30 reads data from the phase change memory 20 through the voltage prediction system 10, and the write instruction means that the reading and writing device 30 writes data to the phase change memory 20 through the voltage prediction system 10.

[0059] Obtaining status information based on the operation instruction means that the voltage prediction system 10 obtains status information based on the operation instruction. For example, if the voltage prediction system 10 receives an operation instruction from the reading and writing device 30, the voltage prediction system 10 obtains status information.

[0060] S102: Generate a relevant address based on the operation instruction and the status information.

[0061] Generating a relevant address based on the operation instruction and the status information means that the voltage prediction system 10 generates a relevant address based on the operation instruction and the status information. For example, the voltage prediction system 10 generates a relevant address through a relevant address prediction model based on the operation instruction and the status information. The relevant address prediction model can be a relevant address prediction model in the prior art, which will not be elaborated here. Among them, the relevant address is an address related to the operation address in the operation instruction, such as an address adjacent to the operation address; if the operation instruction is a read instruction, the operation address is the read address; if the operation instruction is a write instruction, the operation address is the write address.

[0062] S103: Operate the phase change memory 20 based on the relevant address.

[0063] Operating the phase change memory 20 based on the relevant address means that the voltage prediction system 10 operates the phase change memory 20 based on the first relevant address. Among them, operating the phase change memory 20 based on the relevant address means writing to the relevant address of the phase change memory 20 or reading from the relevant address of the phase change memory 20.

[0064] In this embodiment, by receiving an operation instruction for the phase change memory 20, the status information is obtained based on the operation instruction; a relevant address is generated based on the operation instruction and the status information; and the phase change memory 20 is operated based on the relevant address. In the above manner, a relevant address is generated based on the operation instruction and the status information when the operation instruction is received, so as to operate the phase change memory 20 through the relevant address, improve the stability of the relevant address of the phase change memory 20, reduce crosstalk, and improve the stability of the phase change memory 20.

[0065] According to some embodiments of the present application, the operation instruction of this embodiment includes a read instruction, and the relevant address includes a first relevant address. Step S101 includes: obtaining a read address from the read instruction, obtaining an address wear value corresponding to the read address, and the status information includes the address wear value.

[0066] Among them, the voltage prediction system 10 obtains a read address from the read instruction and obtains an address wear value corresponding to the read address. That is, the voltage prediction system 10 receives a read instruction from the reading and writing device 30, and the read instruction includes a read address, and the read address refers to the address where the voltage prediction system 10 reads the phase change memory 20. The address wear value refers to the number of times of writing to the same address of the phase change memory 20, and the address wear value corresponding to the read address refers to the number of times of writing to the read address of the phase change memory 20.

[0067] Step S102 includes: generating a first relevant address based on the read address and the address wear value.

[0068] The voltage prediction system 10 generates a first correlated address based on the read address and the address wear value. For example, the voltage prediction system 10 generates the first correlated address through a correlated address prediction model based on the read address and the address wear value. Wherein, the first correlated address is an address related to the read address, such as an address adjacent to the read address.

[0069] Step S103 includes: writing to the phase change memory 20 based on the first correlated address.

[0070] The voltage prediction system 10 writes to the phase change memory 20 based on the first correlated address.

[0071] Optionally, the voltage prediction system 10 compares the address wear value corresponding to the read address with a preset wear value; in response to the address wear value corresponding to the read address being greater than or equal to the preset wear value, that is, the read address wear reaches the preset degree, the voltage prediction system 10 writes to the phase change memory 20 based on the first correlated address. In response to the address wear value corresponding to the read address being less than the preset wear value, the voltage prediction system 10 does not need to write to the phase change memory 20.

[0072] During the process that the voltage prediction system 10 reads the phase change memory 20 based on the read address and the predicted voltage, the medium current of the phase change memory 20 corresponding to the read address is large, and the medium temperature adjacent to the read address continuously rises, resulting in instability of other addresses adjacent to the read address of the phase change memory 20 and generating read crosstalk.

[0073] In this embodiment, by generating the first correlated address based on the read address and the address wear value and writing to the phase change memory 20 based on the first correlated address. In this way, the first correlated address of the phase change memory 20 can be rewritten, reducing read crosstalk and improving the stability of the phase change memory 20.

[0074] Optionally, the status information further includes the temperature information of the read address, and the temperature information of the read address refers to the temperature of the PCM particles corresponding to the read address. Step S102 includes: generating the first correlated address based on the temperature information of the read address and the address wear value.

[0075] Wherein, the voltage prediction system 10 generates the first correlated address based on the temperature information of the read address and the address wear value. For example, the voltage prediction system 10 generates the first correlated address through a correlated address prediction model based on the temperature information of the read address and the address wear value.

[0076] This embodiment generates the first correlated address based on the temperature information of the read address and the address wear value, improving the accuracy of the first correlated address.

[0077] According to some embodiments of the present application, please refer to Figure 3 as shownFigure 3 It is a schematic flowchart of another embodiment of the control method for the phase change memory of the present application. Based on Figure 1 the control method shown, the control method of this embodiment further includes the following steps:

[0078] S201: Obtain a predicted voltage based on the state information.

[0079] The operation instructions of this embodiment include a read instruction. The voltage prediction system 10 receives the read instruction from the read / write device 30 and obtains the state information based on the read / write instruction. For example, when the voltage prediction system 10 receives the read instruction from the read / write device 30, the voltage prediction system 10 obtains the state information.

[0080] Obtaining the predicted voltage based on the state information means that the voltage prediction system 10 receives the read instruction, and the voltage prediction system 10 obtains the predicted voltage based on the state information. For example, the voltage prediction system 10 calculates the predicted voltage through a voltage prediction model for the state information. The voltage prediction model can be a voltage prediction model in the prior art and will not be elaborated here.

[0081] S202: Read the phase change memory 20 based on the read instruction and the predicted voltage.

[0082] Reading the phase change memory 20 based on the read instruction and the predicted voltage means that the voltage prediction system 10 reads the phase change memory 20 based on the read instruction and the predicted voltage. For example, the voltage prediction system 10 is connected to the phase change memory 20 through a read bus, and the voltage prediction system 10 reads the phase change memory 20 based on the read instruction and the predicted voltage to read data from the phase change memory 20.

[0083] In this embodiment, a predicted voltage is obtained based on the state information, and the phase change memory 20 is read based on the read instruction and the predicted voltage. In the above manner, the electrical parameter drift of the phase change memory 20 can be avoided, and the stability of the phase change memory 20 can be improved.

[0084] According to some embodiments of the present application, please refer to Figure 4 shown Figure 4 It is a schematic flowchart of yet another embodiment of the control method for the phase change memory of the present application. The control method of this embodiment includes the following steps:

[0085] S301: Obtain a predicted voltage based on the state information.

[0086] S302: Read the phase change memory 20 based on the read instruction and the predicted voltage.

[0087] Steps S301 - S302 are the same as steps S201 - S202 and will not be elaborated here.

[0088] S303: Obtain multiple preset voltage levels, and the predicted voltage corresponds to one of the multiple preset voltage levels.

[0089] Obtain multiple preset voltage levels, and the predicted voltage corresponds to one of the multiple preset voltage levels. That is, the voltage prediction system 10 is pre-set with multiple preset voltage levels, the predicted voltage corresponds to one of the multiple preset voltage levels, and the voltage prediction system 10 obtains multiple preset voltage levels.

[0090] For example, the voltage prediction system 10 is pre-set with a preset voltage level of 0V, a preset voltage level of 1V, a preset voltage level of 2V, and a preset voltage level of 3V; where 0V, 1V, 2V, and 3V are for illustration and do not limit the preset voltage levels; the predicted voltage corresponds to the preset voltage level of 1V. In other embodiments, the voltage prediction system 10 is pre-set with a preset voltage level of 0V, a preset voltage level of 1V, a preset voltage level of 2V, and a preset voltage level of 1V.

[0091] S304: In response to a failed read of the phase change memory 20, switch the preset voltage level.

[0092] In response to a failed read of the phase change memory 20, switch the preset voltage level. That is, when the voltage prediction system 10 fails to read the phase change memory 20 through a read instruction and the predicted voltage, switch the preset voltage level.

[0093] For example, in response to a failed read of the phase change memory 20, the voltage prediction system 10 switches the preset voltage level from 1V to 2V.

[0094] S305: Update the predicted voltage based on the switched preset voltage level and the status information.

[0095] Update the predicted voltage based on the switched preset voltage level and the status information, that is, the voltage prediction system 10 updates the predicted voltage based on the switched preset voltage level and the status information. For example, the voltage prediction system 10 updates the predicted voltage through a voltage prediction model for the preset voltage level of 2V and the status information.

[0096] S306: Read the phase change memory 20 based on the read instruction and the updated predicted voltage.

[0097] Read the phase change memory 20 based on the read instruction and the updated predicted voltage, that is, the voltage prediction system 10 reads the phase change memory 20 based on the read instruction and the updated predicted voltage.

[0098] In this embodiment, in response to a failed read of the phase change memory 20, a preset voltage level is switched; based on the switched preset voltage level and status information, a predicted voltage is updated, and the phase change memory 20 is read based on the read instruction and the updated predicted voltage. In the above manner, by switching the preset voltage level to update the predicted voltage and reading the phase change memory 20 with the updated predicted voltage, the success rate of reading the phase change memory 20 by the voltage prediction system 10 can be improved, and the stability of the phase change memory 20 can be further improved.

[0099] According to some embodiments of the present application, refer to Figure 5 as shown Figure 5 is Figure 4 a schematic flowchart of an embodiment of step S304 in. In this embodiment, step S304 includes the following steps:

[0100] S401: In response to a failed read of the phase change memory 20, count the number of failed reads of the phase change memory 20.

[0101] In response to a failed read of the phase change memory 20, count the number of failed reads of the phase change memory 20. Compare the number with a preset number; in response to the number being less than the preset number, proceed to step S302; in response to the number being greater than or equal to the preset number, end.

[0102] Specifically, the voltage prediction system 10 counts the number of failed reads of the phase change memory 20 in response to a failed read of the phase change memory 20. The voltage prediction system 10 is pre-set with a preset number and compares the number with the preset number; in response to the number being less than the preset number, proceed to step S302.

[0103] For example, after the voltage prediction system 10 obtains the predicted voltage based on the status information, if the voltage prediction system 10 responds to a failed read of the phase change memory 20, the number of failed reads of the phase change memory 20 is counted as 1.

[0104] Optionally, in response to a successful read of the phase change memory 20, the number is cleared.

[0105] S402: In response to the number being less than the preset number, switch the preset voltage level.

[0106] In response to the number being less than the preset number, switch the preset voltage level; the voltage prediction system 10 switches the preset voltage level in response to the number being less than the preset number.

[0107] In this embodiment, in response to a read failure of the phase change memory 20, the number of read failures of the phase change memory 20 is counted; in response to the number being less than a preset number, the preset voltage level is switched. In the above manner, the voltage prediction system 10 is restricted from performing read failures on the phase change memory 20, reducing the wear of the phase change memory 20.

[0108] According to some embodiments of the present application, the status information of this embodiment includes at least one of an address wear value, a read / write timestamp, and the temperature of the PCM particle corresponding to the read address.

[0109] Among them, the timestamp refers to a complete and verifiable piece of data that can indicate that a piece of data has existed at a specific point in time; the read / write timestamp includes a read timestamp and a write timestamp. The read timestamp refers to the completion of reading data from the phase change memory 20 at a specific point in time, and the write timestamp refers to the completion of writing data to the phase change memory 20 at a specific point in time; the temperature of the PCM particle corresponding to the read address refers to the temperature of the PCM particle of the phase change memory 20 corresponding to the read address.

[0110] For example, the status information includes an address wear value, a read / write timestamp, and the temperature of the PCM particle corresponding to the read address. The voltage prediction system 10 calculates a predicted voltage through a voltage prediction model for the status information, that is, the voltage prediction system 10 calculates the sum of multiplying the address wear value by a first coefficient, the read / write timestamp by a second coefficient, and the PCM particle temperature by a third coefficient to obtain the predicted voltage, where the first coefficient, the second coefficient, and the third coefficient are coefficients preset by the voltage prediction system 10.

[0111] According to some embodiments of the present application, the operation instruction of this embodiment includes a write instruction, and the relevant address includes a second relevant address. Step S101 includes: obtaining a write address from the write instruction, and obtaining an address wear value corresponding to the write address. The status information includes the address wear value.

[0112] Among them, the voltage prediction system 10 obtains the write address from the write instruction and obtains the address wear value corresponding to the write address. That is, the voltage prediction system 10 receives a write instruction from the read / write device 30. The write instruction includes a write address, and the write address refers to the address where the voltage prediction system 10 writes to the phase change memory 20. The address wear value corresponding to the write address refers to the number of times of writing to the write address of the phase change memory 20.

[0113] Step S102 includes: generating a second relevant address based on the write address and the address wear value.

[0114] The voltage prediction system 10 generates a second correlated address based on the write address and the address wear value. For example, the voltage prediction system 10 generates the second correlated address based on the write address and the address wear value through a correlated address prediction model. Herein, the second correlated address is an address related to the write address, such as an address adjacent to the write address.

[0115] Step S103 includes: operating on the phase change memory 20 based on the second correlated address.

[0116] The voltage prediction system 10 writes to the phase change memory 20 based on the second correlated address.

[0117] Optionally, the voltage prediction system 10 compares the address wear value corresponding to the write address with a preset wear value; in response to the address wear value corresponding to the write address being greater than or equal to the preset wear value, that is, the write address wear reaches the preset degree, the voltage prediction system 10 writes to the phase change memory 20 based on the second correlated address.

[0118] In this embodiment, by generating the second correlated address based on the write address and the address wear value and writing to the phase change memory 20 based on the second correlated address. In the above manner, it is possible to rewrite the second correlated address of the phase change memory 20, reduce write crosstalk, and improve the stability of the phase change memory 20.

[0119] According to some embodiments of the present application, please refer to Figure 6 and Figure 2 as shown in Figure 6 is a schematic flowchart of yet another embodiment of the control method of the phase change memory of the present application. The voltage prediction system 10 of this embodiment includes an equalization module 13, and the equalization module 13 is connected to the phase change memory 20 through a write bus. On the basis of the control method shown in Figure 1 the control method of this embodiment further includes the following steps:

[0120] S501: Perform equalization processing on the write data corresponding to the write instruction.

[0121] The operation instruction of this embodiment includes a write instruction, and the write instruction includes write data. Perform equalization processing on the write data corresponding to the write instruction; that is, the voltage prediction system 10 performs equalization processing on the write data through the equalization module 13.

[0122] For example, the write data is 1111100, and the voltage prediction system 10 performs equalization processing on the write data through the equalization module 13 to obtain the equalized write data as 010101, achieving the equalization of 0 and 1. Among them, the equalization module 13 performs equalization processing on the write data using an equalization algorithm of the prior art, which will not be elaborated herein.

[0123] S502: Write the equalized write data into the phase change memory 20.

[0124] Write the balanced write data to the phase change memory 20, that is, the voltage prediction system 10 writes the balanced write data to the phase change memory 20.

[0125] In this embodiment, the equalization module 13 performs equalization processing on the write data and writes the equalized write data to the phase change memory 20; in the above manner, the 0 and 1 of the write data are equalized, which can improve the service life of the phase change memory 20.

[0126] This application also provides a voltage prediction system 10, as Figure 2 shown, the voltage prediction system 10 of this embodiment includes a status information generation module 11 and an address prediction module 14, and the address prediction module 14 is respectively connected to the status information generation module 11 and the phase change memory 20.

[0127] The status information generation module 11 is connected to the read / write device 30. For example, the read / write device 30 is connected to the status information generation module 11 through a read / write bus. Among them, the status information generation module 11 is used to receive an operation instruction for the phase change memory 20 from the read / write device 30 and obtain status information based on the operation instruction.

[0128] The address prediction module 14 is used to generate a relevant address based on the operation instruction and the status information, and operate on the phase change memory 20 based on the relevant address.

[0129] Optionally, the operation instruction includes a read instruction, the relevant address includes a first relevant address, the status information generation module 11 is used to obtain a read address from the read instruction and obtain an address wear value corresponding to the read address; the address prediction module 14 is used to generate a first relevant address based on the read address and the address wear value, and write to the phase change memory 20 based on the first relevant address.

[0130] Optionally, the operation instruction includes a write instruction, the relevant address includes a second relevant address, the status information generation module 11 is used to obtain a write address from the write instruction and obtain an address wear value corresponding to the write address; the address prediction module 14 is used to generate a second relevant address based on the write address and the address wear value, and write to the phase change memory 20 based on the second relevant address.

[0131] The status information generation module 11 of this embodiment is used to receive an operation instruction for the phase change memory 20 from the read / write device 30 and obtain status information based on the operation instruction; the address prediction module 14 is used to generate a relevant address based on the operation instruction and the status information, and operate on the phase change memory 20 based on the relevant address. In the above manner, the stability of the relevant address of the phase change memory 20 is improved, crosstalk is reduced, and the stability of the phase change memory 20 is improved.

[0132] According to some embodiments of the present application, the voltage prediction system 10 of this embodiment further includes a voltage prediction module 12, and the voltage prediction module 12 is respectively connected to the status information generation module 11 and the phase change memory 20.

[0133] The operation instruction includes a read instruction. The voltage prediction module 12 is configured to obtain a predicted voltage based on the status information, and read the phase change memory 20 based on the read instruction and the predicted voltage. The address prediction module 14 and the voltage prediction module 12 may be provided in the same module. In other embodiments, the address prediction module 14 may be independently provided from the voltage prediction module 12, which will not be elaborated herein.

[0134] The voltage prediction module 12 of this embodiment is configured to obtain a predicted voltage based on the status information, and read the phase change memory 20 based on the read instruction and the predicted voltage. In the above manner, the electrical parameter drift of the phase change memory 20 can be avoided, and the stability of the phase change memory 20 can be improved.

[0135] Optionally, the voltage prediction system 10 further includes an equalization module 13, and the voltage prediction module 12 is connected to the phase change memory 20 through the equalization module 13. The voltage prediction system 10 is further configured to, in response to receiving a write instruction, the equalization module 13 is configured to perform equalization processing on the write data to write the equalized write data into the phase change memory 20.

[0136] According to some embodiments of the present application, the voltage prediction system 10 of this embodiment is further connected to a configuration device 40, and the status information generation module 11 is connected to the configuration device 40. For example, the configuration device 40 is connected to the status information generation module 11 through a configuration bus.

[0137] The configuration device 40 is configured to configure at least one of the address wear value and the recording method of the read and write timestamps, the refresh interval of the PCM particle temperature, the voltage prediction model, the preset voltage level, the related address prediction model, and the equalization algorithm. Through the configuration device 40, it can be flexibly set to adapt to different application scenarios.

[0138] The present application also provides a computer-readable storage medium. Please refer to Figure 7 , Figure 7 is a schematic framework diagram of an embodiment of the computer-readable storage medium of the present application. As Figure 7 shown, the computer-readable storage medium 70 stores program instructions 71 that can be run by a processor, and the program instructions 71 are used to implement the steps in any of the above control method embodiments.

[0139] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be elaborated herein.

[0140] The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments. For the same or similar parts, reference can be made to each other. For the sake of brevity, they will not be elaborated herein.

[0141] In several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0142] In addition, in each embodiment of the present application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0143] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods in various embodiments of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs and other various media that can store program codes.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present application, and they should all be covered within the scope of the claims and the description of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A control method of a phase change memory, characterized in that: include: receiving an operation instruction for the phase change memory, and obtaining state information based on the operation instruction, wherein the operation instruction includes a read instruction, and the state information includes an address wear value, wherein the address wear value refers to the number of times the same address of the phase change memory is written; generating a relevant address based on the operation instruction and the state information, wherein the relevant address is an address related to the operation address in the operation instruction; operating the phase change memory based on the associated address; Obtaining a predicted voltage based on the state information, wherein the state information further includes temperature information of a read address; Reading the phase change memory based on the read instruction and the predicted voltage; Wherein, the relevant address includes a first relevant address; The step of obtaining status information based on the operation instruction comprises: Acquire a read address from the read instruction, and acquire an address wear value corresponding to the read address; The step of generating the relevant address based on the operation instruction and the status information comprises: generating the first relevant address based on the read address and the address wear value by a relevant address prediction model; The step of obtaining the predicted voltage based on the state information comprises: The predicted voltage is obtained by calculating the state information.

2. The method according to claim 1, characterized in that The step of operating the phase change memory based on the relevant address comprises: The phase change memory is written based on the first associated address.

3. The method according to claim 1, characterized in that The method further comprises: Acquire a plurality of preset voltage levels, wherein the predicted voltage corresponds to one of the plurality of preset voltage levels; In response to a failure in reading the phase change memory, switching the preset voltage level; Update the predicted voltage based on the switched preset voltage level and the state information; The phase change memory is read based on the read instruction and the updated prediction voltage.

4. The method according to claim 3, characterized in that: In response to a failure in reading the phase change memory, the step of switching the preset voltage level comprises: In response to a failure to read the phase change memory, counting the number of failures to read the phase change memory; In response to the number being less than a preset number, the preset voltage level is switched.

5. The method according to claim 1, characterized in that The relevant address includes a second relevant address; the operation instruction includes a write instruction, and the step of obtaining the status information based on the operation instruction includes: Acquire a write address from the write instruction, and acquire an address wear value corresponding to the write address, wherein the address wear value refers to the number of times the same address of the phase change memory is written; The step of generating the relevant address based on the operation instruction and the status information comprises: generating the second relevant address based on the write address and the address wear value by a relevant address prediction model; The step of operating the phase change memory based on the relevant address comprises: Writing is performed to the phase change memory based on the second associated address.

6. The method according to claim 5, characterized in that The method further comprises: Performing balanced processing on the write data corresponding to the write instruction; The equalized write data is written into the phase change memory.

7. A voltage prediction system, characterized in that: include: A state information generating module, configured to receive an operation instruction for a phase change memory from a read / write device, and obtain state information based on the operation instruction, wherein the operation instruction includes a read instruction, and the state information includes an address wear value, wherein the address wear value refers to the number of times the same address of the phase change memory is written; an address prediction module, connected to the state information generation module and the phase change memory, respectively, the address prediction module is used to generate a relevant address based on the operation instruction and the state information, and operate the phase change memory based on the relevant address, the relevant address is an address related to the operation address in the operation instruction; a voltage prediction module, connected to the state information generation module and the phase change memory, respectively, the voltage prediction module being used to obtain a predicted voltage based on the state information, and to read the phase change memory based on the read instruction and the predicted voltage; Among them, the status information generation module is used to obtain the read address from the read instruction and obtain the address wear value corresponding to the read address; the address prediction module is used to generate a first related address based on the read address and the address wear value through a related address prediction model; the voltage prediction module is used to calculate the status information to obtain the predicted voltage.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program can implement the control method according to any one of claims 1 to 6 when executed by a processor.

Images