Mini-LED Chip and Its Preparation Method

Abstract

The present invention discloses a Mini-LED chip and a preparation method thereof, relating to the field of semiconductor optoelectronic devices. The preparation method includes the following steps: S1, providing an epitaxial wafer, which includes a plurality of preset regions; S2, forming a bonding layer; S3, bonding with a second substrate; S4, forming a first through hole; the first through hole is arranged away from the edge of the preset region, and its side wall is inclined; S5, forming a first contact layer; the first contact layer covers the bottom and the side wall of a preset length of the first through hole, and it only forms an ohmic contact with the P-type semiconductor layer; S6, forming a second contact layer to obtain an intermediate; S7, forming a DBR layer on the intermediate, and etching to form a second through hole and a third through hole in the regions where the first contact layer and the second contact layer are located; S8, forming an N electrode and a P electrode to obtain an LED wafer; S9, cutting the LED wafer to obtain a Mini-LED chip. Implementing the present invention can improve the light efficiency of the Mini-LED chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a Mini-LED chip and a method for manufacturing the same. Background Art

[0002] A Mini-LED chip is an LED chip with the long side dimension of the chip ranging from 100 μm to 300 μm. It has a small volume, can effectively improve the display pixels, and has good application prospects. A common Mini-LED chip is a flip-chip Mini-LED chip, and its specific structure is as Figure 1 shown. Specifically, its forming process is as follows: grow an AlGaInP-based LED epitaxial wafer on a GaAs substrate, roughen the surface of the epitaxial wafer, bond the epitaxial wafer to a transparent substrate using BCB, remove the GaAs substrate, etch a P-type AlGaInP mesa, deposit a metal reflective layer and a barrier layer on the surfaces of the P-type AlGaInP mesa and the N-type AlGaInP, and finally fabricate an N-type electrode 100 and a P-type electrode 200. Since the area for forming the P-type electrode 200 has undergone step etching (i.e., etching to the edge of the P-type AlGaInP mesa), this results in a smaller light-emitting area and reduces the light efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a Mini-LED chip and a method for manufacturing the same, which can increase the light-emitting area of the Mini-LED chip and improve the light efficiency.

[0004] To solve the above technical problem, the present invention provides a method for manufacturing a Mini-LED chip, which includes the following steps:

[0005] S1. Provide an epitaxial wafer, the epitaxial wafer includes a first substrate and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked on the first substrate in sequence; the epitaxial wafer includes a plurality of preset regions, and each preset region forms a Mini-LED chip;

[0006] S2. Form a bonding layer on the P-type semiconductor layer;

[0007] S3. Bond the epitaxial wafer obtained in step S2 to a second substrate, and remove the first substrate;

[0008] S4. Form a first through hole; the first through hole is disposed away from the edge of the preset region, and the edge of the first through hole does not extend to any edge of the preset region; the first through hole is etched to the P-type semiconductor layer, the depth of the first through hole is greater than the total thickness of the N-type semiconductor layer and the active layer; the side wall of the first through hole is inclined, and the inclination angle ≤ 70°;

[0009] S5. Form a first contact layer in the first through hole; the first contact layer covers the bottom and a preset length of the side wall of the first through hole, and the first contact layer forms an ohmic contact only with the P-type semiconductor layer; the thickness of the first contact layer is less than the depth of the first through hole;

[0010] S6. Form a second contact layer on the N-type semiconductor layer to obtain an intermediate body;

[0011] S7. Form a DBR layer on the intermediate body, and etch to form a second through hole and a third through hole in the regions where the first contact layer and the second contact layer are located;

[0012] S8. Form an N electrode and a P electrode to obtain an LED wafer; wherein, the N electrode is electrically connected to the second contact layer through the third through hole, and the P electrode is electrically connected to the first contact layer through the second through hole;

[0013] S9. Cut the LED wafer to obtain Mini-LED chips.

[0014] As an improvement of the above technical solution, the first contact layer includes a first metal layer and a first etching barrier layer stacked in sequence on the P-type semiconductor layer; the first etching barrier layer is used to protect the first metal layer when etching the DBR layer; and / or

[0015] The second contact layer includes a second metal layer and a second etching barrier layer stacked in sequence on the N-type semiconductor layer, and the second etching barrier layer is used to protect the second metal layer when etching the DBR layer.

[0016] As an improvement of the above technical solution, the cross-sectional area of the first through hole is less than 5% of the surface area of the preset region; and / or

[0017] The top surfaces of the N electrode and the P electrode are flush.

[0018] As an improvement of the above technical solution, the first metal layer is one or more of an Au layer, an AuBe layer or an AuZn layer, and its thickness is 0.5 μm to 1 μm; and / or

[0019] The first etching barrier layer is one or more of a Ti layer, a Pt layer, a TiW layer, a Ni layer, and its thickness is 0.5 μm to 3 μm;

[0020] The second metal layer is one or more of an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, and its thickness is 0.5 μm to 1 μm; and / or

[0021] The second etching barrier layer is one or more of a Ti layer, a Pt layer, a TiW layer, and a Ni layer, and its thickness is 0.5 μm to 3 μm; and / or

[0022] The bonding layer is an Al2O3 layer and / or an SiO2 layer, and its thickness is 500 nm to 3000 nm.

[0023] As an improvement to the above technical solution, the first metal layer is an Au layer or an AuBe layer, and its thickness is 0.5 μm to 0.8 μm; and / or

[0024] The first etching barrier layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; and / or

[0025] The second metal layer is an Au layer or an AuGeNi layer, and its thickness is 0.5 μm to 0.8 μm; and / or

[0026] The second etching barrier layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; and / or

[0027] The bonding layer is an SiO2 layer, and its thickness is 500 nm to 1000 nm.

[0028] As an improvement to the above technical solution, step S5 includes:

[0029] S51. Form a first contact layer in the first through hole;

[0030] S52. Anneal the epitaxial wafer obtained in step S51 so that the first metal layer forms an ohmic contact with the P-type semiconductor layer; wherein, the annealing temperature is 300 °C to 550 °C;

[0031] Step S6 includes:

[0032] S61: Form a second contact layer on the N-type semiconductor layer;

[0033] S62. Anneal the epitaxial wafer obtained in step S61 so that the second metal layer forms an ohmic contact with the N-type semiconductor layer to obtain an intermediate; wherein, the annealing temperature is 300 °C to 400 °C.

[0034] As an improvement to the above technical solution, the N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP current spreading layer, and an N-type AlGaInP confinement layer that are sequentially stacked on the first substrate; and / or

[0035] The P-type semiconductor layer includes a P-type AlGaInP confinement layer and a P-type GaP window layer that are sequentially stacked on the active layer; and / or

[0036] A GaAs buffer layer and a GaInP etch stop layer are further sequentially provided between the first substrate and the N-type semiconductor layer; and / or

[0037] The first substrate is a GaAs substrate; and / or

[0038] The second substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate; and / or

[0039] The N electrode and the P electrode are the same or different in composition, and both are laminated structures formed by at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer.

[0040] As an improvement to the above technical solution, step S2 includes:

[0041] S21. Roughen the P-type GaP window layer;

[0042] S22. Form a bonding layer on the P-type GaP window layer after roughening; and / or

[0043] Step S3 includes:

[0044] S31. Bond the epitaxial wafer obtained in step S2 to the second substrate;

[0045] S32. Remove the first substrate, the GaAs buffer layer and the GaInP etch stop layer.

[0046] As an improvement to the above technical solution, step S6 includes:

[0047] S61: Form a second contact layer on the N-type GaAs ohmic contact layer; the width of the second contact layer is smaller than the width of the N-type GaAs ohmic contact layer;

[0048] S62. Using the second contact layer as a mask, etch and remove the N-type GaAs ohmic contact layer around the second contact layer;

[0049] S63. Etch to form an etch groove; the etch groove is close to the edge of the preset area, the first through hole is arranged away from the etch groove, and the edge of the first through hole does not extend to any edge of the etch groove;

[0050] S64. Anneal the epitaxial wafer obtained in step S63 so that the second metal layer forms an ohmic contact with the N-type GaAs ohmic contact layer to obtain an intermediate; wherein, the annealing temperature is 300°C to 400°C.

[0051] Correspondingly, the present invention also discloses a Mini-LED chip, which is prepared by the above method for preparing a Mini-LED chip.

[0052] Implementing the present invention has the following beneficial effects:

[0053] 1. In the method for preparing a Mini-LED chip of the present invention, a first through hole is provided at a position on the edge of the preset area far from the epitaxial wafer, that is, the first through hole is provided in the central area of the preset area without forming a stepped etching, which effectively reduces the loss of the light-emitting area and improves the light efficiency of the Mini-LED chip. In order to still maintain good contact between the P electrode and the P-type semiconductor layer after adopting the first through hole with this structure, on the one hand, the side wall of the first through hole is set to be inclined, and on the other hand, a bowl-shaped first contact layer is formed in the first through hole, effectively improving the contact area.

[0054] 2. In the method for preparing a Mini-LED chip of the present invention, by controlling the opening size and layout position of the first through hole, the P electrode and the N electrode are made to be at the same height. This makes it not easy to occur problems such as side tilt and false soldering during packaging, improving the packaging yield. Furthermore, it also makes it not easy to fall off and open circuit during subsequent use, improving the reliability of the Mini-LED chip. Description of the Drawings

[0055] Figure 1 is a schematic structural diagram of a Mini-LED chip in the prior art;

[0056] Figure 2 is a cross-sectional structural diagram of an epitaxial wafer in an embodiment of the present invention;

[0057] Figure 3 is a top-view structural diagram of an epitaxial wafer in an embodiment of the present invention;

[0058] Figure 4 is a schematic structural diagram of a Mini-LED chip in an embodiment of the present invention;

[0059] Figure 5 is a top-view structural diagram of a Mini-LED chip in an embodiment of the present invention;

[0060] In the figure, 100 is an N-type electrode, 200 is a P-type electrode, 1 is an epitaxial wafer, 11 is a first substrate, 12 is an N-type semiconductor layer, 121 is an N-type GaAs ohmic contact layer, 122 is an N-type AlGaInP current spreading layer, 123 is an N-type AlGaInP confinement layer, 13 is an active layer, 14 is a P-type semiconductor layer, 141 is a P-type AlGaInP confinement layer, 142 is a P-type GaP window layer, 15 is a GaAs buffer layer, 16 is a GaInP etch stop layer, 17 is a preset area, 2 is a bonding layer, 21 is an etch groove, 3 is a second substrate, 4 is a first via hole, 5 is a first contact layer, 51 is a first metal layer, 52 is a first etch stop layer, 6 is a second contact layer, 61 is a second metal layer, 62 is a second etch stop layer, 7 is a DBR layer, 71 is a second via hole, 72 is a third via hole, 8 is an N electrode, 9 is a P electrode, and 10 is a light-emitting area. Detailed implementation mode

[0061] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below.

[0062] The present invention provides a method for preparing a horizontal-structure LED chip, which includes the following steps:

[0063] S1: Provide an epitaxial wafer;

[0064] Referring to Figure 2 and Figure 3 , the epitaxial wafer 1 includes a first substrate 11, and an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14 sequentially provided on the first substrate 11. Specifically, the LED chip of the present invention can be a red, green, yellow or violet LED chip. Based on the control of the emission wavelength, different types of semiconductor layers and active layers can be selected. Exemplarily, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the N-type semiconductor layer 12 can be an N-type GaN layer, the active layer 13 can be an InGaN-GaN type multi-quantum well layer, and the P-type semiconductor layer 14 can be a P-type GaN layer and / or a P-type InGaN layer, but not limited thereto. In another embodiment, when the LED chip is a violet LED chip, the N-type semiconductor layer 12 can be an N-type AlGaN layer, the active layer 13 can be an AlGaN-AlGaN type multi-quantum well layer, and the P-type semiconductor layer 14 can be a P-type AlGaN layer and a P-type GaN layer, but not limited thereto.

[0065] Preferably, in one embodiment, the LED chip is a red LED chip. The epitaxial wafer 1 includes a GaAs buffer layer 15, a GaInP etch stop layer 16, an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14 that are sequentially disposed on a first substrate 11. Among them, the first substrate 11 is a GaAs substrate. The N-type semiconductor layer 12 includes an N-type GaAs ohmic contact layer 121, an N-type AlGaInP current spreading layer 122, and an N-type AlGaInP confinement layer 123 that are sequentially disposed on the GaInP etch stop layer 16; the P-type semiconductor layer 14 includes a P-type AlGaInP confinement layer 141 and a P-type GaP window layer 142 that are sequentially stacked on the active layer 13. In the following steps, a red LED chip is used for illustration, but the technical solution of the present invention is not limited to the red LED chip described here.

[0066] Specifically, referring to Figure 3 , the epitaxial wafer 1 includes a plurality of preset regions 17, and each of the preset regions 17 forms a Mini-LED chip subsequently, that is, after subsequent cutting and splitting, each preset region 17 corresponds to a Mini-LED chip.

[0067] S2: Form a bonding layer on the P-type semiconductor layer;

[0068] Among them, according to different subsequent bonding processes, bonding layers 2 of different materials can be formed on the P-type semiconductor layer 14. For example, when using the eutectic bonding process, an Au layer, a Cu layer, an In layer, a Pb layer, or an Sn layer can be used, but it is not limited thereto. Another example is that when using the thermocompression bonding process, an Au layer, a Cu layer, an Ag layer, or an Al layer can be used as the bonding layer 2, but it is not limited thereto.

[0069] Preferably, in one embodiment, when using the thermocompression bonding process for bonding, the bonding layer 2 can be an Al2O3 layer and / or an SiO2 layer, which can not only achieve good bonding but also improve the light extraction efficiency. Specifically, the thickness of the bonding layer 2 is 500 nm to 3000 nm. More preferably, the bonding layer 2 is an SiO2 layer, and its thickness is 500 nm to 1000 nm.

[0070] Preferably, in one embodiment, when the Mini-LED chip is a red LED chip, step S2 includes:

[0071] S21: Roughen the P-type GaP window layer;

[0072] S22: Form a bonding layer on the roughened P-type GaP window layer.

[0073] Specifically, by roughening the P-type GaP window layer 142, on the one hand, impurities on the surface of the P-type GaP window layer 142 can be removed, improving the crystal quality of subsequent layers. On the other hand, the adhesion between the bonding layer 2 and the P-type GaP window layer 142 can be enhanced. On the third hand, the light extraction efficiency can be improved.

[0074] S3: Bond the epitaxial wafer obtained in step S2 to the second substrate;

[0075] Among them, the epitaxial wafer 1 and the second substrate 3 can be bonded by bonding methods such as eutectic bonding and thermocompression bonding, but not limited to this. Preferably, the thermocompression bonding process is used for bonding. The bonding temperature is 360°C to 550°C, and the bonding pressure is 8000 kgf to 15000 kgf.

[0076] Among them, the second substrate 3 can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but not limited to this. Preferably, it is a sapphire substrate.

[0077] Specifically, after bonding, the first substrate 11 is peeled off. The first substrate 11 can be peeled off by methods such as laser lift-off or wet etching, but not limited to this.

[0078] Preferably, in one embodiment, when the Mini-LED chip is a red light LED chip, step S3 includes:

[0079] S31: Bond the epitaxial wafer obtained in step S2 to the second substrate;

[0080] S32: Remove the first substrate, the GaAs buffer layer, and the GaInP etch stop layer.

[0081] S4: Form a first through hole;

[0082] Among them, the first through hole 4 can be formed by a dry etching or wet etching process. The depth of the first through hole 4 is greater than the total thickness of the N-type semiconductor layer 12 and the active layer 13. Based on this depth control, on the one hand, the first contact layer 5 formed subsequently can only form an ohmic contact with the P-type semiconductor layer 14, preventing leakage. On the other hand, the contact area between the first contact layer 5 and the P-type semiconductor layer 14 is enlarged, optimizing the ohmic contact between the two.

[0083] Specifically, the side wall of the first through hole 4 is inclined, and the inclination angle ≤ 70°. The inclined side wall, on the one hand, can further improve the ohmic contact between the first contact layer 5 and the P-type semiconductor layer 14; on the other hand, it can improve the coating compactness of the subsequent DBR layer 7, avoiding cracks. Preferably, the inclination angle is 50° to 60°. When the inclination angle is too small, the light-emitting area will be reduced and the light-emitting efficiency will be lowered.

[0084] Specifically, the first through hole 4 is disposed away from the edge of the preset area 17, and the edge of the first through hole 4 does not extend to any edge of the preset area 17, that is, the first through hole 4 is disposed in the central area of the preset area 17 without forming a stepped etching. Based on such a first through hole 4, the loss of the light emitting area can be effectively reduced, and the light efficiency of the Mini-LED chip can be improved.

[0085] Preferably, in one embodiment, etching grooves 21 are provided on at least two edges of the preset area 17, and the N-type semiconductor layer 12, the active layer 13, and the P-type semiconductor layer 14 in the etching grooves 21 are all removed. The first through hole 4 is disposed away from the edge of the etching groove 21, and the edge of the first through hole 4 does not extend to any edge of the etching groove 21. Based on the above solution, the light efficiency of the Mini-LED chip can be further improved.

[0086] Specifically, the maximum cross-sectional area of the first through hole 4 ≤ 10% of the area of the preset area 17 to improve the light efficiency and ensure a good ohmic contact between the first contact layer 5 at the bottom of the first through hole 4 and the P-type semiconductor layer 14. Preferably, in one embodiment, the maximum cross-sectional area of the first through hole 4 ≤ 5% of the area of the preset area 17, which can not only further improve the light efficiency, but also make the subsequent P electrode 9 mainly located above the DBR layer 7, laying a good foundation for the N electrode 8 and the P electrode 9 to be at the same height, that is, the top surfaces of the N electrode 8 and the P electrode 9 are flush. It should be noted that in the present invention, the cross-sectional area of the first through hole 4 is reduced, and the light emitting area of the Mini-LED is increased, but the smaller cross-sectional area also means that the ohmic contact performance of the P electrode 9 becomes worse. For this reason, the present invention adopts a first through hole 4 with a ramp structure and forms a bowl-shaped first contact layer 5, effectively improving the ohmic contact performance.

[0087] S5: Form a first contact layer in the first through hole;

[0088] Among them, the first contact layer 5 can be formed by processes such as evaporation and sputtering, but is not limited thereto. Preferably, in one embodiment, the first contact layer 5 is formed by the processes of photolithography, evaporation, and lift-off stripping.

[0089] Among them, the first contact layer 5 covers the bottom and the side wall of the first through hole 4 with a preset length, that is, a bowl-shaped first contact layer 5 is formed, which can greatly increase the contact area between the first contact layer 5 and the P-type semiconductor layer 14 and ensure the ohmic contact between the two under the condition of reducing the area of the first through hole 4. And the first contact layer 5 only forms an ohmic contact with the P-type semiconductor layer 14 to prevent leakage. In addition, the thickness of the first contact layer 5 is less than the depth of the first through hole 4. If the thickness of the first contact layer 5 is too large, the probability of contacting the active layer 13 and the N-type semiconductor layer 12 increases, and the leakage probability increases.

[0090] Preferably, in one embodiment, the first contact layer 5 includes a first metal layer 51 and a first etch stop layer 52 that are sequentially stacked on the P-type semiconductor layer 14. The first etch stop layer 52 can protect the first metal layer 51 during the etching process of the DBR layer 7, preventing it from affecting the ohmic contact with the P-type semiconductor layer 14.

[0091] Specifically, the first metal layer 51 is one or more of an Au layer, an AuBe layer, or an AuZn layer, but is not limited thereto; the above-mentioned first metal layer 51 can form a good ohmic contact with the P-type semiconductor layer 14. Preferably, the first metal layer 51 is an Au layer or an AuBe layer. Specifically, the thickness of the first metal layer 51 is 0.5 μm to 1 μm, preferably 0.5 μm to 0.8 μm.

[0092] Specifically, the first etch stop layer 52 is one or more of a Ti layer, a Pt layer, a TiW layer, or a Ni layer, but is not limited thereto. Preferably, it is a Ti layer or a TiW layer. Specifically, the thickness of the first etch stop layer 52 is 0.5 μm to 3 μm, preferably 1 μm to 2 μm.

[0093] Preferably, in one embodiment, step S5 includes:

[0094] S51: Form a first contact layer in the first through hole;

[0095] S52: Anneal the epitaxial wafer obtained in step S51;

[0096] Through annealing, the first metal layer 51 can form an ohmic contact with the P-type semiconductor layer 14; wherein, the annealing temperature is 300 °C to 550 °C, preferably 450 °C to 500 °C.

[0097] S6: Form a second contact layer on the N-type semiconductor layer to obtain an intermediate;

[0098] Among them, the second contact layer 6 can be formed by processes such as evaporation and sputtering, but is not limited thereto. Preferably, in one embodiment, the second contact layer 6 is formed by photolithography, evaporation, and lift-off processes.

[0099] Specifically, the second contact layer 6 includes a second metal layer 61 and a second etch stop layer 62 that are sequentially stacked on the N-type semiconductor layer 12. Among them, the second metal layer 61 can form a good ohmic contact with the N-type semiconductor layer 12, and the second etch stop layer 62 can form a good blocking effect during the subsequent etching of the DBR layer 7, enabling the DBR layer 7 to be completely etched clean and preventing it from affecting the ohmic contact between the second metal layer 61 and the N-type semiconductor layer 12.

[0100] Specifically, the second metal layer 61 is one or more of an Au layer, a Ni layer, an AuGe layer, or an AuGeNi layer, but is not limited thereto; the above-mentioned second metal layer 61 can form a good ohmic contact with the N-type semiconductor layer 12. Preferably, the second metal layer 61 is an Au layer or an AuGeNi layer. Specifically, the thickness of the second metal layer 61 is 0.5 μm to 1 μm, preferably 0.5 μm to 0.8 μm.

[0101] Specifically, the second etch stop layer 62 is one or more of a Ti layer, a Pt layer, a TiW layer, or a Ni layer, but is not limited thereto. Preferably, it is a Ti layer or a TiW layer. Specifically, the thickness of the etch stop layer is 0.5 μm to 3 μm, preferably 1 μm to 2 μm.

[0102] Preferably, in one embodiment, step S6 includes:

[0103] S61: Form a second contact layer on the N-type semiconductor layer;

[0104] S62. Anneal the epitaxial wafer obtained in step S61;

[0105] By annealing, the second metal layer 61 can form an ohmic contact with the N-type semiconductor layer 12; wherein, the annealing temperature is 300 °C to 400 °C, preferably 300 °C to 340 °C.

[0106] More preferably, in one embodiment of the present invention, when the Mini-LED chip is a red light LED chip, step S6 includes:

[0107] S61: Form a second contact layer on the N-type GaAs ohmic contact layer;

[0108] Wherein, the width of the second contact layer 6 is smaller than the width of the N-type GaAs ohmic contact layer 121.

[0109] S62. Using the second contact layer as a mask, etch away the N-type GaAs ohmic contact layer around the second contact layer;

[0110] Specifically, etching away the N-type GaAs ohmic contact layer 121 can reduce its light absorption, so that more light is reflected by the DBR layer 7, improving the light emission efficiency.

[0111] S63. Etch to form an etch groove that etches to the second substrate;

[0112] Specifically, the etch groove 21 is provided at the edge of the preset area 17 for realizing electrical insulation of multiple preset areas 17.

[0113] S64. Anneal the epitaxial wafer obtained in step S63;

[0114] Specifically, through annealing, an ohmic contact can be formed between the second metal layer 61 and the N-type GaAs ohmic contact layer 121.

[0115] S7: Form a DBR layer on the intermediate body, and etch to form a second through-hole and a third through-hole in the regions where the first contact layer and the second contact layer are located;

[0116] Specifically, the DBR layer 7 can be formed by MOCVD or PECVD, but is not limited thereto. The DBR layer 7 covers the entire surface of the intermediate body, which can, on the one hand, achieve the reflection of light, and on the other hand, form a passivation protection.

[0117] Specifically, the DBR layer 7 can be etched by a dry etching process or a wet etching process to form a second through-hole 71 and a third through-hole 72. Since the first etching barrier layer 52 and the second etching barrier layer 62 are formed in the present invention, the underlying structure is not damaged during the etching process, so complete etching can be achieved.

[0118] S10: Form an N electrode and a P electrode to obtain an LED wafer;

[0119] Specifically, the N electrode 8 and the P electrode 9 can be formed by processes such as evaporation and sputtering, but are not limited thereto. Preferably, in one embodiment, the N electrode 8 and the P electrode 9 are formed by processes of photolithography, evaporation, and lift-off.

[0120] Among them, the specific compositions of the N electrode 8 and the P electrode 9 are the same or different. Preferably, they are the same, so that the N electrode 8 and the P electrode 9 can be formed by one evaporation process to improve efficiency.

[0121] Specifically, both the N electrode 8 and the P electrode 9 are laminated structures formed by at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer, but are not limited thereto. Preferably, in one embodiment, the N electrode 8 and the P electrode 9 include a first Ti layer, a first Al layer, a second Ti layer, a second Al layer, a third Ti layer, a third Al layer, a Ni layer, a Pt layer, and an Au layer laminated in sequence. This electrode structure has good self-supporting performance and can still avoid depression in the presence of the first through-hole 4, effectively ensuring that the N electrode 8 and the P electrode 9 are of the same height, that is, their upper surfaces are flush. It should be noted that refer to Figure 1, in conventional LED chips, there is often a height difference between the P-type electrode and the N-type electrode, which causes it to be prone to tilting during die bonding, resulting in poor soldering, reducing the shear force that the chip can withstand, and thus when there is mechanical vibration or the encapsulation colloid expands and contracts due to heat, there is a risk of the LED chip falling off or the circuit being open and the lamp dying. Currently, a common solution is to set part of the P-type electrode on the light-emitting area, but this reduces the effective area of the light-emitting area, which has a particularly significant impact on small-sized Mini-LED chips. And the present invention effectively ensures that the N electrode 8 and the P electrode 9 are at the same height and improves the die bonding yield and finished product reliability by jointly controlling the arrangement position, size of the first through hole 4, and the composition of the P electrode 9 and the N electrode 8.

[0122] Specifically, the N electrode 8 is electrically connected to the second contact layer 6 through the third through hole 72, and the P electrode 9 is electrically connected to the first contact layer 5 through the second through hole 71.

[0123] S11: Cut the LED wafer to obtain Mini-LED chips;

[0124] Specifically, first grind and thin the second substrate, and then Mini-LED chips can be obtained through laser cutting and scribing.

[0125] Correspondingly, the present invention also discloses a Mini-LED chip, see Figure 4 and Figure 5 , which includes a second substrate 3, a bonding layer 2, a P-type semiconductor layer 14, an active layer 13, an N-type semiconductor layer 12, a second contact layer 6, a DBR layer 7, and an N electrode 8 that are sequentially stacked on the back surface of the second substrate 3; the N electrode 8 is electrically connected to the second contact layer 6 through a third through hole 72 provided on the DBR layer 7.

[0126] The Mini-LED chip further includes a first through hole 4 etched to the P-type semiconductor layer 14, a first contact layer 5 provided in the first through hole 4, and a P electrode 9; the first through hole 4 is provided at the edge away from the N-type semiconductor layer 12, and the edge of the first through hole 4 does not extend to any edge of the N-type semiconductor layer 12; the depth of the first through hole 4 is greater than the total thickness of the N-type semiconductor layer 12 and the active layer 13; the side wall of the first through hole 4 is inclined, and the inclination angle ≤ 70°; the first contact layer 5 covers the bottom and a preset length of the side wall of the first through hole 4, and the first contact layer 5 only forms an ohmic contact with the P-type semiconductor layer 14; the thickness of the first contact layer 5 is less than the depth of the first through hole 4; the DBR layer 7 covers the side wall and the bottom of the first through hole 4, the P electrode 9 is provided on the DBR layer 7, and is electrically connected to the first contact layer 5 through a second through hole 71 provided on the DBR layer 7. Based on the above Mini-LED chip, the proportion of the light-emitting area 10 can be greatly increased, and the light efficiency of the Mini-LED chip can be improved.

[0127] The above are the preferred embodiments of the invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A method for preparing a Mini-LED chip, characterized in that, Including the following steps: S1. Provide an epitaxial wafer, which includes a first substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer that are sequentially stacked on the first substrate; the epitaxial wafer includes a plurality of preset regions, and each preset region forms a Mini-LED chip; S2. Form a bonding layer on the P-type semiconductor layer; S3. Bond the epitaxial wafer obtained in step S2 to a second substrate, and remove the first substrate; S4. Form a first through hole; The first through hole is arranged away from the edge of the preset region, and the edge of the first through hole does not extend to any edge of the preset region; the cross-sectional area of the first through hole is less than 5% of the surface area of the preset region, the first through hole is etched to the P-type semiconductor layer, and the depth of the first through hole is greater than the total thickness of the N-type semiconductor layer and the active layer; the side wall of the first through hole is inclined, and the inclination angle ≤ 70°; S5. Form a first contact layer in the first through hole; the first contact layer covers the bottom and a preset length of the side wall of the first through hole, and the first contact layer only forms an ohmic contact with the P-type semiconductor layer; the thickness of the first contact layer is less than the depth of the first through hole; S6. Form a second contact layer on the N-type semiconductor layer to obtain an intermediate body; S7. Form a DBR layer on the intermediate body, and etch to form a second through hole and a third through hole in the regions where the first contact layer and the second contact layer are located; S8. Form an N electrode and a P electrode to obtain an LED wafer; wherein, the N electrode is electrically connected to the second contact layer through the third through hole, and the P electrode is electrically connected to the first contact layer through the second through hole; the top surfaces of the N electrode and the P electrode are flush; S9. Cut the LED wafer to obtain Mini-LED chips; The first contact layer includes a first metal layer and a first etching barrier layer that are sequentially stacked on the P-type semiconductor layer; the first etching barrier layer is used to protect the first metal layer when etching the DBR layer; The second contact layer includes a second metal layer and a second etching barrier layer that are sequentially stacked on the N-type semiconductor layer, and the second etching barrier layer is used to protect the second metal layer when etching the DBR layer.

2. The manufacturing method of the Mini-LED chip according to claim 1, wherein The first metal layer is one or more of an Au layer, an AuBe layer, or an AuZn layer, and its thickness is 0.5 μm to 1 μm; and / or The first etching barrier layer is one or more of a Ti layer, a Pt layer, a TiW layer, or a Ni layer, and its thickness is 0.5 μm to 3 μm; The second metal layer is one or more of an Au layer, a Ni layer, an AuGe layer, or an AuGeNi layer, and its thickness is 0.5 μm to 1 μm; and / or The second etching barrier layer is one or more of a Ti layer, a Pt layer, a TiW layer, or a Ni layer, and its thickness is 0.5 μm to 3 μm; and / or The bonding layer is an Al2O3 layer and / or an SiO2 layer, and its thickness is 500 nm to 3000 nm.

3. The method for preparing a Mini-LED chip according to claim 1 or 2, characterized in that, The first metal layer is an Au layer or an AuBe layer, and its thickness is 0.5 μm to 0.8 μm; and / or The first etching barrier layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; and / or The second metal layer is an Au layer or an AuGeNi layer, and its thickness is 0.5 μm to 0.8 μm; and / or The second etching barrier layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; and / or The bonding layer is a SiO2 layer, and its thickness is 500 nm to 1000 nm.

4. The manufacturing method of the Mini-LED chip according to claim 1, wherein, Step S5 includes: S51. Form a first contact layer in the first through hole; S52. Anneal the epitaxial wafer obtained in step S51 to form an ohmic contact between the first metal layer and the P-type semiconductor layer; wherein, the annealing temperature is 300 °C to 550 °C; Step S6 includes: S61: Form a second contact layer on the N-type semiconductor layer; S62. Anneal the epitaxial wafer obtained in step S61 to form an ohmic contact between the second metal layer and the N-type semiconductor layer, obtaining an intermediate; wherein, the annealing temperature is 300 °C to 400 °C.

5. The manufacturing method of the Mini-LED chip according to claim 1, characterized in that, The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP current spreading layer, and an N-type AlGaInP confinement layer that are sequentially stacked on the first substrate; and / or The P-type semiconductor layer includes a P-type AlGaInP confinement layer and a P-type GaP window layer that are sequentially stacked on the active layer; and / or A GaAs buffer layer and a GaInP etch stop layer are further sequentially provided between the first substrate and the N-type semiconductor layer; and / or The first substrate is a GaAs substrate; and / or The second substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate; and / or The N electrode and the P electrode have the same or different compositions, and both are laminated structures formed by at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer.

6. The manufacturing method of the Mini-LED chip according to claim 5, wherein, Step S2 includes: S21. Roughen the P-type GaP window layer; S22. Form a bonding layer on the roughened P-type GaP window layer; and / or Step S3 includes: S31. Bond the epitaxial wafer obtained in step S2 to the second substrate; S32. Remove the first substrate, the GaAs buffer layer, and the GaInP etch stop layer.

7. The manufacturing method of the Mini-LED chip according to claim 5, characterized in that, Step S6 includes: S61: Form a second contact layer on the N-type GaAs ohmic contact layer; the width of the second contact layer is smaller than the width of the N-type GaAs ohmic contact layer; S62. Using the second contact layer as a mask, etch and remove the N-type GaAs ohmic contact layer around the second contact layer; S63. Etch to form an etch groove; the etch groove is close to the edge of the preset area, the first through hole is arranged away from the etch groove, and the edge of the first through hole does not extend to any edge of the etch groove; S64. Anneal the epitaxial wafer obtained in step S63 to form an ohmic contact between the second metal layer and the N-type GaAs ohmic contact layer, obtaining an intermediate; wherein, the annealing temperature is 300 °C to 400 °C.

8. A Mini-LED chip, characterized in that, Prepared by the preparation method of the Mini-LED chip according to any one of claims 1 to 7.

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