Voltage regulation circuit, electronic device and voltage regulation method

Abstract

The present application discloses a voltage regulation circuit, an electronic device, and a voltage regulation method. When the post-stage load of the VRM is working, a logic high level is input to the SYNC pin of the SPS / DrMOS to enable the normal operation of the SPS / DrMOS; when the post-stage load of the VRM is not working, the SYNC pin of the SPS / DrMOS is set to an intermediate state to enable the SPS / DrMOS to enter the standby mode, thereby reducing the static current on the VCC pin and reducing the additional power consumption on the VCC pin of the SPS / DrMOS.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular, to a voltage regulation circuit, an electronic device, and a voltage regulation method. Background Art

[0002] The load demand voltages, draw currents, etc. of some modules in an electronic device, such as a central processor unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), etc., are dynamically changing. For example, when opening a document and opening a game, the load voltage and current of the CPU vary greatly. Therefore, the core voltages Vcore required by the above-mentioned various modules are different, and may instantaneously increase or decrease, and the device power supply that outputs a fixed voltage cannot meet the voltage requirements of the above-mentioned modules. For this reason, a voltage regulator module (VRM) is provided in the electronic device to convert a relatively large DC voltage (such as 12V) output by the power supply into a stable relatively small DC voltage (such as 0.5V - 2V), and can adjust the magnitude of the output voltage in real time according to the load demand to meet the working voltage requirements of the above-mentioned modules. Summary of the Invention

[0003] The present application provides a voltage regulation circuit, an electronic device, and a voltage regulation method, which can reduce the additional power consumption of the electronic device.

[0004] In a first aspect, a voltage regulation circuit is provided, including: a pulse width modulation (PWM) controller, and N first circuits, where N is a positive integer. The first circuit includes: a unidirectional conduction device and a second circuit. The PWM controller is configured to output a PWM voltage signal to the second circuit, and the second circuit is configured to reduce the voltage received at the high-voltage input terminal of the voltage regulation circuit according to the PWM voltage signal and then output it. The PWM controller includes an EN pin, and the EN pin of the PWM controller is connected to the input terminal of the enable signal of the PWM controller. The second circuit includes a DrMOS, and the DrMOS includes a SYNC pin and a VCC pin. The VCC pin is connected to the input terminal of the drive voltage of the DrMOS, and the SYNC pin is not connected to the input terminal of the drive voltage of the DrMOS. The first end of the pull-up resistor module is connected to the VCC pin, and the second end is connected to the SYNC pin. The first end of the pull-down resistor module is connected to the SYNC pin, and the second end is grounded. The pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor. The first ends of the first resistor and the third resistor are both connected to the VCC pin, and the second ends are both connected to the SYNC pin. The first ends of the second resistor and the fourth resistor are both connected to the SYNC pin, and the second ends are both grounded. The first resistor and the second resistor belong to the voltage regulation circuit and are located outside the PWM controller and the second circuit. The third resistor and the fourth resistor belong to the DrMOS. The first end of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second end is connected to the SYNC pin.

[0005] Implementing the voltage regulation circuit of the first aspect, the SYNC pin is not connected to the input terminal of the drive voltage of the DrMOS, but is connected to VCC through the pull-up resistor module and grounded through the pull-down resistor module. This can regulate the voltage on the SYNC pin during the working process and the non-working process of the voltage regulation circuit, and prevent the SYNC pin from continuously receiving the drive voltage.

[0006] Combined with the first aspect, in some embodiments, the static current on the VCC pin when the SYNC pin is at the intermediate state level is less than the static current on the VCC pin when the SYNC pin is at the logic high level. When the EN pin of the PWM controller receives a logic high level, the unidirectional conduction device conducts from the first end to the second end, and the SYNC pin receives a high level. When the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device cuts off from the first end to the second end, and the SYNC pin receives an intermediate state level.

[0007] Through the previous embodiment, when the PWM controller is working, a logic high level is input to the SYNC pin to enable the DrMOS to work properly. When the PWM controller is not working, the SYNC pin is set to the intermediate state, thereby reducing the static current on the VCC pin, that is, reducing the additional power consumption on the VCC pin.

[0008] In combination with the first aspect, in some embodiments, the voltage regulation circuit further includes: a first capacitor, where a first end of the first capacitor is connected to the SYNC pin, and a second end of the first capacitor is grounded. The first capacitor can be used to adjust the timing of the SYNC pin entering the intermediate state level from the logic high level, making the SYNC pin discharge slower than the EN pin, thereby avoiding an undervoltage fault in the PWM controller.

[0009] In combination with the first aspect, in some embodiments, the first capacitor is located outside the PWM controller and the second circuit.

[0010] In combination with the first aspect, in some embodiments, when the voltage difference from the first end to the second end of the unidirectional conduction device is greater than the conduction voltage drop of the unidirectional conduction device, the unidirectional conduction device conducts from the first end to the second end; otherwise, the unidirectional conduction device is cut off.

[0011] In combination with the first aspect, in some embodiments, the unidirectional conduction device is a diode, where the anode of the diode is connected to the EN pin of the PWM controller, and the cathode of the diode is connected to the SYNC pin.

[0012] In combination with the first aspect, in some embodiments, the DrMOS includes: a driver, a first switching transistor, and a second switching transistor. Among them, for the first switching transistor, the drain is connected to the high-voltage input terminal of the voltage regulation circuit, the gate is connected to the first output terminal of the driver, and the source is connected to the output terminal of the DrMOS; for the second switching transistor, the drain is connected to the output terminal of the DrMOS, the gate is connected to the second output terminal of the driver, and the source is grounded; the input terminal of the driver is connected to the output terminal of the PWM controller.

[0013] In combination with the previous embodiment, the first switching transistor can be an N-type field-effect transistor, and the second switching transistor can be an N-type field-effect transistor.

[0014] In combination with the previous embodiment, when the PWM voltage signal is in the positive half-cycle, the first output terminal of the driver outputs a first driving signal, the first switching transistor conducts, and the second switching transistor is cut off; when the PWM voltage signal is in the negative half-cycle, the second output terminal of the driver outputs a second driving signal, the first switching transistor is cut off, and the second switching transistor conducts.

[0015] In combination with the previous embodiment, the second circuit further includes: a first inductor, a second capacitor. A first end of the first inductor is connected to the output terminal of the DrMOS, a second end of the first inductor and a first end of the second capacitor are both connected to the high-voltage output terminal of the voltage regulation circuit, and a second end of the second capacitor is grounded.

[0016] In combination with the first aspect, in some embodiments, the high-voltage input terminal of the voltage regulation circuit is connected to the high-voltage output terminal of the power supply.

[0017] In combination with the first aspect, in some embodiments, the high-voltage output terminal of the voltage regulation circuit is connected to the high-voltage input terminal of the load.

[0018] In combination with the previous embodiment, the current output by the high-voltage output terminal of the voltage regulation circuit to the load is the sum of the output currents of the first circuits started in N first circuits.

[0019] In combination with the first aspect, in some embodiments, the voltage regulation circuit is connected to the load, and the load includes any one of the following: CPU, GPU, ASIC.

[0020] In combination with the first aspect, in some embodiments, the input terminal of the enable signal of the PWM controller is a GPIO interface. This GPIO interface can be used to receive control signals from a control unit (such as a CPU, EC, etc.).

[0021] In combination with the first aspect, in some embodiments, the PWM controller is integrated in the first chip, and the DrMOS is integrated in the second chip, and the first chip and the second chip are different.

[0022] In the second aspect, an electronic device is provided, and the electronic device includes a voltage regulation circuit provided in the first aspect or any one of the embodiments of the first aspect.

[0023] In combination with the second aspect, in some embodiments, the electronic device further includes a power supply, and the power supply is used to input a voltage to the voltage regulation circuit.

[0024] In combination with the second aspect, in some embodiments, the electronic device further includes a load, and the voltage output by the voltage regulation circuit is used to supply the load.

[0025] In the third aspect, a voltage regulation method is provided, which is applied to the electronic device provided in the second aspect or any one of the embodiments of the second aspect. The method may include: the electronic device detects an operation of starting the load; inputs a logic high level to the EN pin of the PWM controller; detects an operation of shutting down the load; inputs a logic low level to the EN pin of the PWM controller.

[0026] Through the method of the third invention, the electronic device can use the voltage regulation circuit to reduce a larger voltage and then output it to meet the actual requirements of the subsequent load, and can also reduce the extra power consumption on the VCC pin of the DrMOS when the subsequent load is not working.

[0027] In combination with the third aspect, in some embodiments, the electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller through the GPIO interface.

[0028] In combination with the third aspect, in some embodiments, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage requirement of the load, and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage requirement of the load. For example, if the voltage requirement of the load increases, the duty cycle is increased; otherwise, the duty cycle is decreased.

[0029] In combination with the third aspect, in some embodiments, the electronic device can also obtain the current requirement of the load, and adjust the number of the first circuits started in the N first circuits of the voltage regulation circuit according to the current requirement of the load. For example, if the current requirement of the load increases, the number of the started first circuits is increased; otherwise, the number of the started first circuits is decreased.

[0030] In a fourth aspect, a PCB board is provided, including the voltage regulation circuit in the first aspect or any one of the embodiments of the first aspect.

[0031] In a fifth aspect, a chip is provided, and the chip includes the voltage regulation circuit in the first aspect or any one of the embodiments of the first aspect.

[0032] In a sixth aspect, a power supply system is provided, and the power supply system may include: a power supply, the voltage regulation circuit in the first aspect or any one of the embodiments of the first aspect, and a load. The power supply is used to provide an input voltage for the voltage regulation circuit, and the voltage regulation circuit is used to reduce the input voltage provided by the power supply and then output it to the load.

[0033] In a seventh aspect, a power supply circuit is provided, and the power supply circuit may include: a power supply, the voltage regulation circuit in the first aspect or any one of the embodiments of the first aspect. The power supply is used to provide an input voltage for the voltage regulation circuit, and the voltage regulation circuit is used to reduce the input voltage provided by the power supply and then output it.

[0034] In an eighth aspect, a power supply system is provided, and the power supply system may include: the voltage regulation circuit in the first aspect or any one of the embodiments of the first aspect, and a load. The voltage regulation circuit is used to reduce the received input voltage and then output it to the load.

[0035] In a ninth aspect, a readable storage medium is provided, including instructions, which when running on a device, cause the device to execute the method in the third aspect or any one of the embodiments of the third aspect.

[0036] In a tenth aspect, a program product is provided, which when running on a device, causes the device to execute the method in the third aspect or any one of the embodiments of the third aspect.

[0037] In an eleventh aspect, a chip system is provided, which includes at least one processor for implementing the method according to the third aspect or any one of the implementation manners of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 FIG. is a structural diagram of a single-phase VRM provided by an embodiment of the present application;

[0039] Figure 2 FIG. is a structural diagram of a multi-phase VRM provided by an embodiment of the present application;

[0040] Figure 3 FIG. is a schematic diagram of partial pins of MP2886, partial pins of MP86941, and a partial peripheral structure provided by an embodiment of the present application;

[0041] Figure 4 FIG. is a partial structural diagram of an improved VRM provided by an embodiment of the present application;

[0042] Figure 5 FIG. is an internal structural diagram of an SPS / DrMOS provided by an embodiment of the present application;

[0043] Figure 6 FIG. is a partial structural diagram of an improved VRM provided by an embodiment of the present application;

[0044] Figure 7 FIG. is a partial structural diagram of an improved VRM provided by an embodiment of the present application;

[0045] Figure 8 FIG. is a partial structural diagram of an improved VRM provided by an embodiment of the present application;

[0046] Figure 9 FIG. is a partial structural diagram of an improved VRM provided by an embodiment of the present application;

[0047] Figure 10 FIG. is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and thoroughly described with reference to the accompanying drawings.

[0049] First, several concepts related to the present application are introduced.

[0050] VRM

[0051] VRM is used to convert a relatively large DC voltage (such as 12V) output by a power supply in an electronic device into a stable relatively small DC voltage (such as 0.5V - 2V) and output it to modules such as a CPU, a GPU, and an ASIC to meet the working voltage requirements of the above modules.

[0052] Figure 1 It is a schematic diagram of a single-phase voltage regulation module (single-phase VRM) 10. This single-phase VRM 10 can also be referred to as a single-phase DC-DC Buck type step-down circuit.

[0053] The single-phase VRM 10 may include: a pulse-width modulation (pulse-width modulation controller, PWM) controller 101, a driver 102, a high-side power stage field-effect transistor (high side field-effect transistor, HS-FET) M1, a low-side power stage field-effect transistor (LS-FET) M2, an inductor L, and a capacitor C. The single-phase VRM 10 also includes: a first input terminal and a second input terminal, a first output terminal and a second output terminal.

[0054] The first input terminal is also referred to as the high-voltage input terminal, which is connected to the high-voltage output terminal of the device power supply for receiving the input voltage Vin; the second input terminal is also referred to as the low-voltage input terminal, which is connected to the low-voltage output terminal of the device power supply. The first output terminal is also referred to as the high-voltage output terminal, which is connected to an input terminal of the subsequent load for outputting the core voltage Vcore required by the subsequent load; the second output terminal is also referred to as the low-voltage output terminal, which is connected to another input terminal of the subsequent load. The second input terminal and the second output terminal can both be connected to the ground terminal (GND). The input voltage Vin can be the output voltage of the device power supply, and the device power supply can be a battery. The subsequent load refers to modules such as a CPU, GPU, ASIC, etc. that have special working voltage requirements.

[0055] The PWM controller 101 is connected to the driver 102 for outputting a PWM voltage signal to the driver 102. This PWM voltage signal can be generated by a comparator CP in the PWM controller 101, which compares a fixed reference voltage Vref with the core voltage Vcore output by the single-phase VRM 10. The PWM controller 101 is used to control the duty cycle of the PWM waveform according to the real-time demand of the load, so that the output voltage is stabilized at the required value of the core voltage Vcore. The PWM voltage signal output by the PWM controller 101 is an analog signal with alternating high and low levels in sequence. When the PWM voltage signal is at a high level, the PWM voltage signal is in the positive half-cycle; when the PWM voltage signal is at a low level, the PWM voltage signal is in the negative half-cycle.

[0056] The driver 102 may include a control logic circuit 1011 and two driver circuits 1012, 1013.

[0057] Either M1 or M2 can be an N-type field effect transistor or a P-type field effect transistor.

[0058] The drain (D) of M1 is connected to the first input terminal, the gate (G) of M1 is connected to the output terminal of the driving circuit 1012, and the source (S) of M1 is connected to the first end of L. The drain (D) of M2 is connected to the first end of L, the gate (G) of M2 receives the output terminal of the driving circuit 1013, and the source (S) of M2 is connected to the second input terminal. The second end of L is connected to the first output terminal for outputting the required core voltage Vcore to the subsequent load. The first end of C is connected to the second end of L, and the second end of C is connected to the second output terminal.

[0059] When the PWM voltage signal output by the PWM controller 101 is in the positive half cycle, the control logic circuit 1011 in the driver 102 generates a signal for the driving circuit 1012 to output a first driving signal S1 to M1. M1 conducts, M2 disconnects / cuts off, the current flows from VCC through M1 and L to charge C, and L generates a self-induced electromotive force. When the PWM voltage signal output by the PWM controller 101 is in the negative half cycle, the control logic circuit 1011 in the driver 102 generates a signal for the driving circuit 1013 to output a second driving signal S2 to M2. M1 disconnects / cuts off, M2 conducts, the current in L will try to maintain its existing magnetic field, which will cause the voltage to reverse and accumulate in C. When the electromotive force on L decreases or becomes small, C outputs the supply voltage to the subsequent load. Thus, under the action of the PWM voltage signal, the driver 102 controls the frequent switching of M1 and M2 to provide a continuous and stable current and voltage to the subsequent load.

[0060] Integrating M1, M2, and the driver 102 into one chip, the device of this integration scheme is called a smart power stage (SPS), and can also be called DrMOS, which can reduce the overall size, improve the power density and efficiency. The SPS / DrMOS can also integrate an overcurrent protection circuit for controlling the output current to avoid the output current exceeding the rated value; it can also integrate an error detection circuit for detecting faults such as overheating, overvoltage, and open circuit.

[0061] The output terminal of the DrMOS is connected to the source (S) of M1, and the drain (D) of M2 is also connected to the first end of L.

[0062] One phase of the VRM refers to a circuit composed of a driver 102, M1, M2, an inductor L, and a capacitor C. To meet the requirements of different loads and improve the output power, a multi-phase voltage regulation module (multi-phase VRM) is introduced.

[0063] Figure 2 It is a schematic diagram of a multiphase VRM 20. This multiphase VRM 20 can also be called a multiphase DC-DC Buck type step-down circuit.

[0064] The multiphase VRM 20 may include: a PWM controller 201, and multiple interleaved single-phase circuits. Each single-phase circuit has the same structure as the Figure 1 single-phase circuit shown. The first output terminals of each single-phase circuit are all connected to an input terminal of the subsequent load, and are used to output the core voltage Vcore required by the subsequent load. The PWM controller 201 is used to respectively provide a PWM voltage signal to some or all of the multiple single-phase circuits. The current output by the multiphase VRM 20 to the subsequent load is the sum of the output currents of several started single-phase circuits among the multiple circuits.

[0065] The multiphase VRM 20 needs to use multiple SPS / DrMOS.

[0066] Extra power consumption generated by the VRM

[0067] Some VRMs in some possible implementation manners may have extra power consumption. For example, specifically as follows:

[0068] Some PWM controllers and SPS / DrMOS with specific structures will cause extra power consumption. Generally, the PWM controller can be integrated in a power management IC chip and can be called a PWM control chip; the SPS / DrMOS can be integrated in another power management IC chip and can be called an SPS / DrMOS chip. The structures of the PWM control chip and the SPS / DrMOS chip that cause extra power consumption are introduced below.

[0069] The PWM control chip includes the structure of the PWM controller 201 described above Figure 2 and also includes an enable pin EN. The EN pin can be connected to a signal interface (such as a general purpose input output (GPIO) interface) to receive the enable signal sent by it, also called a control signal. This control signal can come from a control unit (such as a CPU, an embedded controller (EC), etc.) in an electronic device. When the EN pin receives a logic high level, the PWM control chip works to implement the functions of the PWM controller mentioned above; when the EN pin receives a logic low level, the PWM control chip does not work.

[0070] When the subsequent load of the VRM (such as the GPU) is working, the EN pin in the PWM control chip is at a logic high level, so that the PWM control chip can implement the functions of the PWM controller mentioned above; when the subsequent load of the VRM (such as the GPU) is not working, the EN pin in the PWM control chip is at a logic low level, and the PWM control chip does not operate.

[0071] Referring to Table 1, Table 1 shows the logic level conditions of the EN pin of the PWM control chip.

[0072]

[0073]

[0074] Table 1

[0075] As shown in Table 1, the logic high level requirement of the EN pin of the PWM control chip is greater than 0.8V, for example, it can be 3.3V or other values.

[0076] The SPS / DrMOS chip includes one of the above Figure 1 SPS / DrMOS or Figure 2 multiple SPS / DrMOS among them.

[0077] Refer to Figure 3 , Figure 3 Exemplarily shows some pins of the PWM control chip, some pins of the SPS / DrMOS chip and some peripheral structures. As Figure 3 shown, the PWM control chip may include a PWM pin, an EN pin, etc., and the SPS / DrMOS chip includes an EN pin, a VCC pin, a SYNC pin, a PWM pin, a VIN pin and some other pins (such as a SW pin for outputting a switching signal, a GND pin, etc.). The EN pin of the PWM control chip can be connected to the GPIO to receive an enable signal. The PWM pin of the PWM control chip is directly connected to the PWM pin of the SPS / DrMOS chip, and the PWM pin of the PWM control chip is used to output a PWM voltage signal to the PWM pin of the SPS / DrMOS chip. The switching SW pin of the SPS / DrMOS chip is connected to the first end of the inductor L in the VRM, and this L can be Figure 1 or Figure 2 the inductor L among them.

[0078] In the SPS / DrMOS chip, the VCC pin is used to receive the power supply voltage for driving the SPS / DrMOS chip. The VCC pin is usually directly connected to the common VCC network in the electronic device to receive the driving voltage output by the common VCC network. This driving voltage can be 3.3V for example. Usually, as Figure 3As shown, on the periphery of the SPS / DrMOS chip, the SYNC pin is also directly connected to the common VCC network, used to receive the power supply voltage (such as 3.3V) for driving this SPS / DrMOS chip. The PWM pin is used to receive the PWM voltage signal output by the previous-stage PWM controller. The VIN pin is connected to the high-voltage output terminal of the device power supply, used to receive the DC voltage output by the device power supply.

[0079] Among them, the SYNC pin is a mode switching control pin of the chip. When this pin is at a high level, the SPS / DrMOS chip enters the normal working mode (active mode); when this pin is at an intermediate state level or floating, the SPS / DrMOS chip enters the standby mode (standby mode); when this pin is at a low level, the SPS / DrMOS chip enters the diode simulation mode. The diode simulation mode means that when the current of the inductor L flows from the second end to the first end, M2 conducts, and when the current of the inductor L flows from the first end to the second end, then M2 turns off to prevent current backflow.

[0080] When the SYNC pin is floating or at an intermediate state level, the SPS / DrMOS chip enters the standby mode and stops working. Even if the SPS / DrMOS chip receives the PWM voltage signal, it will not output voltage, that is, it enters the standby mode. When the SPS / DrMOS chip enters the normal working mode, as long as the SPS / DrMOS chip receives the PMW signal input by the PWM controller, the SPS / DrMOS chip will start working.

[0081] The SYNC pin can receive high level, low level and intermediate state level. Refer to Table 2, and Table 2 shows the three-state voltage range of the SYNC pin in the SPS / DrMOS chip.

[0082]

[0083] Table 2

[0084] As shown in Table 2, the intermediate state level of the SYNC pin is between the logic high level and the logic low level. When the SYNC pin is in the intermediate state, the SPS / DrMOS chip is disconnected from other connected devices, that is, it enters the standby mode.

[0085] Refer to Table 3, and Table 3 shows the corresponding relationship between the SPS / DrMOS mode, the SYNC pin state, and the static current on the VCC pin. The static current on the VCC pin refers to the current when there is no signal input to the SPS / DrMOS, that is, the current consumed by the device without being affected by external factors.

[0086]

[0087] Table 3

[0088] As shown in Table 3, when the SYNC pin is at a logic high level, there is a static current of about 4 mA on the VCC pin, and there is a power consumption of 3.3 V * 4 mA = 13.2 mW on the VCC pin. When the SYNC pin is at an intermediate level, there is a static current of about 30 μA on the VCC pin, and there is only a power consumption of 3.3 V * 30 μA = 99 μW on the VCC pin, which is much lower than the power consumption when the SYNC pin is at a logic high level.

[0089] When the subsequent load (such as GPU) of the VRM is working, the SYNC pin in the SPS / DrMOS chip is at a logic high level, and the scheme of directly connecting the SYNC pin and the VCC pin can meet this requirement. When the SYNC pin is at a logic high level, the SPS / DrMOS chip realizes the functions of the SPS / DrMOS mentioned above.

[0090] However, when the subsequent load (such as GPU) of the VRM is not working, the scheme of directly connecting the SYNC pin and the VCC pin brings an additional power consumption of 3.3 V * 4 mA = 13.2 mW on the VCC pin. If the VRM set in the electronic device is a single-phase VRM, there is an additional power consumption of about 13.2 mW; if the VRM set in the electronic device is a multi-phase VRM, there is an additional power consumption of about 13.2 mW * number of phases. If multiple VRMs are set in the electronic device, the above additional power consumption will further increase.

[0091] The above additional power consumption not only exists in the VRM with an SPS / DrMOS chip as an SPS / DrMOS, but also generally exists in VRMs with the following characteristics: the SPS / DrMOS includes a SYNC pin and a VCC pin, there is a large static current on the VCC pin when the SYNC pin is at a logic high level, and the SYNC pin continuously receives a logic high level.

[0092] To solve the above problems, the present application provides a power consumption optimization scheme, which improves the peripheral connection relationship of the SYNC pin in the VRM's SPS / DrMOS to achieve the following purposes: when the subsequent load of the VRM is working, input a logic high level to the SYNC pin to enable the normal operation of the SPS / DrMOS; when the subsequent load of the VRM is not working, set the SYNC pin to an intermediate state to enable the SPS / DrMOS to enter the standby mode, thereby reducing the static current on the VCC pin and reducing the additional power consumption on the VCC pin.

[0093] The optimization scheme provided by the present application can be used to improve the peripheral connection relationship of the SYNC pin in a single-phase VRM, or can also be used to improve the peripheral connection relationships of multiple SYNC pins in a multi-phase VRM.

[0094] The solution provided by this application can be applied to a VRM that has the above problems and has a smaller static current on the VCC pin when the SYNC pin of the SPS / DrMOS is in an intermediate state compared to a logic high level. For example, it can be applied to a VRM that uses a PWM control chip as the PWM controller and an SPS / DrMOS chip as an SPS / DrMOS. Taking this as an example, when the subsequent load of the VRM does not work, there is only a power consumption of 3.3V * 30μA = 99μW on the VCC pin of an SPS / DrMOS, compared to the power consumption of 3.3V * 4mA = 13.2mW on the VCC pin of an SPS / DrMOS in the above problem, which greatly reduces the additional power consumption of an SPS / DrMOS. When a multi-phase VRM or multiple VRMs are set in an electronic device, the overall additional power consumption will be further reduced.

[0095] Improved VRM

[0096] The improvements of the VRM provided by this application mainly involve the following three pins: the EN pin of the PWM controller, the SYNC pin of the SPS / DrMOS, and the VCC pin. For the sake of simplicity of expression, the EN pin mentioned later refers to the EN pin of the PWM controller, the SYNC pin mentioned later refers to the SYNC pin of the SPS / DrMOS, and the VCC pin mentioned later refers to the VCC pin of the SPS / DrMOS.

[0097] (1) The first improved VRM

[0098] Reference Figure 4 , Figure 4 shows the peripheral connection method of the SYNC pin in an improved VRM provided by an embodiment of this application.

[0099] As Figure 4 shown, two resistors R1, R2 and a unidirectional conduction device D1 are added to the peripherals of the PWM controller and the SPS / DrMOS. That is, the resistors R1, R2, D1 belong to the peripheral circuit of the PWM controller and the SPS / DrMOS, and this peripheral circuit and the PWM controller, SPS / DrMOS are not integrated on the same chip. Among them, the first end of R1 is connected to the VCC pin, and the second end of R1 is connected to the SYNC pin. The first end of R2 is connected to the SYNC pin, and the second end of R2 is grounded. The first end of D1 is connected to the EN pin of the PWM controller, and the second end of D1 is connected to the SYNC pin. When the voltage at the first end of D1 is greater than the voltage at the second end and the difference reaches the conduction voltage drop of D1, D1 conducts unidirectionally from the first end to the second end. D1 can be a unidirectional conduction device or a unidirectional conduction circuit that forms a smaller conduction voltage drop (less than 1V), for example, it can be a diode.

[0100] Thus, at the periphery of the SPS / DrMOS, the SYNC pin is no longer directly connected to the VCC pin.

[0101] When the subsequent load of the VRM is working, the voltage on the SYNC pin is at a logic high level. The specific logic implementation is as follows: when the subsequent load of the VRM is working, the EN pin of the PWM controller is at a logic high level; R1 and R2 divide the voltage between the VCC pin and the ground terminal, and the voltage on the SYNC pin is the voltage divided by R2; the voltage difference between the first end and the second end of D1 (i.e., the voltage difference between the EN pin and the SYNC pin) is greater than the forward voltage drop of D1, so D1 conducts from the first end to the second end; after that, the voltage on the SYNC pin is equal to the voltage of the EN pin minus the voltage divided by D1, and the voltage on the SYNC pin is at a logic high level.

[0102] Exemplarily, assuming that the power supply voltage received by the VCC pin is 3.3V and the resistances of R1 and R2 are the same, the voltage divided by R2 on the SYNC pin is 1.65V; assuming that when the subsequent load of the VRM is working, the logic high level of the EN pin is 3.3V and the forward voltage drop of D1 is 0.3V, then D1 will conduct, and the voltage on the SYNC pin after D1 conducts is 3V; if the tri-state voltage of the SYNC pin is as shown in Table 2, then the voltage on the SYNC pin is at a logic high level at this time.

[0103] When the subsequent load of the VRM is not working, the voltage on the SYNC pin is at an intermediate state level. The specific logic implementation is as follows: R1 and R2 divide the voltage between the VCC pin and the ground terminal, and the voltage on the SYNC pin is the voltage divided by R2; the EN pin of the PWM controller is at a logic low level, and the voltage difference between the first end and the second end of D1 (i.e., the voltage difference between the EN pin and the SYNC pin) is less than the forward voltage drop of D1, and D1 does not conduct from the first end to the second end; the voltage on the SYNC pin is still the voltage divided by R2, and the voltage on this SYNC pin is at an intermediate state level.

[0104] Exemplarily, assuming that the power supply voltage received by the VCC pin is 3.3V and the resistances of R1 and R2 are the same, the voltage divided by R2 on the SYNC pin is 1.65V; assuming that when the subsequent load of the VRM is not working, the logic low level of the EN pin is 0.3V and the forward voltage drop of D1 is 0.3V, then D1 does not conduct, and the voltage on the SYNC pin is still 1.65V, the voltage divided by R2; if the tri-state voltage of the SYNC pin is as shown in Table 2, then the voltage on the SYNC pin is at an intermediate state level at this time.

[0105] The voltages on the R1, R2, and VCC pins, the logic level of the EN pin, the forward voltage drop of D1, etc. provided in this application are used to meet the implementation logic in the above two cases.

[0106] (2) The second improved VRM

[0107] refer to Figure 5 , Figure 5 An internal structure of SPS / DrMOS is shown as an example. Figure 5 As shown, inside the SPS / DrMOS, a resistor R3 is connected between the SYNC pin and the VCC pin, and a resistor R4 is connected between the SYNC pin and GND.

[0108] based on Figure 5 The SPS / DrMOS shown in Figure 2 Figure 6 , Figure 6 A peripheral connection method of the SYNC pin in an improved VRM provided in an embodiment of the present application is shown.

[0109] like Figure 6 As shown, the PWM controller and Figure 5 The SPS / DrMOS shown in the figure has a unidirectional conduction device D1 added to its periphery. That is, D1 is a peripheral circuit of the PWM controller and SPS / DrMOS, and D1, the PWM controller, and the SPS / DrMOS are not integrated in the same chip. The first end of D1 is connected to the EN pin of the PWM controller, and the second end of D1 is connected to the SYNC pin. When the voltage at the first end of D1 is greater than the voltage at the second end and the difference reaches the conduction voltage drop of D1, D1 conducts unidirectionally from the first end to the second end. In this way, R3 can achieve Figure 4 The function of R1 in the above example, R4 can realize Figure 4 The function of R2 is based on Figure 6 The VRM structure can also achieve the above-mentioned Figure 4 For details on the logic of the VRM structure, please refer to the previous article.

[0110] In some embodiments, Figure 4 R1 and Figure 6 R3 and R4 in the circuit can exist at the same time, so that the parallel resistance of R1 and R3 and R4 divides the voltage between the VCC pin and the ground terminal.

[0111] In some embodiments, Figure 4 R2 and Figure 6 R3 and R4 in the circuit can exist at the same time, so that the parallel resistance of R3, R2 and R4 divides the voltage between the VCC pin and the ground terminal.

[0112] In some embodiments, Figure 4 R1, R2 and Figure 6 R3 and R4 in the circuit can exist at the same time, so that the parallel resistance of R1 and R3 and the parallel resistance of R2 and R4 divide the voltage between the VCC pin and the ground terminal.

[0113] In the above three embodiments, by connecting R1 and R3 in parallel, and / or by connecting R2 and R4 in parallel, the voltage division on the SYNC pin can be changed. By setting R1 and / or R2 according to actual needs, the voltage on the SYNC pin can be at a suitable intermediate state level when the subsequent load of the VRM is not working. The suitable intermediate state level can be the intermediate range of the intermediate state level range of the SYNC pin. For example, when the intermediate state level range of the SYNC pin is 1.3V - 1.7V as shown in Table 2, the suitable intermediate state level can be around 1.5V. The suitable intermediate state level can improve the stability of the VRM and ensure the achievement of the purpose of this application.

[0114] In some embodiments, the SPS / DrMOS may only include R3 internally and not include R4, then it needs to be used in conjunction with Figure 4 R2 therein. Or, the SPS / DrMOS may only include R4 internally and not include R3, then it needs to be used in conjunction with Figure 4 R1 therein.

[0115] (3) The third improved VRM

[0116] Referring to Figure 7 , Figure 7 shows the peripheral connection method of the SYNC pin in an improved VRM provided by the embodiment of this application. This VRM includes Figure 5 the SPS / DrMOS shown in

[0117] As shown in Figure 7 , between the PWM controller and Figure 5 the SPS / DrMOS shown in D1 , a reserved position L for a unidirectional conduction device D1 is set between the EN pin and the SYNC pin R1 . A reserved position L for a resistor R1 is set between the VCC pin and the SYNC pin D1 . When no device is integrated at L R1 , the EN pin and the SYNC pin are disconnected; when no device is integrated at L D1 , the VCC pin and the SYNC pin are disconnected externally. That is, the reserved position L R1 and the reserved position L

[0118] If D1 is set at L D1 , L R1If R1 is not set, the EN pin and the SYNC pin are connected through D1, and the VCC pin and the SYNC pin are disconnected externally. D1, R3, and R4 can be used to achieve the purpose of this application, that is, when the subsequent load of the VRM works, a logic high level is input to the SYNC pin to enable the SPS / DrMOS to work properly. When the subsequent load of the VRM does not work, the SYNC pin is set to an intermediate state to reduce the extra power consumption on the VCC pin.

[0119] If L D1 If D1 is not set and R1 with 0Ω is set at L2, the EN pin and the SYNC pin are disconnected, and the VCC pin and the SYNC pin are directly connected externally. Such a connection method is Figure 3 the VRM with relatively large extra power consumption as shown.

[0120] It can be seen that Figure 7 the VRM shown can flexibly integrate devices at L D1 、L R1 as required to achieve different functions.

[0121] (4) The fourth improved VRM

[0122] During the normal operation of the PWM controller, when the EN pin of the PWM controller is at a logic high level, the VRM outputs voltage; when the EN pin of the PWM controller is at a logic low level, the VRM does not output voltage.

[0123] According to the improved VRM introduced above, the SYNC pin enters the high level state as the EN pin is set to the logic high level, and enters the intermediate state level as the EN pin is set to the logic low level. It can be seen that the voltage drops of the SYNC pin of the SPS / DrMOS and the EN pin of the PWM controller occur simultaneously. However, the voltage range for the SYNC pin to enter the intermediate state is about 1.3V - 1.7V, while the voltage threshold for the EN pin to enter the low level is about 0.4V, which is lower than the intermediate state level of the SYNC pin. Therefore, when the VRM stops outputting voltage instantaneously, it is possible that the SPS / DrMOS enters the standby mode first, and after a period of time t, the EN pin of the PWM controller enters the low level. During the time period t, the EN pin of the PWM controller is in the enabled state, but the SPS / DrMOS has entered the standby mode. When the PWM controller detects that it has enabled the output but the VRM does not output voltage, the PWM controller will report an output voltage undervoltage fault.

[0124] To avoid the above-mentioned undervoltage fault, the present application also provides an improved VRM, which can make the SYNC pin power off slower than the EN pin, that is, it can ensure that after the EN pin enters the low level, the SYNC pin enters the intermediate state level from the high level, thereby eliminating the output undervoltage fault reported at the moment of power-off.

[0125] refer to Figure 8 , Figure 8 A peripheral connection method of the SYNC pin in an improved VRM provided in an embodiment of the present application is shown.

[0126] like Figure 8 As shown, in Figure 4 Based on the structure shown, a capacitor C1 is added to the periphery of the PWM controller and SPS / DrMOS, the first end of C1 is connected to the SYNC pin, and the second end of C1 is grounded. That is, C1 is located in the peripheral circuit of the PWM controller and SPS / DrMOS, and C1, the PWM controller, and the SPS / DrMOS are not integrated in the same chip.

[0127] When the VRM's downstream load is working, the EN pin of the PWM controller is at a logic high level, D1 is turned on, and the voltage on the SYNC pin is at a logic high level. At this time, capacitor C1 is charged, and the voltage polarity is positive at the top and negative at the bottom. Soon after, it is charged to a capacitor voltage close to the logic high level input to the EN pin. When the VRM's downstream load is not working, the EN pin of the PWM controller is at a logic low level, and D1 is turned off. At this time, capacitor C1 gradually discharges, and the voltage released by C1 is superimposed on the voltage divider of R2 and output to the SYNC pin. Therefore, the voltage on the SYNC pin will gradually decrease from a logic high level to an intermediate state level. It can be seen that C1 can be used to adjust the timing of the SYNC pin entering the intermediate state level from a logic high level, so that the SYNC pin is powered off slower than the EN pin.

[0128] The fourth improved VRM can be combined with any of the above improved VRMs, that is, it can be used in Figure 4 On the basis of adding C1, you can also Figure 6 Add C1 on the basis, or you can Figure 6 In the optional implementation mode of adding C1, it is also possible to Figure 7 The first end of the above C1 is connected to the SYNC pin, the second end of C1 is grounded, and C1 can be realized in Figure 8 Same functionality in .

[0129] For example, reference Figure 9 , Figure 9 The peripheral connection mode of the SYNC pin in an improved VRM provided by an embodiment of the present application is shown. Figure 6 The SPS / DrMOS shown has C1 added.

[0130] C1 may also be referred to as the first capacitor.

[0131] Similarly, there is the same undervoltage risk during the power-on process of the PWM controller. After the PWM controller is powered on, it may take a period of time t before the SYNC pin of the SPS / DrMOS enters the high level. Within the time period t, the EN pin of the PWM controller is in the enabled state, but the SPS / DrMOS is still in the standby mode. When the PWM controller detects that it has enabled the output but the VRM does not output voltage, the PWM controller will report an output voltage undervoltage fault. Therefore, after the EN pin of the PWM controller enters the logic high level, the internal components of the PWM controller can start working after a delay. This can prevent the PWM controller from entering the enabled state before the SPS / DrMOS during the power-on process, thereby eliminating the reported output undervoltage fault at the moment of power-on.

[0132] In the improved VRM of the present application, it includes DrMOS, L, C, and the Figure 4 , Figures 6 - 8 The circuit of the peripheral structure of the PWM controller and DrMOS in can be referred to as the first circuit. The circuit including DrMOS, L, and C can be referred to as the second circuit. Among them, L and C can be the Figure 1 or Figure 2 L and C in, L may also be referred to as the first inductor, and C may also be referred to as the second capacitor.

[0133] Figure 1 or Figure 2 M1 in can also be referred to as the first switching transistor, and M2 can also be referred to as the second switching transistor.

[0134] The pull-up resistor module may include R1 and / or R3 mentioned above, and the pull-down resistor module may include R2 and / or R4 mentioned above. R1 may be referred to as the first resistor, R2 may be referred to as the second resistor, R3 may be referred to as the third resistor, and R4 may be referred to as the fourth resistor.

[0135] In the improved VRM provided by the present application, the PWM controller can be integrated in one chip, and the SPS / DrMOS is integrated in another chip, and the two chips are different. Alternatively, the PWM controller, SPS / DrMOS, and the peripheral circuits (such as L, C, C1, R1-R4, etc.) mentioned above can all be integrated into the same chip.

[0136] Generally speaking, the improved VRM provided by this application may include: a PWM controller, one or more SPS / DrMOS, and the peripheral connection relationship between the PWM controller and one or more SPS / DrMOS. The functions of each module in this VRM can be described in the previous text, and the peripheral connection relationship between the PWM controller and one or more SPS / DrMOS can refer to any of the connection relationships in the previous text Figure 4 , Figures 6 - 8 in the previous text

[0137] The improved VRM provided by this application can be a single-phase VRM or a multi-phase VRM

[0138] The improved VRM provided by this application is used to convert a relatively large DC voltage (such as 12V) output by the power supply in the electronic device into a stable relatively small DC voltage (such as 0.5V - 2V), and output it to the subsequent loads such as the CPU, GPU, and ASIC. Moreover, this VRM can also reduce the additional power consumption on the VCC pin of the SPS / DrMOS when the subsequent load of the VRM is not working

[0139] This application discloses a Printed Circuit Board (PCB), and this PCB may include any of the improved VRMs introduced above

[0140] This application discloses a chip system, and this chip system may include any of the improved VRMs introduced above

[0141] This application discloses a power supply system, and this power supply system may include: a power supply, any of the improved VRMs introduced above, and a load. The power supply is used to provide a DC input voltage for the VRM, and the VRM is used to reduce the DC input voltage provided by the power supply and then output it to the load

[0142] This application discloses a power supply circuit, and this power supply circuit may include: a power supply, any of the improved VRMs introduced above. The power supply is used to provide a DC input voltage for the VRM, and the VRM is used to reduce the DC input voltage provided by the power supply and then output it

[0143] This application discloses a power supply circuit, and this power supply circuit may include: any of the improved VRMs introduced above, and a load. The VRM is used to reduce the received DC input voltage and then output it to the load

[0144] This application discloses an electronic device, and this electronic device may include any of the improved VRMs introduced above

[0145] This application discloses an electronic device, and this electronic device may include the power supply system provided above

[0146] The present application discloses an electronic device, which may include any one of the power supply circuits provided above.

[0147] In the electronic device provided by the present application, when the subsequent load of the VRM is working, an application processor (AP) (such as a CPU) or a controller (such as an embedded controller (EC)) in the electronic device can input a logic high level to the EN pin of the PWM controller through the GPIO; when the subsequent load of the VRM is not working, the AP or the controller can input a logic low level to the EN pin of the PWM controller through the GPIO.

[0148] The electronic device disclosed in the present application can be a mobile phone, a tablet computer, a desktop computer, a desktop computer with a touch-sensitive surface or a touch panel, a laptop, a notebook computer, a smart screen, a wearable device (such as a smart watch, a smart bracelet, etc.), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a vehicle-mounted computer, a smart headset, a game console, an Internet of Things (IOT) device or a smart home device, etc.

[0149] Reference Figure 10 , Figure 10 FIG. 13 is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 is used for the voltage regulation method provided in the embodiment of the present application.

[0150] As Figure 10 shown, the electronic device 100 may include: a power supply 1001, a power management module 1002, a processor 1003, and a memory 1004.

[0151] The power supply 1001 may be a battery, and the battery can be charged by wired or wireless means, and can also supply power to each module in the electronic device through the power management module 1002.

[0152] The power management module 1002 is connected to the power supply 1001 and the processor 1003. The power management module 1002 receives the power supply voltage output by the power supply 1001 and supplies power to the processor 1003 and other modules. The power management module 1002 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 1002 can also be disposed in the processor 1003.

[0153] The processor 1003 may include one or more processing units. For example, the processor 1003 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0154] The memory 1004 may be used to store computer-executable program code, and the executable program code may include instructions. The processor 1003 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the memory 1004. The memory 1004 may include a program storage area and a data storage area. In a specific implementation, the memory 1004 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0155] The power management module 1002 in this application includes the improved VRM provided above. As Figure 10 shown, the power management module 1002 includes a VRM that powers the GPU in the processor 1003. The high-voltage input terminal of the VRM is connected to the high-voltage output terminal of the power supply 1001, and the low-voltage input terminal of the VRM is connected to the low-voltage output terminal of the power supply 1001 and grounded; the high-voltage output terminal of the VRM is connected to the high-voltage input terminal of the GPU, and the low-voltage output terminal of the VRM is connected to the low-voltage input terminal of the GPU and grounded. The structure of the VRM may refer to, for example, Figure 4 、 Figures 6 - 8 any one of the VRM structures in

[0156] Not limited to the GPU, other module in the electronic device 100, such as load modules like AP and ASIC, can be configured with corresponding VRMs in the power management module 1002 to reduce the power supply voltage output by the power supply 1001 to the core voltage required by these load modules and then supply it to the corresponding load modules.

[0157] As Figure 10As shown, the electronic device 100 may further include: a wireless communication module 1005, a mobile communication module 1006, an antenna 1005A, an antenna 1006A, a sensor module 1008, a focusing motor 1009, a camera 1010, a display screen 1011, etc. Among them, the sensor module 1008 may include a gyro sensor 1008A, an acceleration sensor 1008B, an ambient light sensor 1008C, an image sensor 1008D, a distance sensor 1008E, etc. Among them, the wireless communication module 1005 may include a WLAN communication module, a Bluetooth communication module, etc. Each part of the electronic device may transmit data through a bus.

[0158] The wireless communication function of the electronic device 100 may be implemented by the antenna 1005A, the antenna 1006A, the mobile communication module 1006, the wireless communication module 1005, a modulation and demodulation processor, a baseband processor, etc.

[0159] The antenna 1005A and the antenna 1006A may be used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication frequency bands. Different antennas may also be multiplexed to improve the utilization rate of the antennas.

[0160] The mobile communication module 1006 may provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc. applied to the electronic device 100. The mobile communication module 1006 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 1006 may receive electromagnetic waves by the antenna 1006A, and perform filtering, amplification, etc. on the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 1006 may also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves through the antenna 1006A and radiate it out.

[0161] The modulation and demodulation processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Subsequently, the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device, or displays an image or video through the display screen 1011.

[0162] The wireless communication module 1005 can provide wireless communication solutions including wireless local area networks (WLAN), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 1005 can be one or more devices integrating at least one communication processing module. The wireless communication module 1005 receives electromagnetic waves via the antenna 1005A, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 1003. The wireless communication module 1005 can also receive the signal to be sent from the processor 1003, modulate the frequency of the signal, amplify it, and convert it into electromagnetic waves for radiation through the antenna 1005A.

[0163] The gyroscope sensor 1008A can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., x, y, and z axes) can be determined by the gyroscope sensor 1008A. The gyroscope sensor 1008A can be used for anti-shake shooting. For example, when the shutter is pressed, the gyroscope sensor 1008A detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyroscope sensor 1008A can also be used for navigation and somatosensory game scenes.

[0164] The acceleration sensor 1008B can detect the magnitude of the acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device. For example, the acceleration sensor 1008B can be applied to applications such as horizontal and vertical screen switching, pedometers, etc.

[0165] The ambient light sensor 1008C is used to sense the brightness of the ambient light. The electronic device 100 can adaptively adjust the brightness of the display screen 1011 according to the sensed brightness of the ambient light. The ambient light sensor 1008C can also be used to automatically adjust the white balance when taking pictures.

[0166] The image sensor 1008D, also known as the photosensitive element, can convert the optical image on the photosensitive surface into an electrical signal in a corresponding proportional relationship with the optical image by using the photoelectric conversion function of the optoelectronic device. The image sensor can be a charge coupled device (CCD) sensor or a complementary metal-oxide-semiconductor (CMOS) sensor.

[0167] The distance sensor 1008E can be used to measure distance. The electronic device 100 can measure distance through infrared or laser. In some shooting scenarios, the electronic device 100 can use the distance sensor 1008E to measure distance to achieve rapid focusing.

[0168] The focusing motor 1009 can be used for rapid focusing. The electronic device 100 can control the movement of the lens through the focusing motor 1009 to achieve autofocus.

[0169] The electronic device 100 can achieve the shooting function through the ISP, camera 1010, video codec, GPU, display screen 1011, application processor, etc.

[0170] The ISP is used to process the data fed back by the camera 1010. For example, when taking a photo, the shutter is opened, and the light passes through the lens and is transmitted to the photosensitive element of the camera. The optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also optimize the noise and brightness of the image through algorithms. The ISP can also optimize parameters such as the exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 1010.

[0171] The camera 1010 can be used to capture static images or videos. The object generates an optical image through the lens and projects it onto the image sensor. The image sensor can convert the optical signal into an electrical signal, and then transmit the electrical signal to the ISP to convert it into a digital image signal. The ISP can output the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in standard RGB, YUV and other formats. In some embodiments, the electronic device 100 can include one or N processors 1003, where N is a positive integer greater than 1.

[0172] The video codec is used to compress or decompress digital images. The electronic device 100 can support one or more image codecs. In this way, the electronic device 100 can open or save pictures or videos in multiple coding formats.

[0173] The electronic device 100 can implement a display function through a GPU, a display screen 1011, an application processor, etc. The GPU is a microprocessor for image processing, and is connected to the display screen 1011 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 1003 may include one or more GPUs, which execute program instructions to generate or change display information.

[0174] The display screen 1011 is used to display images, videos, etc. The display screen 1011 includes a display panel. The display panel can adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 1011, where N is a positive integer greater than 1.

[0175] It can be understood that the structure schematically shown in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than those shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The components shown in the figure can be implemented in hardware, software, or a combination of software and hardware.

[0176] The present application also provides a voltage regulation method, which is applied to the improved VRM provided by the present application. In this method, when detecting an operation to start the subsequent load of the VRM, a logic high level is input to the EN pin of the PWM controller so that the SPS / DrMOS works normally; when detecting an operation to turn off the subsequent load of the VRM, a logic low level is input to the EN pin of the PWM controller so that the SPS / DrMOS enters the standby mode, thereby reducing the static current on the VCC pin and reducing the additional power consumption on the VCC pin.

[0177] In some embodiments, in combination with this voltage regulation method, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage requirement of the load, and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage requirement of the load. For example, if the voltage requirement of the load increases, the duty cycle is increased; otherwise, the duty cycle is decreased.

[0178] In some embodiments, in combination with this voltage regulation method, the electronic device can also obtain the current requirement of the load, and adjust the number of first circuits started in the N first circuits of the voltage regulation circuit according to the current requirement of the load. For example, if the current requirement of the load increases, the number of started first circuits is increased; otherwise, the number of started first circuits is decreased.

[0179] The various embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0180] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state disk (SSD)), etc.

[0181] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0182] The terms "first" and "second" are for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0183] In summary, the above description is only an embodiment of the technical solution of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made in accordance with the disclosure of the present application shall be included within the protection scope of the present application.

Claims

1. A voltage regulation circuit, characterized in that, it includes: a pulse width modulation (PWM) controller, a unidirectional conduction device, and a second circuit, wherein, the PWM controller includes an EN pin, and the EN pin of the PWM controller is connected to the input end of the enable signal of the PWM controller; the second circuit includes a DrMOS, and the DrMOS includes a SYNC pin and a VCC pin, the VCC pin is connected to the input end of the drive voltage of the DrMOS, and the SYNC pin is not connected to the input end of the drive voltage of the DrMOS; the first end of the pull-up resistor module is connected to the VCC pin, and the second end is connected to the SYNC pin; the first end of the pull-down resistor module is connected to the SYNC pin, and the second end is grounded; the pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor; the first ends of the first resistor and the third resistor are both connected to the VCC pin, and the second ends are both connected to the SYNC pin; the first ends of the second resistor and the fourth resistor are both connected to the SYNC pin, and the second ends are both grounded; the first resistor and the second resistor belong to the voltage regulation circuit and are located outside the PWM controller and the second circuit; the third resistor and the fourth resistor belong to the DrMOS; the first end of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second end is connected to the SYNC pin. When the voltage difference from the first end to the second end of the unidirectional conduction device is greater than the conduction voltage drop of the unidirectional conduction device, the unidirectional conduction device conducts from the first end to the second end, otherwise, the unidirectional conduction device is cut off.

2. The voltage regulation circuit according to claim 1, characterized in that, the PWM controller is used to output a PWM voltage signal to the second circuit, and the second circuit is used to reduce the voltage received by the high-voltage input end of the voltage regulation circuit according to the PWM voltage signal and then output it.

3. The voltage regulation circuit according to claim 1, characterized in that, the voltage regulation circuit includes N first circuits, and each first circuit includes a unidirectional conduction device and a second circuit.

4. The voltage regulation circuit according to claim 1, characterized in that, the static current on the VCC pin when the SYNC pin is at an intermediate state level is less than the static current on the VCC pin when the SYNC pin is at a logic high level; when the EN pin of the PWM controller receives a logic high level, the unidirectional conduction device conducts from the first end to the second end, and the SYNC pin receives a high level; when the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device is cut off from the first end to the second end, and the SYNC pin receives an intermediate state level.

5. The voltage regulation circuit according to claim 1, characterized in that, the voltage regulation circuit further includes: a first capacitor, the first end of the first capacitor is connected to the SYNC pin, and the second end of the first capacitor is grounded.

6. The voltage regulation circuit according to claim 5, wherein, the first capacitor is located outside the PWM controller and the second circuit.

7. The voltage regulation circuit according to claim 1, wherein, the unidirectional conduction device is a diode, the anode of the diode is connected to the EN pin of the PWM controller, and the cathode of the diode is connected to the SYNC pin.

8. The voltage regulation circuit according to claim 1, wherein, the DrMOS includes: a driver, a first switching transistor, and a second switching transistor, wherein, for the first switching transistor, the drain is connected to the high-voltage input terminal of the voltage regulation circuit, the gate is connected to the first output terminal of the driver, and the source is connected to the output terminal of the DrMOS; for the second switching transistor, the drain is connected to the output terminal of the DrMOS, the gate is connected to the second output terminal of the driver, and the source is grounded; the input terminal of the driver is connected to the output terminal of the PWM controller.

9. The voltage regulation circuit according to claim 8, wherein, when the PWM voltage signal received by the second circuit is in the positive half cycle, the first output terminal of the driver outputs a first driving signal, the first switching transistor is turned on, and the second switching transistor is turned off; when the PWM voltage signal received by the second circuit is in the negative half cycle, the second output terminal of the driver outputs a second driving signal, the first switching transistor is turned off, and the second switching transistor is turned on.

10. The voltage regulation circuit according to claim 8, wherein, the second circuit further includes: a first inductor, a second capacitor, the first end of the first inductor is connected to the output terminal of the DrMOS, the second end of the first inductor and the first end of the second capacitor are both connected to the high-voltage output terminal of the voltage regulation circuit, and the second end of the second capacitor is grounded.

11. The voltage regulation circuit according to claim 1, wherein, the high-voltage input terminal of the voltage regulation circuit is connected to the high-voltage output terminal of the power supply.

12. The voltage regulation circuit according to claim 1, wherein, the high-voltage output terminal of the voltage regulation circuit is connected to the high-voltage input terminal of the load.

13. The voltage regulation circuit according to claim 3, wherein, the current output from the high-voltage output terminal of the voltage regulation circuit is the sum of the output currents of the first circuits started in the N first circuits.

14. The voltage regulation circuit according to claim 1, wherein, the voltage regulation circuit is connected to a load, and the load includes any one of the following: CPU, GPU, ASIC.

15. The voltage regulation circuit according to claim 1, wherein, the input terminal of the enable signal of the PWM controller is a GPIO interface.

16. The voltage regulation circuit according to any one of claims 1-15, wherein, the PWM controller is integrated in a first chip, the DrMOS is integrated in a second chip, and the first chip and the second chip are different.

17. An electronic device, wherein, The electronic device includes the voltage regulation circuit as described in any one of claims 1-16.

18. A chip, characterized in that the chip includes the voltage regulation circuit as described in any one of claims 1-15.

19. A voltage regulation method, characterized in that the method is applied to an electronic device, the electronic device is the electronic device described in claim 17, the electronic device includes a load, the load is connected to the voltage regulation circuit, and the method includes: The electronic device detects an operation to start the load; The electronic device inputs a logic high level to the EN pin of the PWM controller; The electronic device detects an operation to turn off the load; The electronic device inputs a logic low level to the EN pin of the PWM controller.

20. According to the method described in claim 19, characterized in that the electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller through a GPIO interface.

21. According to the method described in claim 19, characterized in that after the electronic device inputs a logic high level to the EN pin of the PWM controller, the method further includes: The electronic device obtains the voltage requirement of the load; The electronic device adjusts the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage requirement of the load.

22. According to the method described in any one of claims 19-21, characterized in that the method further includes: The electronic device obtains the current requirement of the load; The electronic device adjusts the number of first circuits started in the N first circuits of the voltage regulation circuit according to the current requirement of the load.

Images