Signal generation circuit, test circuit and memory

Abstract

The present disclosure provides a signal generation circuit, a test circuit, and a memory, relating to the field of semiconductor technology. The signal generation circuit includes a counting circuit, which includes n+1 counting units cascaded in sequence, wherein the first output end of the counting unit of the previous stage is connected to the first input end of the counting unit of the next stage, and the first output end of the counting unit of the n+1 stage is connected to the first input end of the counting unit of the first stage; the counting units of the first to m stages each include a selector, each selector including a first selection signal input end; the counting units of the first to n stages are configured to: based on the selection signals received by the selectors in the counting units of the first to m stages, output a first counting signal with an n-bit step or a second counting signal with an n-bit jump. The counting signal output by the above-mentioned signal generation circuit can be used for various addressing modes such as address ascending addressing or address jump ascending addressing, which can better meet the testing requirements of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a signal generating circuit, a test circuit, and a memory. Background Art

[0002] MBIST (Memory Build In Self Test) is a test circuit built into the memory that can generate commands, addresses, data and other information to test the memory.

[0003] In MBIST, according to the controller's requirements, the address generation circuit generally counts in ascending order from 0. However, as testing requirements increase, the types of test vectors required are increasing, and existing test circuits can no longer meet current testing requirements. Summary of the Invention

[0004] The present disclosure provides a signal generating circuit, a test circuit, and a memory, which can solve the technical problem that the signal generating circuit in the existing test circuit cannot meet the test requirements.

[0005] In a first aspect, an embodiment of the present disclosure provides a signal generating circuit, including a counting circuit;

[0006] The counting circuit includes n+1 counting units cascaded in sequence, wherein the first output end of the counting unit of the previous stage is connected to the first input end of the counting unit of the next stage, and the first output end of the counting unit of the n+1th stage is connected to the first input end of the counting unit of the first stage;

[0007] The counting units of the 1st to mth stages each include a selector, each of the selectors includes a first selection signal input terminal, and both n and m are positive integers, and 3≤m<n;

[0008] The counting units of the 1st to the nth levels are configured to: output an n-bit step counting signal based on the step selection signal received by the selectors in the counting units of the 1st to the mth levels; or output an n-bit jump counting signal based on the jump selection signal received by the selectors in the counting units of the 1st to the mth levels.

[0009] In some embodiments, the counting signal includes a first counting signal and a second counting signal; the counting units at the 1st to n+1th stages each include a trigger, each trigger including a clock terminal, an input terminal, an output terminal, and an inverting output terminal; the clock terminal of each trigger receives the same clock signal; the output terminal of the trigger of the counting unit at the 2nd to nth stages serves as the first counting signal output terminal of the counting unit at the 2nd to nth stages, and the inverting output terminal of the trigger of the counting unit at the 2nd to nth stages serves as the second counting signal output terminal of the counting unit at the 2nd to nth stages;

[0010] The output end of the selector of the first-stage counting unit serves as the first counting signal output end of the first-stage counting unit, and the inverting output end corresponding to the output end of the selector of the first-stage counting unit serves as the second counting signal output end of the first-stage counting unit.

[0011] In some embodiments, the counting unit of the first stage includes a first trigger, a first selector, and an inverter;

[0012] The inverting output terminal of the first trigger is connected to the input terminal of the first trigger, and the output terminal of the first trigger is connected to the step receiving terminal of the first selector;

[0013] The jump receiving end of the first selector serves as the first input end of the counting unit of the first stage and is connected to the output end of the trigger in the counting unit of the n+1th stage;

[0014] The output end of the first selector serves as the first counting signal output end of the first-stage counting unit, and the output end of the first selector is connected to the input end of the inverter, and the output end of the inverter serves as the second counting signal output end corresponding to the first-stage counting unit;

[0015] The output end of the first selector also serves as the first output end of the first-stage counting unit.

[0016] In some embodiments, the counting unit of the second stage includes a first XOR gate, a second selector, a second flip-flop, and a first AND gate;

[0017] The first input terminal of the first XOR gate serves as the first input terminal of the second-stage counting unit, the second input terminal of the first XOR gate is connected to the output terminal of the second flip-flop, and the output terminal of the first XOR gate is connected to the step receiving terminal of the second selector;

[0018] The jump receiving end of the second selector is connected to the second counting signal output end of the second stage counting unit, and the output end of the second selector is connected to the input end of the second trigger;

[0019] The output end of the second flip-flop serves as the first counting signal output end of the second-stage counting unit, and the inverting output end of the second flip-flop serves as the second counting signal output end of the second-stage counting unit;

[0020] The first input end of the first AND gate is connected to the first input end of the second-level counting unit, the second input end of the first AND gate is connected to the first counting signal output end of the second-level counting unit, and the output end of the first AND gate serves as the first output end of the counting unit.

[0021] In some embodiments, the counting unit of the third stage includes a third selector, a second XOR gate, a third flip-flop, and a second AND gate;

[0022] The step receiving end of the third selector serves as the first input end of the counting unit of the third stage, and the jump receiving end of the third selector is connected to the first counting signal output end of the counting unit of the second stage;

[0023] The first input terminal of the second XOR gate is connected to the output terminal of the third selector, the second input terminal of the second XOR gate is connected to the output terminal of the third flip-flop, and the output terminal of the second XOR gate is connected to the input terminal of the third flip-flop;

[0024] The output end of the third flip-flop serves as the first counting signal output end of the third-stage counting unit, and the inverting output end of the third flip-flop serves as the second counting signal output end of the third-stage counting unit;

[0025] The first input of the second AND gate is connected to the output of the third selector, the second input of the second AND gate is connected to the output of the third trigger, and the output of the second AND gate serves as the first output of the third-stage counting unit.

[0026] In some embodiments, when 4≤i≤n, the counting unit of the i-th level includes an i-th XOR gate, an i-th flip-flop, and an i-th AND gate, where i is a positive integer;

[0027] The first input end of the i-th XOR gate serves as the first input end of the i-th counting unit, the second input end of the i-th XOR gate is connected to the output end of the i-th trigger, and the output end of the i-th XOR gate is connected to the input end of the i-th trigger;

[0028] The output end of the i-th trigger serves as the first counting signal output end of the i-th stage counting unit, and the inverting output end of the i-th trigger serves as the second counting signal output end of the i-th stage counting unit;

[0029] The first input end of the i-th AND gate is connected to the first input end of the i-th counting unit, the second input end of the i-th AND gate is connected to the output end of the i-th trigger, and the output end of the i-th AND gate serves as the first output end of the i-th counting unit.

[0030] In some embodiments, the counting unit of the n+1th stage includes an n+1th XOR gate and an n+1th flip-flop;

[0031] The first input end of the n+1th XOR gate serves as the first input end of the n+1th level counting unit, the second input end of the n+1th XOR gate is connected to the output end of the n+1th trigger, the output end of the n+1th XOR gate is connected to the input end of the n+1th trigger, and the output end of the n+1th trigger serves as the first output end of the n+1th level counting unit.

[0032] In some embodiments, m=3, and each of the selectors in the first to third stages of the counting units is configured as:

[0033] When the first selection signal input terminal receives a step selection signal, the signal received by the step receiving terminal is selected and output; when the first selection signal input terminal receives a jump selection signal, the signal received by the jump receiving terminal is selected and output.

[0034] In some embodiments, the signal generating circuit further includes a selection circuit, which includes a second selection signal input terminal, and the selection circuit is configured to output the counting signals output by the counting units of the 1st to nth levels in ascending or descending order based on the selection signal received at the second selection signal input terminal.

[0035] In some embodiments, the selection circuit includes n second selectors, each of the second selectors includes an ascending order receiving terminal, a descending order receiving terminal, and a second selection signal input terminal;

[0036] The ascending order receiving end of the i-th second selector is connected to the first counting signal output end corresponding to the i-th level counting unit, and the descending order receiving end of the i-th second selector is connected to the second counting signal output end corresponding to the i-th level counting unit; wherein, i

[0037] In some embodiments, the signal generating circuit is applied to a memory;

[0038] The signal generating circuit is configured to: based on the selection signal received by the first selection signal input terminal and the selection signal received by the second selection signal input terminal, select and output the counting signals output by the counting units of the 1st to nth levels as the row address addressing signal or the column address addressing signal of the memory.

[0039] In a second aspect, an embodiment of the present disclosure provides a test circuit for use in a memory built-in self-test, the test circuit comprising the signal generating circuit provided in the first aspect;

[0040] The counting signal output by the signal generating circuit is used as an address signal for the memory built-in self-test.

[0041] In a third aspect, an embodiment of the present disclosure provides a memory, comprising the test circuit provided in the second aspect.

[0042] The signal generating circuit, test circuit and memory provided by the embodiments of the present disclosure can realize a variety of counting timing control methods, such as address step ascending addressing, address jump ascending addressing and other addressing methods, thereby supporting more test vectors. The scheme is simple and easy to implement, and has little impact on circuit area, power consumption and timing, and can better meet the current memory testing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a signal generating circuit provided in an embodiment of the present disclosure Figure 1 ;

[0044] Figure 2 A schematic diagram of a signal generating circuit provided in an embodiment of the present disclosure Figure 2 ;

[0045] Figure 3 A schematic structural diagram of a counting circuit provided in an embodiment of the present disclosure;

[0046] Figure 4 A timing diagram of a signal generating circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method separately.

[0048] It should be noted that the brief descriptions of terms in this disclosure are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0049] In the specification and claims of this disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish between similar or similar objects or entities and are not necessarily intended to limit a particular order or precedence, unless otherwise noted. It should be understood that the terms used in this manner are interchangeable where appropriate, e.g., embodiments of the disclosure can be implemented in an order other than that shown or described in the drawings.

[0050] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0051] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the element.

[0052] It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present through which it is connected or coupled to the other element.

[0053] The embodiments of the present disclosure can be applied to the field of semiconductor technology, for example, can be applied to the test circuit design of memory in integrated circuit design, including the design of an address generator in memory testing to generate the address information required for memory testing, but it is not limited to this scope. Other command planning and generation circuits and counting timing control circuits can adopt the technical solutions provided by the embodiments of the present disclosure.

[0054] With the rapid development of integrated circuits (ICs), their scale is increasing, and the requirements for circuit quality and reliability are further increasing. Testing ICs is becoming increasingly difficult. To achieve rapid testing and screening of ICs, automated test equipment (ATE) provides strong support. ATE uses IC design simulation files as IC input stimulus, provides an IC test environment through the ATE test platform, and compares the IC output with the test results to determine the quality of the IC.

[0055] In the integrated circuit testing industry, test vectors represent the timing characteristics of the integrated circuit being tested. Simply put, during IC testing, ATE sends a series of timing signals to the input pins of the IC being tested. The output timing signals are then compared at the IC's output pins to verify that the IC meets its functional requirements. In a narrow sense, test vectors are the truth table of the IC.

[0056] MBIST is a test circuit built into the memory, capable of automatically generating commands, addresses, data, and other information for memory testing. "Built-in" refers to the fact that test vectors for the memory are not generated by an external ATE, but rather automatically generated by the built-in memory test logic, with results compared. During MBIST testing, the machine simply issues test commands via the standard JTAG interface, and the test results are retrieved via the TDO interface.

[0057] It is understood that a memory typically includes multiple bit lines (BLs), multiple word lines (WLs), and multiple memory cells, where each memory cell is connected to a corresponding WL and a corresponding BL. In practical applications, a memory cell can be activated using a row address and a column address to access it.

[0058] Address generation (AG) is an addressing technique that facilitates the addressing of large-capacity memories and the implementation of dynamic program floating. In MBIST, address generation circuits typically count in ascending order from 0, as required by the controller. However, as testing demands increase, the demand for more and more test vectors increases, and address generation circuits with only ascending addressing capabilities are no longer able to meet current testing needs.

[0059] In the face of the above technical problems, a signal generating circuit is provided in an embodiment of the present disclosure, which can generate a variety of counting timing controls such as step ascending counting, jump ascending counting, step descending counting, jump descending counting, etc. And it can be applied to test circuits. The test circuit has a simple structure and has little impact on circuit area, power consumption, and timing. It can realize a variety of addressing modes such as address step ascending addressing, address jump ascending addressing, address step descending addressing, address jump descending addressing, etc., so as to support more test vectors and better meet the test requirements of the memory. It should be noted that the function of the above test circuit is not limited to this range test circuit and MBIST. Other command planning and generation circuits and counting timing control circuits can adopt this design. The detailed process can be referred to the following embodiments.

[0060] Reference Figure 1 , Figure 1 A schematic diagram of a signal generating circuit provided in an embodiment of the present disclosure Figure 1 In some embodiments of the present disclosure, the signal generating circuit 100 includes a counting circuit 110 .

[0061] The counting circuit 110 includes n+1 counting units connected in cascade, wherein the first output of the previous counting unit is connected to the first input of the next counting unit, and the first output of the n+1th counting unit is connected to the first input of the first counting unit. Figure 1 In the embodiment, the first output terminal P1 of counting unit 1 is connected to the first input terminal S2 of counting unit 2, the first output terminal P2 of counting unit 2 is connected to the first input terminal S3 of counting unit 3, the first output terminal P3 of counting unit 3 is connected to the first input terminal S4 of counting unit 4, ..., the first output terminal Pn+1 of counting unit n+1 is connected to the first input terminal S1 of counting unit 1.

[0062] The first to mth stage counting units each include a selector Z, and each selector Z includes a first selection signal input terminal Se1 , wherein n and m are both positive integers, and 3≤m<n.

[0063] Optionally, n can be 4, 8, 10, 14, 15, 16, 32, etc., and can be specifically determined according to the number of address lines of the memory.

[0064] In some embodiments, the 1st to nth level counting units are configured to: output an n-bit step counting signal based on the step selection signal received by the selector in the 1st to mth level counting units; or output an n-bit jump counting signal based on the jump selection signal received by the selector in the 1st to mth level counting units.

[0065] In some embodiments, when the selectors in the 1st to mth stage counting units receive the step selection signal, the signals generated by the 1st to nth stage counting units according to the clock signal are output as the above-mentioned stepped counting signals.

[0066] When the selectors in the 1st to mth level counting units receive the jump selection signal, the selectors in the 1st level counting unit select the counting signal output by the n+1th level counting unit as the counting signal output by the 1st level counting unit; the selectors in the 2nd to mth level counting units select the input signals of the 2nd to mth level counting units so that the 2nd to n+1th level counting units output stepped counting signals, thereby enabling the 1st to nth level counting units to output n-bit jumping counting signals.

[0067] For example, taking n=8 and m=3 as an example, when the first selection signal input terminal Se1 of the selector in the 1st to mth stage counting units receives the step selection signal, the first counting signals output by the 1st to nth stage counting units of the counting circuit 110 will change with the clock signal in the manner of 00000000, 00000001, 00000010, 00000011, 00000100, ..., 11111110, 11111111, thereby generating a step-up ascending counting signal; when the above-mentioned first selection signal input terminal Se1 receives the jump selection signal, the selector in the 1st stage counting unit of the counting circuit 110 will select the counting signal output by the n+1th stage counting unit as the counting signal output by the 1st stage counting unit; the selectors in the 2nd and 3rd stage counting units will select the input signals of the 2nd and 3rd stage counting units in the counting circuit, so that the 2nd to n+1th stages The counting units output stepped counting signals, i.e., the counting signals output by the 2nd to n+1th stage counting units will change in the same manner as 00000000, 00000001, 00000010, 00000011, 00000100, ..., 11111110, 11111111 along with the clock signal. However, since the first stage counting unit of the counting circuit 110 outputs the counting signal output by the n+1th stage counting unit, Therefore, the second counting signals output by the 1st to nth stage counting units of the counting circuit 110 in this case will change in the manner of 00000000, 00000010, 00000100, 00000110, 00001000, ..., 11111110, and 00000001, 00000011, 00000101, ..., 11111111, thereby generating a jumping ascending counting signal.

[0068] In the embodiment of the present disclosure, by using the counting signal output by the n+1th stage counting unit as the lowest bit of the counting signal output by the counting circuit 110, and configuring the 2nd to n+1th stage counting units to output stepped counting signals according to the clock signal, the lowest bit counting signal output by the counting circuit 110 can be flipped only when the counting signal output by the 2nd to n+1th stage counting units reaches the highest bit of an even number or the highest bit of an odd number, thereby achieving the goal that the counting signal output by the counting circuit 110 can be increased by 2 each time the clock rises.

[0069] It is understandable that, based on the above principle, by selecting different values ​​of m, the counting signal output by the counting circuit 110 can be increased by 4 or 8 each time the clock rises, etc., which will not be described in detail in this embodiment.

[0070] In some embodiments, the first counting signal may be used as an ascending address for ascending addressing, and the second counting signal may be used as a skip ascending address for skip ascending addressing.

[0071] The signal generating circuit provided by the embodiment of the present disclosure can realize a variety of counting timing control methods, such as address ascending addressing, address jump ascending addressing and other addressing methods, so as to support more test vectors. The scheme is simple and easy to implement, and has little impact on circuit area, power consumption and timing, and can better meet the current memory testing requirements.

[0072] Reference Figure 2 , Figure 2 A schematic diagram of a signal generating circuit provided in an embodiment of the present disclosure Figure 2 In some embodiments of the present disclosure, the signal generating circuit 100 includes a counting circuit 110 and a selecting circuit 120. The selecting circuit 120 includes a second selecting signal input terminal. The selecting circuit 120 is configured to output the counting signals output by the 1st to nth stage counting units in ascending or descending order based on the selecting signal received at the second selecting signal input terminal.

[0073] In some embodiments, the first to nth stage counting units each include a first counting signal output terminal and a second counting signal output terminal. Figure 2 In the example, the first counting signal output terminals of the 1st to nth counting units are respectively denoted as RA <0> , RA <1> , RA <2> ,……,RA <n-1>The second counting signal output terminals of the 1st to nth counting units are respectively denoted as RB <0> , RB <1> , RB <2> ,……,RB <n-1>.

[0074] Among them, the second counting signal output terminal RB <0> , RB <1> , RB <2> ,……,RB <n-1>The output signals are respectively the first counting signal output terminal RA <0> , RA <1> , RA <2> ,……,RA <n>The output signal is the inverted signal.

[0075] For example, when RA <0> , RA <1> , RA <2> ,……,RA <7> When outputting 00001111 in sequence, RB <0> , RB <1> , RB <2> ,……,RB <7> Output 11110000 in sequence.

[0076] In some embodiments, the selection circuit 120 includes n second selectors, Figure 2 Each second selector includes an ascending order receiving terminal U, a descending order receiving terminal W, an output terminal RO, and a second selection signal input terminal Se2.

[0077] The ascending order receiving terminal U of the i-th second selector Xi <i-1>The first counting signal output terminal RA corresponding to the i-th stage counting unit <i-1>Connect the descending order receiving end W of the i-th second selector Xi <i-1>The second counting signal output terminal RB corresponding to the i-th stage counting unit <i-1>connection; where i∈{1, 2, 3, …, n}.

[0078] In some embodiments, each of the above-mentioned second selectors selects to output the signal received by the ascending receiving end when receiving an ascending selection signal at the second selection signal input end Se2, and selects to output the signal received by the descending receiving end when receiving a descending selection signal at the second selection signal input end Se2.

[0079] Optionally, the ascending selection signal may be a low-level signal 0, and the descending selection signal may be a high-level signal 1. Alternatively, the ascending selection signal may be a high-level signal 1, and the descending selection signal may be a low-level signal 0. Alternatively, the ascending selection signal and the descending selection signal may be two signals in other forms, which are not limited in the embodiments of the present disclosure.

[0080] It is understandable that when the first selection signal input terminal Se1 receives the step selection signal and the second selection signal input terminal Se2 receives the ascending selection signal, the output terminals RO of the n second selectors are <n-1>,……,RO <2> , RO <1> , RO <0> Output counting signal RO <n-1:0>When the first selection signal input terminal Se1 receives the step selection signal and the second selection signal input terminal Se2 receives the descending selection signal, the output terminal of the n second selectors outputs a signal RO <n-1:0>When the first selection signal input terminal Se1 receives the jump selection signal and the second selection signal input terminal Se2 receives the ascending selection signal, the output terminal of the n second selectors outputs a signal RO <n-1:0>When the first selection signal input terminal Se1 receives the jump selection signal and the second selection signal input terminal Se2 receives the descending selection signal, the output terminal of the n second selectors outputs the signal RO <n-1:0>It is a descending count signal of jumps.

[0081] In some embodiments, the above-mentioned signal generating circuit can be applied to a memory; the above-mentioned signal generating circuit can be configured to: based on the selection signal received by the first selection signal input terminal Se1 and the selection signal received by the second selection signal input terminal Se2, select and output the counting signals output by the 1st to nth level counting units as the row address addressing signal or the column address addressing signal of the memory.

[0082] It is understandable that as the density of memory continues to increase, the data lines in its storage cells are physically closer, resulting in a gradual increase in capacitive coupling between adjacent data lines. In the process of testing the memory, when reading and writing a certain data line, it will have an impact on the adjacent data lines, including but not limited to leakage, causing faults between data lines. Through jump addressing, different data can be written to each data line, making it easier to stimulate faults and facilitate troubleshooting. For example, by writing data to the data lines in rows 1, 3, 5, ..., the leakage of the data lines in rows 2, 4, 6, ... can be tested.

[0083] In addition, faults between storage cells can also be detected through jump addressing. For example, by writing different data to different data lines, the leakage effect of surrounding storage cells on the target storage cell is stimulated to detect the problem.

[0084] The disclosed embodiments provide a signal generating circuit that can implement a variety of counting timing control methods, such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, and other addressing methods, thereby supporting more test vectors. The solution is simple and easy to implement, and has little impact on circuit area, power consumption, and timing, and can better meet the current memory testing requirements.

[0085] Based on the contents described in the above embodiments, in some embodiments, m=3, and the first selection signal input terminals Se1 of the selectors in the first to third stage counting units receive the same selection signal.

[0086] In some embodiments, the above-mentioned counting signal includes a first counting signal and a second counting signal; the 1st to n+1th level counting units all include a trigger, which includes a clock terminal, an input terminal, an output terminal and an inverting output terminal; the clock terminal of each trigger receives the same clock signal; the output terminal of the trigger of the 2nd to nth level counting unit serves as the first counting signal output terminal of the 2nd to nth level counting unit, and the inverting output terminal of the trigger of the 2nd to nth level counting unit serves as the second counting signal output terminal of the 2nd to nth level counting unit.

[0087] In some embodiments, the output end of the selector of the first-stage counting unit can serve as the first counting signal output end of the first-stage counting unit, and the inverting output end corresponding to the output end of the selector of the first-stage counting unit can serve as the second counting signal output end of the first-stage counting unit.

[0088] Optionally, the flip-flop in each of the counting units may be a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF). A D-type flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit in various sequential circuits and an important unit circuit in digital logic circuits. A D-type flip-flop has two stable states, "0" and "1," and can flip from one stable state to the other under the influence of a signal received at the clock terminal of the flip-flop.

[0089] In the embodiment of the present disclosure, a trigger is used to realize the jump of the counting circuit under the control of the clock signal. For example, when each rising edge of the clock signal arrives, the output signal of each trigger is flipped, thereby realizing the change of the counting signal.

[0090] In some implementations, the inverted second counting signal may be directly outputted via the inverting output terminal of the flip-flop.

[0091] Take n=8, m=3 as an example, refer to Figure 3 , Figure 3 A schematic structural diagram of a counting circuit provided in an embodiment of the present disclosure.

[0092] exist Figure 3 In the embodiment, the counting circuit 110 includes nine counting units connected in cascade. Each counting unit includes a flip-flop, which includes a clock terminal, an input terminal D, an output terminal Q, an inverting output terminal Q', and a reset terminal RST. The clock terminal of each flip-flop receives the same clock signal CLK. The reset terminal RST of each stage of the flip-flop is used to receive a reset signal, which can reset the counting circuit and restart counting.

[0093] In the embodiment of the present disclosure, the triggers in the above 9 cascaded counting units are respectively recorded as D0, D1, D2, ..., D7, D8; the first counting signal output terminals in the above 1st to 8th stage counting units are respectively recorded as RA <0> , RA <1> , RA <2> ,……,RA <7> The second counting signal output terminals of the above-mentioned 1st to 8th level counting units are respectively denoted as RB <0> , RB <1> , RB <2> ,……,RB <7> ; The counting signal output end of the 9th-level counting unit is recorded as R0.

[0094] The selectors in the first to third stage counting units all include a first selection signal input terminal Se1 for receiving the same selection signal.

[0095] In some embodiments, as Figure 3 As shown in , the first-stage counting unit includes a first flip-flop D0, a first selector 101, and an inverter NOT. The inverting output terminal Q' of the first flip-flop D0 is connected to the input terminal D of the first flip-flop D0, and the output terminal Q of the first flip-flop D0 is connected to the step receiving terminal b of the first selector 101; the jump receiving terminal a of the first selector 101 serves as the first input terminal of the first-stage counting unit and is connected to the output terminal Q of the flip-flop D8 in the ninth-stage counting unit; the output terminal x of the first selector 101 serves as the first counting signal output terminal of the first-stage counting unit, and the output terminal x of the first selector 101 is connected to the input terminal of the inverter NOT, and the output terminal of the inverter NOT serves as the second counting signal output terminal RB corresponding to the first-stage counting unit. <0> .

[0096] The output terminal x of the first selector 101 also serves as the first output terminal of the first-stage counting unit.

[0097] It can be understood that the first stage counting unit can realize the step and jump selection functions of the first stage counting unit through the above-mentioned first selector 101, and output the second counting signal through the inverter.

[0098] The second-stage counting unit includes a first XOR gate XOR1, a second selector 102, a second flip-flop D1, and a first AND gate AND1. The first input of the first XOR gate XOR1 serves as the first input of the second-stage counting unit, the second input of the first XOR gate XOR1 is connected to the output Q of the second flip-flop D1, the output of the first XOR gate XOR1 is connected to the step receiving terminal b of the second selector 102, and the jump receiving terminal a of the second selector 102 is connected to the second counting signal output terminal RB of the second-stage counting unit. <1> The output terminal y of the second selector 102 is connected to the input terminal D of the second flip-flop D1; the output terminal Q of the second flip-flop D1 is connected to the first counting signal output terminal RA of the second stage counting unit. <1> The inverting output terminal Q' of the second trigger D1 serves as the second counting signal output terminal RB corresponding to the second stage counting unit. <1> The first input terminal of the first AND gate AND1 is connected to the first input terminal of the second stage counting unit, and the second input terminal of the first AND gate AND1 is connected to the first counting signal output terminal RA of the second stage counting unit. <1> The output end of the first AND gate AND1 serves as the first output end of the second-stage counting unit.

[0099] The third-stage counting unit includes a third selector 103, a second XOR gate XOR2, a third flip-flop D2, and a second AND gate AND2. The step receiving terminal b of the third selector 103 serves as the first input terminal of the third-stage counting unit, and the jump receiving terminal a of the third selector 103 is connected to the first counting signal output terminal RA corresponding to the second-stage counting unit. <1> The first input terminal of the second XOR gate XOR2 is connected to the output terminal z of the third selector 103, the second input terminal of the second XOR gate XOR2 is connected to the output terminal Q of the third flip-flop D2, and the output terminal of the second XOR gate XOR2 is connected to the input terminal D of the third flip-flop D2; the output terminal Q of the third flip-flop D2 serves as the first counting signal output terminal RA corresponding to the third-stage counting unit <2> The inverting output terminal Q' of the third trigger D2 serves as the second counting signal output terminal RB corresponding to the third stage counting unit. <2> The first input terminal of the second AND gate AND2 is connected to the output terminal z of the third selector 103, the second input terminal of the second AND gate AND2 is connected to the output terminal Q of the third flip-flop D2, and the output terminal of the second AND gate AND2 serves as the first output terminal of the third stage counting unit.

[0100] By analogy, taking m=3 as an example, when 4≤i≤8, the i-th level counting unit includes an i-th XOR gate, an i-th flip-flop, and an i-th AND gate, where i is a positive integer. The first input of the i-th XOR gate serves as the first input of the i-th level counting unit, the second input of the i-th XOR gate is connected to the output of the i-th flip-flop, and the output of the i-th XOR gate is connected to the input of the i-th flip-flop; the output of the i-th flip-flop serves as the first counting signal output of the i-th level counting unit, and the inverting output of the i-th flip-flop serves as the second counting signal output of the i-th level counting unit; the first input of the i-th AND gate is connected to the first input of the i-th level counting unit, the second input of the i-th AND gate is connected to the output of the i-th flip-flop, and the output of the i-th AND gate serves as the first output of the i-th level counting unit.

[0101] The ninth stage counting unit includes a ninth XOR gate XOR9 and a ninth flip-flop D8. A first input terminal of the ninth XOR gate XOR9 serves as the first input terminal of the ninth stage counting unit, a second input terminal of the ninth XOR gate is connected to an output terminal Q of the ninth flip-flop D8, an output terminal of the ninth XOR gate XOR9 is connected to an input terminal D of the ninth flip-flop D8, and an output terminal Q of the ninth flip-flop D8 serves as the first output terminal of the ninth stage counting unit.

[0102] In some embodiments, each selector in the first to third stage counting units is respectively configured as:

[0103] When the first selection signal input terminal Se1 receives a step selection signal, the signal received by the step receiving terminal b is selected and output; when the first selection signal input terminal Se1 receives a jump selection signal, the signal received by the jump receiving terminal a is selected and output.

[0104] Optionally, the step selection signal may be a low-level signal 0, and the skip selection signal may be a high-level signal 1. Alternatively, the step selection signal may be a high-level signal 1, and the skip selection signal may be a low-level signal 0. Alternatively, the step selection signal and the skip selection signal may be two signals in other forms, which are not limited in the embodiments of the present disclosure.

[0105] For a better understanding of the embodiments of the present disclosure, taking D0, D1, D2, ..., D8 as rising edge triggers as an example, when the first selection signal input terminal Se1 receives a step selection signal, the working principle of the above-mentioned counting circuit 110 is as follows:

[0106] In the initial state, the reset signal RST is used to reset D0, D1, D2, ..., D7, and D8, so that the signal output terminals Q of D0, D1, D2, ..., D7, and D8 all output low level 0. At this time, RA <7> , RA <6> , RA <5> ,……,RA <0> The initial count signals RA<7:0> outputted sequentially are 00000000.

[0107] Before the first rising edge of the clock signal appears, except for the signal input terminal D of D0 which is at a high level 1 (because the inverted signal output terminal Q' of D0 is connected to its input terminal D), the input terminals D of the remaining D1, D2, ..., D7 are all at a low level 0. Therefore, when the first rising edge of the clock signal appears, the output terminal Q of D0 flips from a low level 0 to a high level 1, and the output terminals Q of the remaining D1, D2, ..., D7 remain at a low level 0. Since the output terminal x of the first selector 101 now selects to output the high level 1 received by the second receiving terminal b, the counting signal RA<7:0> output by the counting circuit 110 is 00000001.

[0108] Before the second rising edge of the clock signal appears, the input terminal D of D0 is at a low level 0 (for the same reason as above), the input terminal D of D1 is at a high level 1 (this is because the second input terminal of the first XOR gate XOR1 connected to the output terminal x is at a high level 1, and the first input terminal connected to the output terminal Q of D1 is at a low level 0, so that the output terminal of the first XOR gate XOR1 is at a high level 1, and the output terminal y of the second selector 102 now selects to output the signal received by the second receiving terminal b). The remaining input terminals D of D2, ..., D7 are all at a low level 0. Therefore, when the second rising edge of the clock signal appears, the output terminal Q of D1 flips from a low level 0 to a high level 1, and the output terminals Q of the remaining D0, D2, D3, ..., D7 remain at a low level 0, and the counting signal RA<7:0> output by the counting circuit 110 is 00000010.

[0109] Before the third rising edge of the clock signal, the input terminal D of D0 is at a high level 1 (for the same reason as above), the input terminal D of D1 is at a high level 1 (for the same reason as above), and the remaining input terminals D of D2, ..., D7 are all at a low level 0. Therefore, when the third rising edge of the clock signal appears, the output terminal Q of D0 flips from a low level 0 to a high level 1, the output terminal Q of D1 remains at a high level 1, and the output terminals Q of the remaining D2, D3, ..., D7 remain at a low level 0. The counting signal RA<7:0> output by the counting circuit 110 is 00000011.

[0110] By analogy, when the fourth rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit 110 is 00000100; when the fifth rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit 110 is 00000101, ..., when the 255th rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit 110 is 11111111, thereby generating a continuous ascending counting signal.

[0111] In some embodiments, when the first selection signal input terminal Se1 receives the skip selection signal, the operation principle of the counting circuit 110 is as follows:

[0112] In the initial state, the reset signal RST is used to reset D0, D1, D2, ..., D7, and D8, so that the output terminals Q of D0, D1, D2, ..., D7, and D8 all output low level 0. At this time, RA <7> , RA <6> , RA <5> ,……,RA <0> The output counting signal RA<7:0> is 00000000.

[0113] Before the first rising edge of the clock signal appears, since the output terminal x of the first selector 101 selects to output the counting signal R0 received by the first receiving terminal a, when the first rising edge of the clock signal appears, RA <0> At this time, the output is low level 0. At the same time, since the output terminal y of the second selector 102 selects to output the counting signal RB received by the first receiving terminal a, <1> , due to RB <1> For RA <1> The inverted signal of D1 makes the input terminal D high level 1. When the first rising edge of the clock signal appears, the output terminal Q of D1 flips to high level 1, and RA <1> At this time, the output terminal z of the third selector 103 selects to output the counting signal RA received by the first receiving terminal a. <1> The two input terminals of the XOR gate XOR2 receive the counting signal RA <1> (Low level 0) and RA <2> (low level 0), it outputs low level 0. Therefore, when the first rising edge of the clock signal appears, RA <2> Output low level 0, the output terminals Q of the remaining D3, D4, . . . , D7, and D8 all maintain low level 0, and the counting signal RA<7:0> output by the counting circuit 110 is 00000010.

[0114] Before the second rising edge of the clock signal appears, since the output terminal x of the first selector 101 selects to output the counting signal R0 received by the first receiving terminal a, when the second rising edge of the clock signal appears, RA <0> At this time, the output is still low level 0. At the same time, since the output terminal y of the second selector 102 now selects to output the counting signal RB received by the first receiving terminal a, <1> , due to RB <1> For RA <1> The inverted signal of D1 makes the input terminal D of D1 low level 0. When the second rising edge of the clock signal appears, the output terminal Q of D1 flips to low level 0, and RA <1> At this time, the output is low level 0; the third output terminal z of the third selector 103 selects to output the counting signal RA received by the first receiving terminal a at this time. <1> The two input terminals of the XOR gate XOR2 receive the counting signal RA <1> (High level 1) and RA <2> (low level 0), it outputs high level 1. Therefore, when the second rising edge of the clock signal appears, RA <2> Output high level 1, the output terminals Q of the remaining D3, D4, . . . , D7 all maintain low level 0, and the counting signal RA<7:0> output by the counting circuit 110 is 00000100.

[0115] Before the third rising edge of the clock signal appears, since the output terminal x of the first selector 101 selects to output the counting signal R0 received by the first receiving terminal a, when the third rising edge of the clock signal appears, RA <0> At this time, the output is still low level 0. At the same time, since the output terminal y of the second selector 102 now selects to output the counting signal RB received by the first receiving terminal a, <1> , due to RB <1> For RA <1> The inverted signal of D1 makes the input terminal D high level 1. When the third rising edge of the clock signal appears, the output terminal Q of D1 flips to high level 1, and RA <1> At this time, the output terminal z of the third selector 103 selects to output the counting signal RA received by the first receiving terminal a. <1> The two input terminals of the XOR gate XOR2 receive the counting signal RA <1> (Low level 0) and RA <2> (high level 1), it outputs high level 1. Therefore, when the third rising edge of the clock signal appears, RA <2> Output high level 1, the output terminals Q of the remaining D3, D4, . . . , D7 all maintain low level 0, and the counting signal RA<7:0> output by the counting circuit 110 is 00000110.

[0116] By analogy, when the fourth rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit 110 is 00001000; when the fifth rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit is 00001010, and so on; when the 127th rising edge of the clock signal appears, the counting signal RA<7:0> output by the counting circuit 110 is 11111110, thereby generating a jumping timing counting signal.

[0117] It can be understood that after the counting signal RA<7:0> reaches the highest even bit at the 127th rising edge, when the clock signal appears at the 128th rising edge, R0 will flip from 0 to 1, so that the counting signal RA<7:0> output by the counting circuit 110 is 10000001, when the clock signal appears at the 129th rising edge, the counting signal RA<7:0> output by the counting circuit 110 is 00000011, when the clock signal appears at the 129th rising edge, the counting signal RA<7:0> output by the counting circuit 110 is 00000101, ..., and so on, until the highest odd bit, which will not be elaborated in the embodiments of the present disclosure.

[0118] In some embodiments, the counting circuit may also be implemented by other structures, such as using an inverter to output an inverted signal of the counting signal output from the first counting signal output terminal, which will not be described in detail in this embodiment.

[0119] For a better understanding of the embodiments of the present disclosure, in some embodiments of the present disclosure, if n=16, the counting circuit may include 17 cascaded counting units. When the initial output value of each counting unit is 0, each counting unit undergoes a transition at each rising edge of the clock signal Clk output by the clock source, and the signal generation circuit and test circuit output a 16-bit binary counting signal RO<15:0>.

[0120] Reference Figure 4 , Figure 4 A timing diagram of a signal generating circuit provided in an embodiment of the present disclosure.

[0121] It should be noted that for ease of reading, Figure 4 The 16-bit binary count signal RO<15:0> is converted into hexadecimal and displayed.

[0122] The counting circuit can use the signal of the first selection signal input terminal Se1 to select and output a stepping counting signal or a jumping counting signal, and the selection circuit can use the signal of the second selection signal input terminal Se2 to select and output an ascending counting signal or a descending counting signal.

[0123] For example, Figure 4 As shown in FIG, taking the step selection signal and the ascending selection signal as low level 0, and the skip selection signal and the descending selection signal as high level 1 as an example, when the first selection signal input terminal Se1 and the second selection signal input terminal Se2 are both low level 0, the count value of the counting signal RO<15:0> is increased by 1 along with the rising edge of the clock signal. At this time, RO<15:0> can be used as an ascending addressing signal; when the first selection signal input terminal Se1 is low level 0 and the second selection signal input terminal Se2 is high level 1, the count value of RO<15:0> is decreased by 1 along with the rising edge of the clock signal. 1, at this time RO<15:0> can be used as a descending addressing signal; when the first selection signal input terminal Se1 is a high level 1 and the second selection signal input terminal Se2 is a low level 0, the count value of RO<15:0> is increased by 2 with the rising edge of the clock signal, and at this time RO<15:0> can be used as a skip ascending addressing signal; when the first selection signal input terminal Se1 and the second selection signal input terminal Se2 are both high level 1, the count value of RO<15:0> is reduced by 2 with the rising edge of the clock signal, and at this time RO<15:0> can be used as a skip descending addressing signal.

[0124] The signal generating circuit and the test circuit provided in the embodiments of the present disclosure, based on the counting circuit, can realize a variety of addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, etc. by designing the above-mentioned selection circuit, thereby being able to support more test vectors. The scheme is simple and easy to implement, and has little impact on circuit area, power consumption, and timing, and can better meet the current memory testing requirements.

[0125] Based on the contents described in the above embodiments, in some embodiments, the present disclosure further provides a test circuit for use in memory built-in self-test, where the test circuit includes the signal generating circuit described in the above embodiments.

[0126] In some implementations, the counting signal output by the signal generating circuit may be used as an address signal for a memory built-in self-test.

[0127] It's understandable that as memory density increases, the data lines within its storage cells become physically closer, leading to increased capacitive coupling between adjacent data lines. During memory testing, reading or writing a data line can affect adjacent data lines, including but not limited to leakage, which can cause faults between data lines. By using jump addressing, different data can be written to each data line, making it easier to trigger faults and facilitating troubleshooting.

[0128] For example, taking a memory device having 16 data lines as an example, the jump ascending count signal output by the signal generation circuit can be used to write data to the data lines in rows 1, 3, 5, ..., 13, and 15 to test the leakage of the data lines in rows 2, 4, 6, ..., 14, and 16; and the leakage of the data lines in rows 1, 3, 5, ..., 13, and 15 can be tested by writing data to the data lines in rows 2, 4, 6, ..., 14, and 16. Alternatively, the jump descending count signal output by the signal generation circuit can be used to write data to the data lines in rows 15, 13, ..., 5, 3, and 1 to test the leakage of the data lines in rows 16, 14, ..., 6, 4, and 2; and the leakage of the data lines in rows 15, 13, ..., 5, 3, and 1 can be tested by writing data to the data lines in rows 16, 14, ..., 6, 4, and 2.

[0129] Similarly, the jump ascending count signal output by the above-mentioned signal generating circuit can be used to write data to the 1st, 3rd, 5th, ..., 13th, and 15th column data lines to test the leakage conditions of the 2nd, 4th, 6th, ..., 14th, and 16th column data lines; and the leakage conditions of the 1st, 3rd, 5th, ..., 13th, and 15th column data lines can be tested by writing data to the 2nd, 4th, 6th, ..., 14th, and 16th column data lines. This will not be repeated in this embodiment.

[0130] In addition, faults between storage cells can also be detected through jump addressing. For example, by writing different data to different data lines, the leakage effect of surrounding storage cells on the target storage cell is stimulated to detect the problem.

[0131] The test circuit provided in the embodiments of the present disclosure can be applied to a memory built-in self-test (BIST). It can detect faults between data lines or between memory cells through address jumps in ascending or descending order. The solution is simple and easy to implement, with minimal impact on circuit area, power consumption, and timing, better meeting current memory testing requirements. Based on the content described in the above embodiments, the embodiments of the present disclosure also provide a memory including the signal generation circuit or test circuit described in the above embodiments, which will not be further described here.

[0132] Optionally, the above-mentioned memory can be various types of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc., which is not limited in the embodiments of the present disclosure.

[0133] Since MBIST is a test circuit established inside the memory, in some implementations, multiple counting signals such as ascending count signals, jumping ascending count signals, descending count signals, and jumping descending count signals generated by the signal generating circuit can be used as test vectors to implement memory testing. On the one hand, because the test vectors are generated by internal logic, the corresponding module can work together with the memory being tested under the internal high-speed functional clock without the need to shift in the test vectors by the machine's slow clock, which can save a lot of test time; on the other hand, the comparison and verification are also left to the internal logic to complete, and the test machine only needs to collect test results, which can also greatly reduce the test time and better meet the test requirements of the memory.

[0134] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure. < / n>

Claims

1. A signal generating circuit, characterized in that: including a counting circuit; The counting circuit includes n+1 counting units cascaded in sequence, wherein the first output end of the counting unit of the previous stage is connected to the first input end of the counting unit of the next stage, and the first output end of the counting unit of the n+1th stage is connected to the first input end of the counting unit of the first stage; The counting units of the 1st to mth stages each include a selector, each of the selectors includes a first selection signal input terminal, and both n and m are positive integers, and 3≤m<n; The counting units of the first to nth stages are configured to: output an n-bit step counting signal based on the step selection signal received by the selectors in the first to mth stages; or output an n-bit jump counting signal based on the jump selection signal received by the selectors in the first to mth stages; The counting signal includes a first counting signal and a second counting signal; the counting units of the 1st to n+1th stages each include a trigger, and the trigger includes a clock terminal, an input terminal, an output terminal, and an inverting output terminal; the clock terminal of each trigger receives the same clock signal; the output terminal of the trigger of the counting unit of the 2nd to nth stages serves as the first counting signal output terminal of the counting unit of the 2nd to nth stages, and the inverting output terminal of the trigger of the counting unit of the 2nd to nth stages serves as the second counting signal output terminal of the counting unit of the 2nd to nth stages; The output end of the selector of the first-stage counting unit serves as the first counting signal output end of the first-stage counting unit, and the inverting output end corresponding to the output end of the selector of the first-stage counting unit serves as the second counting signal output end of the first-stage counting unit; The counting unit of the first stage includes a first trigger, a first selector and an inverter; The inverting output terminal of the first trigger is connected to the input terminal of the first trigger, and the output terminal of the first trigger is connected to the step receiving terminal of the first selector; The jump receiving end of the first selector serves as the first input end of the counting unit of the first stage and is connected to the output end of the trigger in the counting unit of the n+1th stage; The output end of the first selector serves as the first counting signal output end of the first-stage counting unit, and the output end of the first selector is connected to the input end of the inverter, and the output end of the inverter serves as the second counting signal output end corresponding to the first-stage counting unit; The output end of the first selector also serves as the first output end of the first-stage counting unit.

2. The signal generating circuit according to claim 1, wherein: The counting unit of the second stage includes a first XOR gate, a second selector, a second flip-flop and a first AND gate; The first input terminal of the first XOR gate serves as the first input terminal of the second-stage counting unit, the second input terminal of the first XOR gate is connected to the output terminal of the second flip-flop, and the output terminal of the first XOR gate is connected to the step receiving terminal of the second selector; The jump receiving end of the second selector is connected to the second counting signal output end of the second stage counting unit, and the output end of the second selector is connected to the input end of the second trigger; The output end of the second flip-flop serves as the first counting signal output end of the second-stage counting unit, and the inverting output end of the second flip-flop serves as the second counting signal output end of the second-stage counting unit; The first input end of the first AND gate is connected to the first input end of the second-level counting unit, the second input end of the first AND gate is connected to the first counting signal output end of the second-level counting unit, and the output end of the first AND gate serves as the first output end of the counting unit.

3. The signal generating circuit according to claim 1, wherein: The counting unit of the third stage includes a third selector, a second XOR gate, a third flip-flop and a second AND gate; The step receiving end of the third selector serves as the first input end of the counting unit of the third stage, and the jump receiving end of the third selector is connected to the first counting signal output end of the counting unit of the second stage; The first input terminal of the second XOR gate is connected to the output terminal of the third selector, the second input terminal of the second XOR gate is connected to the output terminal of the third flip-flop, and the output terminal of the second XOR gate is connected to the input terminal of the third flip-flop; The output end of the third flip-flop serves as the first counting signal output end of the third-stage counting unit, and the inverting output end of the third flip-flop serves as the second counting signal output end of the third-stage counting unit; The first input of the second AND gate is connected to the output of the third selector, the second input of the second AND gate is connected to the output of the third trigger, and the output of the second AND gate serves as the first output of the third-stage counting unit.

4. The signal generating circuit according to claim 1, wherein: When 4≤i≤n, the counting unit of the i-th level includes the i-th XOR gate, the i-th trigger and the i-th AND gate, where i is a positive integer; The first input end of the i-th XOR gate serves as the first input end of the i-th counting unit, the second input end of the i-th XOR gate is connected to the output end of the i-th trigger, and the output end of the i-th XOR gate is connected to the input end of the i-th trigger; The output end of the i-th trigger serves as the first counting signal output end of the i-th stage counting unit, and the inverting output end of the i-th trigger serves as the second counting signal output end of the i-th stage counting unit; The first input end of the i-th AND gate is connected to the first input end of the i-th counting unit, the second input end of the i-th AND gate is connected to the output end of the i-th trigger, and the output end of the i-th AND gate serves as the first output end of the i-th counting unit.

5. The signal generating circuit according to claim 1, wherein: The counting unit of the n+1th stage includes an n+1th XOR gate and an n+1th trigger; The first input end of the n+1th XOR gate serves as the first input end of the n+1th level counting unit, the second input end of the n+1th XOR gate is connected to the output end of the n+1th trigger, the output end of the n+1th XOR gate is connected to the input end of the n+1th trigger, and the output end of the n+1th trigger serves as the first output end of the n+1th level counting unit.

6. The signal generating circuit according to any one of claims 1 to 5, characterized in that: m=3, and each of the selectors in the counting units of the first to third stages is configured as follows: When the first selection signal input terminal receives a step selection signal, the signal received by the step receiving terminal is selected and output; when the first selection signal input terminal receives a jump selection signal, the signal received by the jump receiving terminal is selected and output.

7. The signal generating circuit according to any one of claims 1 to 5, characterized in that: The signal generating circuit also includes a selection circuit, which includes a second selection signal input terminal. The selection circuit is configured to output the counting signals output by the 1st to nth level counting units in ascending or descending order based on the selection signal received by the second selection signal input terminal.

8. The signal generating circuit according to claim 7, wherein: The selection circuit includes n second selectors, each of which includes an ascending order receiving terminal, a descending order receiving terminal, and a second selection signal input terminal; The ascending order receiving end of the i-th second selector is connected to the first counting signal output end corresponding to the i-th counting unit, and the descending order receiving end of the i-th second selector is connected to the second counting signal output end corresponding to the i-th counting unit; wherein, i∈{1, 2, 3,…, n}.

9. The signal generating circuit according to claim 8, wherein: The signal generating circuit is applied to a memory; The signal generating circuit is configured to: based on the selection signal received by the first selection signal input terminal and the selection signal received by the second selection signal input terminal, select and output the counting signals output by the counting units of the 1st to nth levels as the row address addressing signal or the column address addressing signal of the memory.

10. A test circuit, characterized in that: Applied to memory built-in self-test, the test circuit comprises the signal generating circuit according to claims 1-8; The counting signal output by the signal generating circuit is used as an address signal for the memory built-in self-test.

11. A memory, characterized in that: comprising the test circuit as claimed in claim 10.

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