Memory test module, memory chip, memory chip test system and method

Abstract

The present invention provides a memory test module, a memory chip, a memory chip test system and a method. By coupling a corresponding input / output interface and a parameter register through the memory test module, it is possible to input the basic electrical parameters required for testing the memory chip before leaving the factory through the input / output interface. After leaving the factory, the basic electrical parameters required for testing can be input through the input / output interface as needed, or obtained from the parameter register. Thus, the test requirements of both the producer before leaving the factory and the user after leaving the factory are compatible. Moreover, when the memory test module is integrated into the package of the memory chip, during testing, only the probes need to be inserted into the input / output interface, and the mass testing of a large number of memory die cores in the memory chip and the batch reading of test results can be achieved through the memory test module. Compared with the existing memory chip, it has fewer test pins, reduces the test cost, and greatly improves the test efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a memory test module, a memory chip, a memory chip test system, and a method thereof. Background Art

[0002] Memories, especially dynamic random access memory (DRAM) chips, are widely used in various electronic devices such as mobile phones, servers, personal computers (PCs), and smart TVs (TVs). As the amount of data that these electronic devices need to process increases, the demand for the storage capacity of memory chips is also continuously expanding.

[0003] Therefore, currently, several memory dies are usually packaged together through packaging technology to form a required large-capacity memory chip. Before leaving the factory, the producer of the memory chip will perform a memory function test to ensure that the memory chip can be used normally after leaving the factory.

[0004] The general process of the function test of a memory chip is as follows: Place the memory chip (usually at the wafer level) on a test bench, use a probe card to pierce the pins of each memory die of the memory chip, and then send instructions one by one to all addresses inside each memory die to perform write and read operations. Then, compare whether the written data and the read data are consistent, so as to check whether there are problems such as poor signals or bad blocks in the internal storage array blocks (BANKS) of each memory, such as DRAM dies.

[0005] As the capacity of memory chips increases day by day, the requirements for testing become more and more stringent. However, the existing memory chip function test methods usually perform tests before the memory chips leave the factory. In fact, after the memory chips leave the factory, users also have the need for memory function tests, and the existing memory chip function test methods cannot yet be compatible with the test requirements of both users and producers. Summary of the Invention

[0006] An object of the present invention is to provide a memory test module, a memory chip, a memory chip test system, and a method thereof, which can be compatible with the test requirements of both users and producers of memory chips.

[0007] To achieve the above object, the present invention provides a memory test module, which is coupled to an input / output interface, a parameter register, and each memory die of a memory chip. The parameter register is used to store the basic electrical parameters required for testing after the memory chip leaves the factory. Among them,

[0008] The memory test module is used to control the power supply and test management system of at least one corresponding memory die according to the basic electrical parameters received by the input / output interface before the memory chip leaves the factory, and further perform individual or batch testing on the at least one memory die according to the test instructions received by the input / output interface. Also,

[0009] after the memory chip leaves the factory, control the power supply and test management system of at least one corresponding memory die according to the basic electrical parameters received by the input / output interface or the basic electrical parameters pre-stored in the parameter register, and further perform individual or batch testing on the at least one memory die according to the test instructions received by the input / output interface.

[0010] Optionally, the memory test module includes:

[0011] An instruction decoding circuit, coupled to the input / output interface, and used to decode the basic electrical parameters and the test instructions received by the input / output interface;

[0012] A function register circuit, coupled to the instruction decoding circuit, and used to temporarily store the decoding result of the instruction decoding circuit, and perform individual or batch testing on the at least one memory die according to the test instruction in the decoding result;

[0013] A parameter configuration circuit, coupled to the function register circuit and the parameter register, and used to control the power supply and test management system of at least one corresponding memory die according to the basic electrical parameters in the decoding result temporarily stored by the function register circuit or the basic electrical parameters pre-stored in the parameter register;

[0014] An output control circuit, coupled to the input / output interface, the function register circuit, and each memory die, and used to output the corresponding test result to the input / output interface according to the corresponding information in the decoding result temporarily stored by the function register circuit.

[0015] Optionally, the output control circuit includes an output OR logic circuit coupled to the function register circuit, which is used to control the number of memory dies outputting the test result according to the corresponding information in the decoding result temporarily stored by the function register circuit when performing batch testing on at least two memory dies in the memory chip, and output the corresponding test result in a serial or parallel manner.

[0016] Optionally, the functional register circuit further includes an OR logic control circuit for controlling the number of memory dice to be batch-tested according to the corresponding information in the temporarily stored decoding result when batch-testing at least two memory dice in the memory chip.

[0017] Optionally, the corresponding information in the decoding result obtained by the instruction decoding circuit includes an address flag bit information and a batch information. The address flag bit information is used to distinguish whether to control the functional register circuit or the power supply and test management system of the memory die, and the batch information is used to distinguish which one or which several memory dice's power supply and test management system need to be controlled.

[0018] Optionally, the power supply and test management system is provided with a one-time programmable storage unit and its corresponding latch circuit. The functional register circuit is further configured to repeatedly write different groups of basic electrical parameters into the latch circuit according to the temporarily stored decoding result during the pre-factory test of the memory chip. The latch circuit writes the best group of basic electrical parameters among the different groups of basic electrical parameters into the one-time programmable storage unit for storage; the one-time programmable storage unit is further configured to download the stored basic electrical parameters to the latch circuit for use by the power supply and test management system when the memory chip is used after leaving the factory.

[0019] Optionally, the one-time programmable storage unit is provided with an enable bit, and the enable bit is used to control the latch circuit to store the basic electrical parameters sent by the memory test module or download the basic electrical parameters stored in the one-time programmable storage unit for use by the power supply and test management system.

[0020] Optionally, the output control circuit is further configured to output whether the current state of the corresponding memory die is idle or not.

[0021] Optionally, at least one of the memory test module, the input / output interface, and the parameter register is integrated in the memory chip and packaged together with the memory die through wafer bonding; or, the memory test module is independently manufactured from the memory chip and is arranged on the same circuit board together with the memory chip.

[0022] Based on the same inventive concept, the present invention further provides a memory chip, which includes at least one memory die and the memory test module as described in the present invention, and all the memory dice and the memory test module are integrated in the same chip-level or wafer-level package.

[0023] Based on the same inventive concept, the present invention further provides a memory chip testing system, which includes a memory chip and the memory testing module as described in the present invention. At least one memory die is integrated in the package of the memory chip, and the memory testing module is disposed outside the package of the memory chip and is located on the same circuit board as the memory chip.

[0024] Based on the same inventive concept, the present invention further provides a method for testing a memory chip, which includes:

[0025] During the testing stage before the memory chip leaves the factory or during the testing stage after the memory chip leaves the factory, providing the memory chip as described in the present invention or the memory chip testing system as described in the present invention;

[0026] If it is during the testing stage before the memory chip leaves the factory, connect the test probes of the test machine to the input / output interface of the memory chip, input test instructions and basic electrical parameters to the memory testing module coupled to the input / output interface, and test at least one memory die of the memory chip and return corresponding test results;

[0027] If it is during the testing stage after the memory chip leaves the factory, control the power supply and test management system of the corresponding at least one memory die according to the basic electrical parameters received through the input / output interface or the basic electrical parameters pre-stored in the parameter register, and further perform individual testing or batch testing on the at least one memory die according to the test instructions received through the input / output interface.

[0028] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0029] 1. By coupling the corresponding input / output interface and parameter register through the memory testing module, the basic electrical parameters required for pre-factory testing of the memory chip can be input through the input / output interface, and the basic electrical parameters required for post-factory testing can be input through the input / output interface as needed or obtained from the parameter register, thereby simultaneously accommodating the testing requirements of producers before factory and users after factory.

[0030] 2. During testing, only by inserting the probes into the input / output interface can communication between a large number of memory dies and the test machine be achieved. Compared with existing memory chips, there are fewer test pins, reducing the testing cost.

[0031] 3. The test machine can batch test a large number of memory dies in the memory chip through the memory testing module, and batch read the test results of multiple memory testing modules in the memory chip, greatly improving the testing efficiency.

[0032] 4. The memory test module can control the number of memory dice in batch testing in the memory chip and the number of memory dice for which test results need to be output, so as to achieve the customization of personalized testing. Description of the Drawings

[0033] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0034] Figure 1 is a schematic diagram of the internal system architecture of the memory test module according to an embodiment of the present invention and a schematic diagram of its connection with the input / output interface, parameter register, and memory dice.

[0035] Figure 2 is a schematic diagram of the internal system architecture of the memory chip according to an embodiment of the present invention and a schematic diagram of its connection with the test machine during testing.

[0036] Figure 3 is a schematic diagram of the architecture of the memory chip and the memory chip test system according to another embodiment of the present invention and a schematic diagram of its connection with the test machine during testing.

[0037] Figure 4 is a schematic diagram of the architecture of the memory chip and the memory chip test system according to still another embodiment of the present invention and a schematic diagram of its connection with the test machine during testing. Detailed Embodiments

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to specify the presence of the stated features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0039] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] Please refer to Figure 1 , an embodiment of the present invention provides a DRAM test module 10, which is coupled to the corresponding input / output interface (GPIO) 12, parameter register (logic register) 11, and each DRAM die D1-Dn of the DRAM chip. Among them, the parameter register 11 is used to store the basic electrical parameters required for testing after the DRAM chip leaves the factory, and the input / output interface 12 is used to receive test instructions or test instructions and basic electrical parameters when testing the DRAM chip. It should be noted that the embodiments of the specification take DRAM as an example of the memory, but the present invention is not limited thereto. The memory test module, memory chip, memory chip test system, and memory chip test method of the present invention can also be applied to other types of memories, such as pseudo-static random access memory PSRAM, flash memory Flash, etc.

[0041] The DRAM test module 10 of this embodiment is used to control the power supply and test management system PWR / TEST sys of at least one DRAM die D1 - Dn among the DRAM dies before the DRAM chip leaves the factory, according to the basic electrical parameters received by the input / output interface 11, and further perform individual tests or batch tests on at least one DRAM die (i.e., the DRAM die controlled by the power supply and test management system PWR / TEST sys) according to the test instructions input by the producer of the DRAM chip through the input / output interface GPIO. Also, after the DRAM chip leaves the factory, it controls the power supply and test management system PWR / TEST sys of at least one DRAM die D1 - Dn among the DRAM dies according to the basic electrical parameters input by the user through the input / output port GPIO or the basic electrical parameters pre - stored in the parameter register, and further performs individual tests or batch tests on at least one DRAM die (i.e., the DRAM die controlled by the power supply and test management system PWR / TEST sys) according to the test instructions input by the user through the input / output port GPIO.

[0042] Thus, through the connection of the DRAM test module 10 with the parameter register 11 and the input / output port GPIO, it can be compatible with the test requirements of both the users after the DRAM chip leaves the factory and the producers before the DRAM chip leaves the factory.

[0043] The DRAM test module 10 includes an instruction decoding circuit 101, a function register circuit 102, a parameter configuration circuit 104, and an output control circuit 103.

[0044] The instruction decoding circuit 101 is coupled to the input / output interface GPIO and is used to decode the basic electrical parameters and test instructions received by the input / output interface GPIO.

[0045] The function register circuit 102 is coupled to the instruction decoding circuit 101, the parameter configuration circuit 104, the output control circuit 103, and the DRAM dies D1 - Dn, and is used to temporarily store the decoding result of the instruction decoding circuit 101, and perform individual tests or batch tests on at least one DRAM die among the DRAM dies D1 - Dn according to the corresponding test instructions in the decoding result of the instruction decoding circuit 101.

[0046] The parameter configuration circuit 104 is coupled to the function register circuit 102 and the parameter register 11, and is used to control the power supply and test management system PWR / TEST sys of at least one DRAM die among the DRAM dies D1 - Dn according to the basic electrical parameters in the decoding result temporarily stored by the function register circuit 102 or the basic electrical parameters pre - stored in the parameter register 11.

[0047] The output control circuit 103 is coupled to the input / output interface GPIO, the function register circuit 102, and the DRAM die chips D1 to Dn, and is configured to feedback the test results corresponding to the respective test instructions to the input / output interface GPIO according to the corresponding information in the decoding results temporarily stored in the function register circuit 102. Optionally, the instructions received by the input / output interface GPIO further include instructions for reading whether the corresponding DRAM die chips in the DRAM chip are idle, and thus the output control circuit 103 can further output whether the current states of the corresponding DRAM die chips are idle.

[0048] In this embodiment, the decoding results obtained after decoding by the instruction decoding circuit 101 will include the address flag bit information (not shown) and the batch information (not shown) of the corresponding information. The address flag bit information is used to distinguish whether to control the function register circuit 102 or the power supply and test management system PWR / TESTsys of the corresponding DRAM die chips in the DRAM die chips D1 to Dn, and the batch information is used to distinguish which one or several DRAM die chips in the DRAM die chips D1 to Dn need to be controlled for the power supply and test management system PWR / TEST sys. Optionally, the batch information can modify the address specified bit in the function register circuit 102, so as to control the number of DRAM die chips for batch testing.

[0049] In this case, different basic electrical parameters can be configured for different DRAM die chips, so as to separately control the power supply and test management system PWR / TEST sys of a certain DRAM die chip, thereby realizing the one-by-one or individual test of the DRAM die chips, or simultaneously controlling the power supply and test management systems of multiple DRAM die chips to realize the batch testing of multiple DRAM die chips.

[0050] It should be understood that the instruction decoding circuit 101, the function register circuit 102, the parameter configuration circuit 104, and the output control circuit 103 can be implemented by any suitable circuit design respectively. For example, the parameter configuration circuit 104 can be implemented by at least two multiplexers, and it can also select the basic electrical parameters from the function register circuit 102 and the basic electrical parameters from the parameter register 11 to configure the power supply and test management system PWR / TESTsys of the DRAM die. For another example, the function register circuit 102 can include a function register (not shown) and a test controller circuit (not shown), etc. Optionally, the function register circuit 102 further includes an OR logic control circuit (not shown, for example, a logical combination of multiple OR gates), and this OR logic circuit is coupled to the DRAM dies D1 to Dn. When batch testing at least two of the DRAM dies D1 to Dn, according to the corresponding information in the decoded result temporarily stored in the function register circuit 102, it connects the corresponding DRAM dies, thereby controlling the number of DRAM dies for batch testing.

[0051] Among them, the basic electrical parameters sent to the power supply and test management system PWR / TEST sys of the DRAM die can be the basic electrical parameters pre-stored in the parameter register 11 (including the modified basic electrical parameters in the parameter register 11), or can be sent by the producer of the DRAM chip to the cache in the function register circuit 102 through the input / output interface GPIO.

[0052] Optionally, an instruction can be sent through the input / output interface GPIO to determine whether to modify the corresponding test flag bit information in the function register circuit 102. Thus, the parameter configuration circuit 104 can determine whether to select the basic electrical parameters in the parameter register 11 or the basic electrical parameters cached in the function register circuit 102 according to this flag bit information.

[0053] Optionally, the output control circuit 103 includes an output OR logic circuit (not shown, for example, a logical combination of multiple OR gates), and this output OR logic circuit is coupled to the function register circuit 102. When batch testing at least two DRAM dies in the DRAM chip, this output OR logic circuit controls the number of DRAM dies for outputting test results according to the corresponding information in the decoded result temporarily stored in the function register circuit 102, and outputs the corresponding test results in a serial or parallel manner. Thus, the test results are read out one by one or in batches.

[0054] It should be noted that, since the number of DRAM dies for batch testing in the DRAM chip can be controlled by the OR logic control circuit in the functional register circuit 102, and the number of DRAM dies for which test results need to be output in the DRAM chip can be controlled by the output OR logic circuit of the output control circuit 103, the DRAM test module 10 can provide customization of the number of DRAM dies for simultaneous testing and the number of test results for viewing for the user, thereby realizing the customization of personalized testing.

[0055] Optionally, a one-time programmable storage unit efuse (not shown) and a latch circuit efuse latch corresponding to the efuse are provided in the power supply and test management system of each DRAM die. The one-time programmable storage unit efuse is only writeable and not erasable, and the data remains after power-off. The latch circuit efuse latch is a set of latches corresponding to the one-time programmable storage unit efuse, which is writeable and erasable, and the data will be lost after power-off. During the pre-factory test of the DRAM chip, different combinations of basic electrical parameters can be repeatedly written into the DRAM test module 10 through the GPIO (General-Purpose Input / Output). The functional register circuit 102 of the DRAM test module 10 will program the corresponding combination of basic electrical parameters into the latch circuit efuse latch according to the decoded results temporarily stored in each test, thereby realizing repeated testing of each DRAM die in the DRAM chip. After repeated testing, the most suitable set of basic electrical parameters can be obtained. At this time, the best (i.e., the most suitable) set of basic electrical parameters can be programmed into the one-time programmable storage unit efuse for storage through the latch circuit efuse latch. When the DRAM chip is used by the user after leaving the factory, only by downloading the best (i.e., the most suitable) set of basic electrical parameters stored in the one-time programmable storage unit efuse to the latch circuit efuse latch, it can be used by the power supply and test management system PWR / TEST sys of each DRAM die.

[0056] Obviously, before leaving the factory, the latch circuit efuse latch stores the basic electrical parameters sent by the functional register circuit 102 of the DRAM test module. After leaving the factory, according to user needs, the basic electrical parameters stored in the latch circuit efuse latch may be the basic electrical parameters sent by the input / output interface GPIO through the functional register circuit 102 of the DRAM test module, or may be the basic electrical parameters downloaded from the one-time programmable storage unit efuse. Based on this, an enable bit (not shown) may be provided in the one-time programmable storage unit efuse, and this enable bit is used to control the latch circuit efuse latch to store the basic electrical parameters sent by the DRAM test module 10 or download the basic electrical parameters stored in the efuse for use by the power supply and test management system PWR / TEST sys of each DRAM die.

[0057] In this embodiment, please refer to Figure 1 and Figure 2, the DRAM test module 10 and each DRAM die in the DRAM chip can be packaged together through wafer bonding, such as through the wafer bonding method of Hybrid Bonding, and thus integrated together in the package of the DRAM chip. At this time, the DRAM chip can be provided with a standby pin HRSTB, a clock pin CLK_T, a mode pin TMODE, a chip select pin CS, a data input pin DIN, a data strobe pin DQS, a data output pin DOUT, a status read pin TDOUT, and a trim pin LR_TRIM, and these pins can all be set on the side where the DRAM test module 10 is coupled to the input / output interface 12 and the parameter register 11. Among them, the standby pin HRSTB can be used to control the DRAM chip integrated with the DRAM test module 10 and the DRAM die to enter the standby mode or exit the standby mode. The clock pin CLK_T is used to provide a clock signal to the DRAM chip to achieve clock control of the DRAM chip. The mode pin TMODE is used to control the mode of the DRAM chip, such as whether it is the producer test mode or the user test mode. The chip select pin CS enables read / write operations on the DRAM chip. When the data input pin DIN is valid, it is used to write data to the DRAM chip. The chip select pin CS and the data input pin DIN are both coupled to the input / output interface GPIO and the instruction decoding circuit 101 of the DRAM test module 10, so as to cooperate with each other to input the test instructions and basic electrical parameters received by the input / output interface GPIO into the instruction decoding circuit 101 of the DRAM test module 10. The data strobe pin DQS, the data output pin DOUT, and the status read pin TDOUT are all coupled to the input / output interface GPIO and the output control circuit 103 of the DRAM test module 10. And through the cooperation of the data strobe pin DQS and the data output pin DOUT, the data of the corresponding DRAM die can be output, and the status of the corresponding DRAM die, that is, whether it is in the idle state or the busy state, can be obtained through the status read pin TDOUT. The trim pin LR_TRIM is coupled to the parameter register 11 and the parameter configuration circuit 104 of the DRAM test module 10, and is used to provide the basic electrical parameters of the parameter register 11 to the parameter configuration circuit 104 according to the test requirements.

[0058] Of course, in another example of the present invention, please refer to Figure 3 , the DRAM test module 10 can also be integrated with the input / output interface 12 and the parameter register 11 in the DRAM chip and packaged together with each DRAM die in the DRAM chip through wafer bonding. At this time, the DRAM test module 10, the input / output interface 12, and the parameter register 11 are all integrated with each DRAM die D1~Dn in the DRAM chip in the package 4 of the DRAM chip.

[0059] Of course, in another example of the present invention, please refer to Figure 4 , the DRAM test module 10, the input / output interface 12, and the parameter register 11 are all manufactured independently of the individual DRAM die D1-Dn of the DRAM chip. At this time, the individual DRAM die D1-Dn are integrated in the package 4 of the DRAM chip, and the DRAM test module 10, the input / output interface 12, and the parameter register 11 are disposed on the same circuit board 5 together with the package of the DRAM chip.

[0060] It should be understood that for the test requirements of large-capacity DRAM chips, it is more advantageous to integrate the DRAM test module 10 with each DRAM die in the same package to form a DRAM chip, which can reduce the pins of the DRAM chip and simplify the test cost. In this case, the DRAM test module 10 and the individual DRAM die D1-Dn can be electrically connected through a hybrid bonding structure.

[0061] Based on Figure 2 and Figure 3 shown above, an embodiment of the present invention further provides a DRAM chip, which includes at least one DRAM die D1-Dn and the DRAM test module 10 as described in the present invention, and all the DRAM die D1-Dn and the DRAM test module 10 are integrated in the same chip-level or wafer-level package 4.

[0062] In this case, when the DRAM test module 10 of the present invention tests the corresponding DRAM chip, only the probes of the probe card 2 need to be inserted into the input / output interface GPIO of the DRAM test module 10 to enable the DRAM test module 10 to communicate with the test machine 3. The test machine 3 can then select different DRAM die for individual testing or select multiple DRAM die for rapid batch testing through the address IDs assigned to each DRAM die D1-Dn and the memory array blocks BANK inside each DRAM die by the DRAM chip, which can greatly improve the test efficiency.

[0063] Based on Figure 4 shown above, another embodiment of the present invention further provides a memory chip test system, which includes a DRAM chip and the DRAM test module 10 as described in the present invention. At least one DRAM die D1-Dn is integrated in the package 4 of the DRAM chip, and the DRAM test module 10 is disposed outside the package 4 of the DRAM chip and is located on the same circuit board 5 as the DRAM chip.

[0064] Figure 4The architecture shown can also be applied to the scenario of CP testing for DRAM wafers. In this case, the package body 4 of the DRAM chip is replaced with a DRAM wafer. When wafer testing several DRAM dies on the entire DRAM wafer 4, that is, during CP (Chip Probing) testing, different from the prior art method of placing the DRAM wafer 4 on the machine table and using probes to pierce the pins of each DRAM die one by one for testing, when using the technical solution of the present invention, it is only necessary to pierce the probes on the pins of the DRAM test module 10 to communicate with the test machine table 3. The test machine table 3 can select different DRAM dies through the pre-set IDs of each DRAM die D0 - Dn to perform rapid batch testing of a large number of DARM dies, which can greatly improve the testing efficiency.

[0065] Based on this, an embodiment of the present invention further provides a DRAM chip testing method, which is applied to the testing stage before the DRAM chip leaves the factory. This testing stage can be the final test (F / T) before the DRAM chip leaves the factory or the wafer testing (CP testing) of the DRAM die before it leaves the wafer fab. It should be noted that if CP testing is performed on multiple DRAM dies on the same wafer, then Figure 4 the DRAM chip 4 should be replaced with a DRAM wafer (wafer) 4. It is mainly to perform functional testing on the DRAM chip, send instructions for writing and reading one by one or in batches to all addresses inside each DRAM die, and then compare whether the written data and the read data are consistent, so as to check whether there are problems such as poor signals or bad blocks in the internal storage array blocks BANK of each DRAM die. Please refer to Figures 1 to 4 For this, the process of this testing method includes: First, the producer provides a DRAM chip as described in the present invention or a memory chip testing system as described in the present invention; then, connect the test probes of the test machine table 3 (i.e., the probes on the probe card 2) to the input / output interface GPIO of the DRAM chip or the memory chip testing system, input test instructions and basic electrical parameters to the DRAM test module 10 coupled to the input / output interface GPIO, and test at least one DRAM die of the DRAM chip according to the test instructions and basic electrical parameters, and further return the corresponding test results to the test machine table through the input / output interface GPIO.

[0066] In addition, another embodiment of the present invention further provides a DRAM chip testing method, which is applied to the testing stage after the DRAM chip leaves the factory. Please refer to Figures 1 to 4, the process of this test method includes: First, the user of the DRAM chip provides a DRAM chip as described in the present invention or a memory chip test system as described in the present invention; Next, connect the test probes of the test machine 3 (i.e., the probes on the probe card 2) to the input / output interface GPIO of the DRAM chip or the memory chip test system, and input test instructions to the DRAM test module 10 coupled to the input / output interface GPIO, or not only input test instructions, but also input basic electrical parameters; Then, the DRAM test module 10 selects the basic electrical parameters received by the input / output interface GPIO according to the input test instructions or selects the basic electrical parameters pre-stored in the parameter register 11 to control the power supply and test management system of at least one corresponding DRAM die in the DRAM chip, and further performs one-by-one testing or batch testing on at least one DRAM die whose power supply and test management system are controlled according to the test instructions received by the input / output interface GPIO, and further returns the corresponding test results to the test machine through the input / output interface GPIO.

[0067] It can be seen that, in the technical solution of the present invention, by coupling the corresponding input / output interface and parameter register with the DRAM test module, the basic electrical parameters required for testing the DRAM chip before leaving the factory can be input through the input / output interface, and the basic electrical parameters required for testing after leaving the factory can be input through the input / output interface as needed, or can be obtained from the parameter register, thereby simultaneously meeting the test requirements of the producer before leaving the factory and the user after leaving the factory. Further, when the DRAM test module is integrated in the package of the DRAM chip, during testing, only need to insert the probes on the input / output interface, and the communication between the corresponding DRAM die and the test machine can be achieved through the DRAM test module. Compared with the existing DRAM chip, it has fewer test pins, reducing the test cost. In addition, it can also achieve batch testing of a large number of DRAM dies in the DRAM chip and batch reading of test results, or achieve batch testing of a large number of DRAM dies on the same wafer and batch reading of test results, greatly improving the test efficiency.

[0068] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A memory test module, characterized in that, each memory die coupled to the input / output interface, the parameter register, and the memory chip, and the parameter register is used to store the basic electrical parameters required for testing after the memory chip leaves the factory; wherein, the memory test module is used to, before the memory chip leaves the factory, control the power supply and test management system of the corresponding at least one memory die according to the basic electrical parameters received by the input / output interface, and further perform individual or batch testing on the at least one memory die according to the test instructions received by the input / output interface, and, after the memory chip leaves the factory, control the power supply and test management system of the corresponding at least one memory die according to the basic electrical parameters received by the input / output interface or the basic electrical parameters pre-stored in the parameter register, and further perform individual or batch testing on the at least one memory die according to the test instructions received by the input / output interface.

2. The memory test module according to claim 1, characterized in that, the memory test module includes: an instruction decoding circuit, coupled to the input / output interface, and used to decode the basic electrical parameters and the test instructions received by the input / output interface; a function register circuit, coupled to the instruction decoding circuit, and used to temporarily store the decoding result of the instruction decoding circuit, and perform individual or batch testing on the at least one memory die according to the test instruction in the decoding result; a parameter configuration circuit, coupled to the function register circuit and the parameter register, and used to control the power supply and test management system of the corresponding at least one memory die according to the basic electrical parameters in the decoding result temporarily stored by the function register circuit or the basic electrical parameters pre-stored in the parameter register; an output control circuit, coupled to the input / output interface, the function register circuit, and each memory die, and used to output the corresponding test result to the input / output interface according to the corresponding information in the decoding result temporarily stored by the function register circuit.

3. The memory test module according to claim 2, characterized in that, the output control circuit includes an output OR logic circuit coupled to the function register circuit, and is used to, when performing batch testing on at least two memory dies in the memory chip, control the number of memory dies outputting the test result according to the corresponding information in the decoding result temporarily stored by the function register circuit, and output the corresponding test result in a serial or parallel manner.

4. The memory test module according to claim 2, characterized in that, the function register circuit further includes an OR logic control circuit, and is used to, when performing batch testing on at least two memory dies in the memory chip, control the number of memory dies undergoing batch testing according to the corresponding information in the temporarily stored decoding result.

5. The memory test module according to claim 2, characterized in that, The corresponding information in the decoding result obtained by the instruction decoding circuit includes address flag bit information and batch information. The address flag bit information is used to distinguish whether to control the function register circuit or the power supply and test management system of the memory die. The batch information is used to distinguish which one or which several memory die power supply and test management systems need to be controlled.

6. The memory test module according to claim 2, wherein, a one-time programmable storage unit and its corresponding latch circuit are provided in the power supply and test management system. The function register circuit is further configured to repeatedly write different groups of basic electrical parameters into the latch circuit according to the temporarily stored decoding result during the pre-factory test of the memory chip. The latch circuit writes the best group of basic electrical parameters among the different groups of basic electrical parameters into the one-time programmable storage unit for storage. The one-time programmable storage unit is further configured to download the stored basic electrical parameters to the latch circuit for use by the power supply and test management system when the memory chip is used after leaving the factory.

7. The memory test module according to claim 6, wherein, an enable bit is provided in the one-time programmable storage unit. The enable bit is used to control the latch circuit to store the basic electrical parameters sent by the memory test module or download the basic electrical parameters stored in the one-time programmable storage unit for use by the power supply and test management system.

8. The memory test module according to claim 3, wherein, the output control circuit is further configured to output whether the current state of the corresponding memory die is idle or not.

9. The memory test module according to any one of claims 1-8, wherein, at least one of the memory test module, the input / output interface, and the parameter register is integrated in the memory chip and packaged together with the memory die through wafer bonding; or, the memory test module is independently manufactured from the memory chip and is provided on the same circuit board as the memory chip.

10. A memory chip, wherein, comprises at least one memory die and the memory test module according to any one of claims 1-9, and all the memory dies and the memory test module are integrated in the same chip-level or wafer-level package.

11. A memory chip test system, wherein, comprises a memory chip and the memory test module according to any one of claims 1-9. At least one memory die is integrated in the package of the memory chip. The memory test module is provided outside the package of the memory chip and is located on the same circuit board as the memory chip.

12. A memory chip test method, wherein, comprises: providing the memory chip according to claim 10 or the memory chip test system according to claim 11 during the pre-factory test stage or the post-factory test stage of the memory chip; If it is in the test stage before the memory chip leaves the factory, the test probe of the test machine is connected to the memory chip or the input / output interface of the memory chip test system, test instructions and basic electrical parameters are input into the memory test module coupled to the input / output interface, and at least one memory die of the memory chip is tested and corresponding test results are returned; If it is in the test stage after the memory chip leaves the factory, according to the basic electrical parameters received by the input / output interface or the basic electrical parameters pre-stored in the parameter register, the power supply and test management system of the corresponding at least one memory die are controlled, and further, the at least one memory die is tested one by one or in batches according to the test instructions received by the input / output interface.

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