Internal power supply structure, semiconductor device, and internal power supply monitoring method

Abstract

The present disclosure relates to the field of semiconductor, and discloses an internal power supply structure, a semiconductor device and an internal power supply monitoring method. The internal power supply structure comprises a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad. The power supply generation circuit is coupled with the internal power supply wiring at an output end and is configured to generate an internal voltage; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit and is configured to transmit the internal voltage; and the internal power supply monitoring wiring is coupled with the pad and is configured to transmit the internal voltage to the pad when the first switch circuit is turned on. In this way, the internal voltage is led out to the pad when the first switch circuit is turned on, so as to facilitate monitoring of the internal voltage generated by the power supply generation circuit. When the first switch circuit is not turned on, the internal voltage is prevented from being transmitted to the internal power supply monitoring wiring, interference possibly caused by the internal power supply monitoring wiring is eliminated, and inaccurate internal voltage is avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to an internal power supply structure, a semiconductor device and an internal power supply monitoring method. BACKGROUND

[0002] In an integrated circuit, a power supply voltage may be abnormal due to a fault or a load, etc., so that the voltage received by an electronic device is abnormal, and thus the electronic device cannot work normally. Therefore, a voltage monitoring circuit for monitoring the power supply voltage is usually added in the integrated circuit to determine whether the voltage output by the power supply is abnormal. Generally, the coupling effect between the wire for transmitting the internal power supply signal and other wires may damage the power supply signal, which affects the accuracy of the monitoring result to some extent. SUMMARY

[0003] Therefore, the present disclosure provides an internal power supply structure, a semiconductor device and an internal power supply monitoring method to avoid the interference of the coupling effect of the wire on the process of monitoring the power supply signal.

[0004] The technical scheme of the present disclosure is implemented as follows:

[0005] The present disclosure provides an internal power supply structure, comprising: a power supply generation circuit, an internal power supply wire, a first switch circuit, an internal power supply monitoring wire and a pad; the output end of the power supply generation circuit is coupled with the internal power supply wire, and is used for generating an internal voltage; the internal power supply wire is coupled with the internal power supply monitoring wire through the first switch circuit, and is used for transmitting the internal voltage; the internal power supply monitoring wire is coupled with the pad, and is used for transmitting the internal voltage to the pad when the first switch circuit is turned on.

[0006] In the above scheme, the internal power supply wire and the internal power supply monitoring wire are arranged on the same layer.

[0007] In the above scheme, the internal power supply structure further comprises a second switch circuit; the second switch circuit is coupled with the internal power supply monitoring wire and the pad respectively, and is used for transmitting the internal voltage to the pad when turned on.

[0008] In the above scheme, the first switch circuit and the second switch circuit are both transmission gate circuits.

[0009] The present disclosure further provides a semiconductor device comprising the internal power supply structure in the above scheme.

[0010] In the above scheme, the semiconductor device comprises: a substrate and a signal wire arranged on a layer different from the internal power supply monitoring wire; the projection of the signal wire along the direction perpendicular to the substrate at least partially overlaps the projection of the internal power supply monitoring wire along the direction perpendicular to the substrate.

[0011] In the above solution, the semiconductor device further comprises: an internal power supply monitoring control circuit; the internal power supply monitoring control circuit is configured to turn on the first switch circuit when the semiconductor device is in an internal power supply monitoring mode; or turn off the first switch circuit when the semiconductor device is in a non-internal power supply monitoring mode.

[0012] In the above solution, the semiconductor device is a semiconductor memory.

[0013] In the above solution, the signal wiring is an address signal line, and the pad is a data input / output pad.

[0014] The internal power supply monitoring method provided by the embodiments of the present disclosure comprises: providing an internal power supply structure; the internal power supply structure comprises: a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring, and a pad; the output end of the power supply generation circuit is coupled with the internal power supply wiring; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit; the internal power supply monitoring wiring is coupled with the pad; an internal voltage is generated by the power supply generation circuit; the first switch circuit is turned on, and the internal voltage is transmitted to the pad through the internal power supply monitoring wiring.

[0015] In the above solution, the internal power supply structure further comprises a second switch circuit; the second switch circuit is coupled with the internal power supply monitoring wiring and the pad respectively; after the first switch circuit is turned on, the internal power supply monitoring method further comprises: turning on the second switch circuit, and transmitting the internal voltage to the pad.

[0016] In the embodiments of the present disclosure, the internal power supply structure comprises: a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring, and a pad. The power supply generation circuit, whose output end is coupled with the internal power supply wiring, is configured to generate an internal voltage; the internal power supply wiring, which is coupled with the internal power supply monitoring wiring through the first switch circuit, is configured to transmit the internal voltage; and the internal power supply monitoring wiring, which is coupled with the pad, is configured to transmit the internal voltage to the pad when the first switch circuit is turned on. In this way, the transmission process of the internal voltage can be controlled based on the on-off state of the first switch circuit; in the case that the first switch circuit is turned on, the internal voltage is led out to the pad through the internal power supply monitoring wiring, so as to facilitate the monitoring of the internal voltage generated by the power supply generation circuit. In the case that the first switch circuit is not turned on, the internal voltage can be prevented from being transmitted to the internal power supply monitoring wiring, so that the interference possibly caused by the internal power supply monitoring wiring can be eliminated, and the inaccuracy of the internal voltage can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 Structure diagram of the internal power supply structure provided by the embodiments of the present disclosure Figure 1 ;

[0018] Figure 2Structure diagram of internal power supply structure provided by the embodiment of the present disclosure Figure 2 ;

[0019] Figure 3 Circuit principle diagram of internal power supply structure provided by the embodiment of the present disclosure

[0020] Figure 4 Diagram of semiconductor device provided by the embodiment of the present disclosure Figure 1 ;

[0021] Figure 5 Layout diagram of semiconductor device provided by the embodiment of the present disclosure

[0022] Figure 6 Diagram of semiconductor device provided by the embodiment of the present disclosure Figure 2 ;

[0023] Figure 7 Structure diagram of semiconductor device provided by the embodiment of the present disclosure

[0024] Figure 8 Flow diagram of internal power supply detection method provided by the embodiment of the present disclosure DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the technical scheme of the present disclosure is further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0026] In the following description, “some embodiments” are related to a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0027] If similar descriptions of “first / second” appear in the application file, the following description is added, in the following description, the terms “first / second / third” related only distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that “first / second / third” can be interchanged with a specific order or sequence as allowed, so that the embodiment of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0029] Figure 1 is a structural schematic diagram of an optional internal power supply structure provided by an embodiment of the present disclosure. The internal power supply structure 100 comprises a power supply generation circuit 10, an internal power supply wiring 20, a first switch circuit 30, an internal power supply monitoring wiring 40 and a pad 50. The power supply generation circuit 10 is coupled with the internal power supply wiring 20 at an output end thereof, and is configured to generate an internal voltage. The internal power supply wiring 20 is coupled with the internal power supply monitoring wiring 40 through the first switch circuit 30, and is configured to transmit the internal voltage. The internal power supply monitoring wiring 40 is coupled with the pad 50, and is configured to transmit the internal voltage to the pad 50 when the first switch circuit 30 is turned on.

[0030] It should be noted that the internal voltage can be any voltage in an integrated circuit that needs to be monitored. For example, the internal voltage can be one or more of the voltage VBB and the voltage VKK.

[0031] It should also be noted that the internal power supply monitoring wiring 40 coupled with the pad 50 means that the internal power supply monitoring wiring 40 is directly connected to the pad 50 or indirectly connected to the pad 50 through other structures. Figure 1

[0032] In the embodiment of the present disclosure, continuing to refer to Figure 1 When the first switch circuit 30 is turned on, the internal voltage generated by the power supply generation circuit 10 can be transmitted to the internal power supply monitoring wiring 40 through the internal power supply wiring 20, and then transmitted to the pad 50. That is, the internal voltage is led out to the pad 50 when the first switch circuit 30 is turned on. Thus, the internal voltage generated by the power supply generation circuit 10 can be monitored by monitoring the parameter change of the pad 50.

[0033] In the embodiment of the present disclosure, continuing to refer to Figure 1 ​The internal power supply structure 100 can be arranged in a semiconductor device such as a memory, and the internal power supply monitoring wiring 40 can be arranged in a wiring layer of the semiconductor device. The internal power supply monitoring wiring 40 is usually long, and in the extension direction of the internal power supply monitoring wiring 40, a part of the internal power supply monitoring wiring 40 is likely to be parallel to other wirings, so that the internal power supply monitoring wiring 40 is likely to be coupled with other wirings in the wiring layer of the semiconductor device. That is, if a signal transmitted on other wirings in the semiconductor device changes, the signal transmitted on the internal power supply monitoring wiring 40 will be distorted. For example, if an internal voltage is transmitted to the internal power supply monitoring wiring 40, and if a signal transmitted on other wirings in the semiconductor device jumps, the internal voltage will be inaccurate. Therefore, the embodiment of the present disclosure introduces the first switch circuit 30 between the internal power supply wiring 20 and the internal power supply monitoring wiring 40, and then the internal power supply wiring 20 and the internal power supply monitoring wiring 40 can be disconnected by controlling the first switch circuit 30, so that the internal voltage generated by the power supply generation circuit 10 cannot be transmitted to the internal power supply monitoring wiring 40, and the internal voltage will not be disturbed by other wirings in the semiconductor device, thereby avoiding the inaccuracy of the internal voltage.

[0034] It can be understood that the embodiment of the present disclosure couples the internal power supply wiring with the internal power supply monitoring wiring through the first switch circuit. In this way, the transmission process of the internal voltage can be controlled based on the conduction state of the first switch circuit. When the first switch circuit is turned on, the internal voltage is led out to the pad through the internal power supply monitoring wiring, so as to monitor the internal voltage generated by the power supply generation circuit. When the first switch circuit is not turned on, the internal voltage cannot be transmitted to the internal power supply monitoring wiring, so that the interference caused by the internal power supply monitoring wiring can be eliminated, and the inaccuracy of the internal voltage can be avoided.

[0035] Figure 2 is a structure diagram of another optional internal power supply structure provided by the embodiment of the present disclosure.

[0036] In some other embodiments of the present disclosure, referring to Figure 2 The internal power supply structure 100 further includes a second switch circuit 60, and the second switch circuit 60 is coupled with the internal power supply monitoring wiring 40 and the pad 50 respectively, and is used for transmitting the internal voltage to the pad 50 when the second switch circuit 60 is turned on.

[0037] In the embodiment of the present disclosure, continuing to refer to Figure 2The pad 50 is usually connected with multiple wires, and corresponds to receiving multiple signals. For example, the pad 50 can be a data input / output pad (DQ PAD); the input / output pad receives signals such as data signals (DQ) in addition to internal voltages. In this way, in the case that the internal power monitoring wire 40 is directly connected to the pad 50, other signals (for example, data signals DQ) received by the pad 50 are transmitted to the internal power monitoring wire 40; and thus, the signals transmitted by other wires coupled with the internal power monitoring wire 40 are interfered by the data signals (DQ). Therefore, the embodiment of the present disclosure introduces a second switch circuit 60 between the internal power monitoring wire 40 and the pad 50; and then, the second switch circuit 60 can be controlled to disconnect the internal power monitoring wire 40 and the pad 50, so that other signals received by the pad 50 cannot be transmitted to the internal power monitoring wire 40. Thus, the internal power monitoring wire 40 and the wires having a coupling effect with the internal power monitoring wire 40 can be prevented from interfering with each other.

[0038] Figure 3 is a circuit principle schematic diagram of an optional internal power supply structure provided by the embodiment of the present disclosure. It should be noted that the first transistor MP1 and the third transistor MP2 can be PMOS (Positive channel Metal Oxide Semiconductor, PMOS) transistors; and the second transistor MN1 and the fourth transistor MN2 can be NMOS (Negative channel Metal Oxide Semiconductor, NMOS) transistors.

[0039] In some embodiments of the present disclosure, referring to Figure 3 The first switch circuit 30 and the second switch circuit 60 are both transmission gate circuits.

[0040] In the embodiment of the present disclosure, referring to Figure 3The transmission gate circuit forming the first switching circuit 30 includes a first transistor MP1 and a second transistor MN1. The sources of both the first transistor MP1 and the second transistor MN1 are connected to internal power supply wiring 20, and the drains of both transistors are connected to internal power monitoring wiring 40. The gate of the first transistor MP1 is connected to a first control signal terminal C', and the gate of the second transistor MN1 is connected to a second control signal terminal C. Thus, the first switching circuit 30 can be turned on or off by controlling the level of the signals input to the first control signal terminal C' and the second control signal terminal C. For example, transmitting a low-level control signal to the first control signal terminal C' of the first transistor MP1 and a high-level control signal to the second control signal terminal C of the second transistor MN1 turns the first switching circuit 30 off. Transmitting a high-level control signal to the first control signal terminal C' of the first transistor MP1 and a low-level control signal to the second control signal terminal C of the second transistor MN1 turns the first switching circuit 30 on.

[0041] In this embodiment of the disclosure, reference is made to Figure 3 The transmission gate circuit forming the second switching circuit 60 includes a first transistor MP2 and a fourth transistor MN2. The sources of both the third transistor MP2 and the fourth transistor MN2 are connected to the internal power monitoring wiring 40. The drains of both the third transistor MP2 and the fourth transistor MN2 are connected to the pad 50. The gate of the third transistor MP2 is connected to the third control signal terminal D', and the gate of the fourth transistor MN2 is connected to the fourth control signal terminal D. Thus, the conduction state of the second switching circuit 60 can be controlled by controlling the level of the signals input to the third control signal terminal D' and the fourth control signal terminal D of the second switching circuit 60. For example, transmitting a low-level control signal to the third control signal terminal D' of the third transistor MP2 and a high-level control signal to the fourth control signal terminal D of the fourth transistor MN2 will turn the second switching circuit 60 off. Transmitting a high-level control signal to the third control signal terminal D' of the third transistor MP2 and a low-level control signal to the second control signal terminal D of the fourth transistor MN2 will turn the second switching circuit 60 on.

[0042] In some embodiments of this disclosure, reference is made to Figure 2 The internal power supply wiring 20 and the internal power monitoring wiring 40 are arranged on the same floor.

[0043] Figure 4 The specific examples illustrate the positional relationships of the metal layers. Figure 5 and Figure 6 The specific example illustrates the positional relationship between signal cabling and internal power monitoring cabling. Figure 4 This is a side view. Figure 5 This is a top view. Figure 6The cross-sectional position is Figure 5 in A-A'.

[0044] It should be noted that, in the direction Z perpendicular to the substrate, the metal layers M0, M1 and M2 are arranged in sequence. Figure 5 and Figure 6 In the embodiment, VKKR and VBBR are both internal power supply monitoring wires, wherein VKKR is a wire for monitoring internal voltage VKK, and VBBR is a wire for monitoring internal voltage VBB. Figure 6 In the embodiment, A6 and BA0 are both signal wires; wherein A6 is a row-column shared address line; and BA0 is a wire for transmitting a bank selection signal. Figure 6 In the embodiment, the signal wire A6 is connected to the A6 PAD, and the signal wire BA0 is connected to the BA0 PAD.

[0045] In the embodiment, in combination with Figure 4 and Figure 6 , the internal power supply structure can be arranged in a semiconductor device such as a semiconductor memory. The semiconductor device usually includes multiple metal layers; for example, the semiconductor device includes metal layers M0, M1 and M2. The internal power supply wire and the internal power supply monitoring wire can be arranged in the same metal layer. For example, the internal power supply monitoring wire VKKR and the internal power supply monitoring wire VBBR are both arranged in the first metal layer M1, and the internal power supply wire can also be arranged in the first metal layer M1. The internal power supply wire and the internal power supply monitoring wire can both be connected to the first switch circuit through a contact structure or the like.

[0046] The embodiment of the present disclosure also provides a semiconductor device 200, which refers to Figure 7 , the semiconductor device 200 includes the internal power supply structure 100 in the present disclosure.

[0047] In some embodiments of the present disclosure, the semiconductor device includes: a substrate, and a signal wire arranged in a layer different from the internal power supply monitoring wire; a projection of the signal wire along a direction perpendicular to the substrate at least partially overlaps a projection of the internal power supply monitoring wire along the direction perpendicular to the substrate.

[0048] In the embodiment, in combination with Figure 5 and Figure 6 , the signal wire and the internal power supply monitoring wire are arranged in different layers. For example, the internal power supply monitoring wires (VKKR and VBBR) are both located in the first metal layer M1, and the signal wires (A6 and BA0) are both located in the second metal layer M2.

[0049] In the embodiment, in combination with Figure 5 and Figure 6The projection of the signal wiring along the direction Z perpendicular to the substrate at least partially overlaps the projection of the internal power supply monitoring wiring along the direction Z perpendicular to the substrate. For example, in the direction Z perpendicular to the substrate, the projection of the signal wiring A6 has an overlapping area S with the projection of the internal power supply monitoring wiring VBBR.

[0050] It should be noted that the positional relationship between the signal wiring BA0 and the internal power supply monitoring wiring (VKKR and VBBR) can be understood with reference to the signal wiring A6 in Figure 5 and Figure 6 Figure 6

[0051] In the embodiments of the present disclosure, in combination with Figure 5 and Figure 6 Compared with part of the wirings in the semiconductor device, the length of the internal power supply monitoring wiring is relatively long; for example, the length of the internal power supply monitoring wiring VKKR is 6829 um, and the length of the signal wiring A6 is 850 um. In the wiring structure of the semiconductor memory, the internal power supply monitoring wiring is likely to have a parallel section with the signal wiring, so that the internal power supply monitoring wiring has a coupling effect with part of the signal wiring.

[0052] It should be noted that the signal wiring and the internal power supply monitoring wiring can also be located in the same metal layer.

[0053] It should also be noted that during the working process of the semiconductor memory, the signal wiring will switch signals; the signal wiring A6 and the signal wiring BA0 are only used as examples and are not limited to these two signal wirings.

[0054] In the embodiments of the present disclosure, in combination with Figure 5 and Figure 6 In the extension direction of the internal power supply monitoring wiring (VKKR and VBBR), part of the section of the internal power supply monitoring wiring is parallel to the signal wiring (A6 and BA0), so that the internal power supply monitoring wiring has a coupling effect with the signal wiring. That is, the internal power supply monitoring wiring and the signal wiring have a parasitic capacitance. Further, in the case where the internal voltage is transmitted to the internal power supply monitoring wiring, if the signal transmitted on the signal wiring jumps and the parasitic capacitance discharges, the internal voltage will be inaccurate. Therefore, the first switch circuit and the second switch circuit are needed to disconnect the signal connected to the internal power supply monitoring wiring, so as to avoid the mutual interference between the internal power supply monitoring wiring and the signal wiring.

[0055] It should be noted that the first switch circuit and the second switch circuit can be understood with reference to the first switch circuit 1 and the second switch circuit 2 in Figure 5 ​​Generally, shielding lines are added on both sides of the signal lines to electrostatically shield the signal lines; thus, weakening the coupling effect between the signal lines and other lines and reducing the mutual interference between the signal lines and other lines. For example, shielding lines VSS are arranged on both sides of the signal lines (A6 and BA0); the shielding lines VSS are grounded; thus, the mutual interference between the adjacent signal lines (A6 and BA0) is weakened.

[0056] It should be further noted that, Figure 6 The metal layer M0 in Figure 4 is not shown

[0057] In the embodiments of the present disclosure, referring to Figure 6 , the shielding lines VSS arranged on both sides of the signal line A6 weaken the mutual interference between the signal line A6 and other lines to a certain extent. However, the signal line A6 and the lines arranged in different layers will still interfere with each other to a certain extent; for example, the signal line A6 can interfere with the lines arranged in the metal layers M0 and M1. When the semiconductor device is in the non-internal power supply monitoring mode, the internal voltage does not need to be monitored at this time, and therefore the first switch circuit and the second switch circuit can be disconnected, and the internal power supply monitoring line is not connected to any signal. That is, when the semiconductor device is in the non-internal power supply monitoring mode, since the internal power supply monitoring line is not connected to any signal, the internal power supply monitoring line can be used as a shielding line of the signal line. Thus, the coupling effect between the signal line and other lines is further weakened, and the mutual interference between the signal line and other lines arranged in different layers is avoided.

[0058] In some embodiments of the present disclosure, referring to Figure 7 , the semiconductor device 200 further includes an internal power supply monitoring control circuit 201. The internal power supply monitoring control circuit 201 is configured to turn on the first switch circuit 30 when the semiconductor device 200 is in the internal power supply monitoring mode, or turn off the first switch circuit 30 when the semiconductor device 200 is in the non-internal power supply monitoring mode.

[0059] In the embodiments of the present disclosure, in combination with Figure 5 and Figure 7 , the semiconductor device 200 can be a semiconductor memory. When the semiconductor device 200 is in the internal power supply monitoring mode, the signals transmitted by the signal lines (A6 and BA0) are not activated, and the internal power supply monitoring lines (VBBR and VKKR) will not have a coupling effect with the signal lines (A6 and BA0). The first switch circuit 30 and the second switch circuit 60 are turned on, and the internal voltage generated by the power supply generation circuit can be transmitted to the pad along the internal power supply line and the internal power supply monitoring line; thus, the internal voltage of the semiconductor device 200 can be monitored by detecting the parameter change of the pad.

[0060] In the embodiments of the present disclosure, in combination with Figure 5 and Figure 7 When the semiconductor device 200 is in the non-internal power supply monitoring mode, the signal wires (A6 and BA0) of the semiconductor device 200 transmit signals, and the pads transmit other signals, such as DQ signals. At this time, if the internal voltage is also transmitted to the internal power supply monitoring wires (VBBR and VKKR), the signals transmitted by the signal wires will affect the accuracy of the internal voltage. Therefore, the internal power supply structure 100 needs to introduce the first switch circuit 30 to disconnect the internal power supply wires and the internal power supply monitoring wires, so as to avoid the internal voltage from being transmitted to the internal power supply monitoring wires; and introduce the second switch circuit 60 to disconnect the internal power supply monitoring wires and the pads, so as to avoid the pads from receiving other signals transmitted to the internal power supply monitoring wires. Thus, the mutual interference between the internal power supply monitoring wires and the signal wires is avoided.

[0061] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 7 When the semiconductor device 200 is in the non-internal power supply monitoring mode, the internal power supply monitoring control circuit 201 can input a low-level control signal to the first control signal end C' of the first switch circuit 30 and input a high-level control signal to the second control signal end C of the first switch circuit 30, so as to close the first switch circuit 30; thus, the internal voltage generated by the power supply generation circuit 10 is prevented from being transmitted to the internal power supply monitoring wires 40. Alternatively, when the semiconductor device 200 is in the internal power supply monitoring mode, the internal power supply monitoring control circuit 201 can input a high-level control signal to the first control signal end C' of the first switch circuit 30 and input a low-level control signal to the second control signal end C of the first switch circuit 30, so as to turn on the first switch circuit 30; thus, the internal voltage generated by the power supply generation circuit 10 is transmitted to the internal power supply monitoring wires 40.

[0062] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 7 When the semiconductor device 200 is in the non-internal power supply monitoring mode, the internal power supply monitoring control circuit 201 can input a low-level control signal to the third control signal end D' of the second switch circuit 60 and input a high-level control signal to the fourth control signal end D of the second switch circuit 60, so as to close the second switch circuit 60; thus, the other signals received by the pads 50 are prevented from being transmitted to the internal power supply monitoring wires 40. Alternatively, when the semiconductor device 200 is in the internal power supply monitoring mode, the internal power supply monitoring control circuit 201 can input a high-level control signal to the third control signal end D' of the second switch circuit 60 and input a low-level control signal to the fourth control signal end D of the second switch circuit 60, so as to turn on the second switch circuit 60; thus, the internal voltage of the internal power supply monitoring wires 40 is transmitted to the pads 50.

[0063] In some embodiments of the present disclosure, referring to Figure 7 , the semiconductor device 200 is a semiconductor memory.

[0064] In embodiments of the present disclosure, the semiconductor device 200 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), etc.

[0065] In some embodiments of the present disclosure, the signal wiring can be an address signal line, and the pad can be a data input / output pad.

[0066] In embodiments of the present disclosure, referring to Figure 5 , when the semiconductor device is a semiconductor memory, the signal wiring can be an address signal line. The address signal line can be one or more of the row / column shared address lines in the semiconductor memory; for example, the address signal line is the row / column shared address line A6. The row / column shared address line A6 can be used to transmit a row address signal RAS, a column address signal CAS, etc. The address signal line can also be a gate signal wiring; for example, the address signal line is the gate signal wiring BA0. The gate signal wiring BA0 can be used to transmit a bank gate signal.

[0067] In embodiments of the present disclosure, referring to Figure 2 , the pad 50 can be a data input / output pad. When the semiconductor device is in an internal power supply monitoring mode, the pad 50 is used to transmit an internal voltage; when the semiconductor device is in a non-internal power supply monitoring mode, the pad 50 is used to transmit a data signal.

[0068] Figure 8 is an optional flowchart of an internal power supply monitoring method provided by embodiments of the present disclosure, which will be described in combination with the steps shown in Figure 8 .

[0069] It should be noted that Figure 8 the internal power supply monitoring method shown can be implemented by Figure 1 the example internal power supply structure.

[0070] S101, providing an internal power supply structure; the internal power supply structure includes: a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring, and a pad; an output end of the power supply generation circuit is coupled with the internal power supply wiring; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit; and the internal power supply monitoring wiring is coupled with the pad.

[0071] In the embodiment of the present disclosure, the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit, so that the conduction state of the first switch circuit can control the transmission process of the internal voltage.

[0072] S102, generating an internal voltage by a power supply circuit.

[0073] S103, turning on the first switch circuit, and transmitting the internal voltage to the pad through the internal power supply monitoring wiring.

[0074] In the embodiment of the present disclosure, in the case that the first switch circuit is turned on, the internal voltage can be led out to the pad, so as to monitor the internal voltage generated by the power supply circuit. In the case that the first switch circuit is not turned on, the internal voltage can be prevented from being transmitted to the internal power supply monitoring wiring, so as to eliminate the interference possibly caused by the internal power supply monitoring wiring. In this way, as long as the internal power supply monitoring wiring and the internal power supply wiring have a coupling effect, and the internal voltage is interfered, the first switch circuit can be introduced between the internal power supply monitoring wiring and the internal power supply wiring in the method of the embodiment of the present disclosure, and the internal power supply monitoring wiring and the internal power supply wiring are disconnected, so as to eliminate the interference of the jump signal on the internal voltage, and prevent the internal voltage from being inaccurate.

[0075] In some embodiments of the present disclosure, S103 can be implemented by S1031. Figure 8 S103 shown will be described in combination with S1031.

[0076] S1031, turning on the second switch circuit, and transmitting the internal voltage to the pad.

[0077] It should be noted that S1031 can be implemented by Figure 2 The internal power supply structure is implemented by an example.

[0078] In the embodiment of the present disclosure, the internal power supply structure further includes a second switch circuit, and the second switch circuit is coupled with the internal power supply monitoring wiring and the pad respectively. Therefore, after the first switch circuit is turned on, the second switch circuit also needs to be turned on, so as to transmit the internal voltage to the pad. In this way, the second switch circuit is introduced between the internal power supply monitoring wiring and the pad, and then the internal power supply monitoring wiring and the pad can be disconnected by controlling the second switch circuit, so that other signals received by the pad cannot be transmitted to the internal power supply monitoring wiring. Therefore, the internal power supply monitoring wiring and the wiring having a coupling effect with the internal power supply monitoring wiring can be prevented from interfering with each other.

[0079] In some embodiments of the present disclosure, the internal power supply wiring and the internal power supply monitoring wiring are arranged in the same layer.

[0080] In some embodiments of the present disclosure, the first switch circuit and the second switch circuit are both transmission gate circuits.

[0081] In some embodiments of the present disclosure, the internal power supply structure is arranged in a semiconductor device; the semiconductor device comprises a substrate and a signal wiring arranged in a layer different from the internal power supply monitoring wiring; a projection of the signal wiring along a direction perpendicular to the substrate at least partially overlaps a projection of the internal power supply monitoring wiring along a direction perpendicular to the substrate.

[0082] In some embodiments of the present disclosure, the semiconductor device further comprises an internal power supply monitoring control circuit; the internal power supply monitoring control circuit is configured to turn on the first switch circuit when the semiconductor device is in an internal power supply monitoring mode; or turn off the first switch circuit when the semiconductor device is in a non-internal power supply monitoring mode.

[0083] In some embodiments of the present disclosure, the semiconductor device is a semiconductor memory.

[0084] In some embodiments of the present disclosure, the signal wiring is an address signal line, and the pad is a data input / output pad.

[0085] It should be noted that, in this document, the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or devices that comprise a series of elements are not limited to those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element.

[0086] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments.

[0087] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An internal power supply structure, characterized by, The internal power supply structure comprises: a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad; the power supply generation circuit is coupled with the internal power supply wiring at an output end thereof, and is configured to generate an internal voltage; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit, and is configured to transmit the internal voltage; the internal power supply monitoring wiring is coupled with the pad, and is configured to transmit the internal voltage to the pad when the first switch circuit is turned on; the internal power supply structure further comprises a second switch circuit; the second switch circuit is coupled with the internal power supply monitoring wiring and the pad respectively, and is configured to transmit the internal voltage to the pad when the second switch circuit is turned on.

2. The internal power supply structure of claim 1, wherein, The internal power supply wiring and the internal power supply monitoring wiring are arranged on the same layer.

3. The internal power supply structure of claim 1, wherein, The first switch circuit and the second switch circuit are both transmission gate circuits.

4. A semiconductor device, characterized by, The semiconductor device comprises the internal power supply structure according to any one of claims 1 to 3.

5. The semiconductor device of claim 4, wherein, The semiconductor device further comprises a signal wiring arranged on a layer different from the internal power supply monitoring wiring; a projection of the signal wiring along a direction perpendicular to the substrate at least partially overlaps a projection of the internal power supply monitoring wiring along the direction perpendicular to the substrate.

6. The semiconductor device of claim 5, wherein, The semiconductor device further comprises an internal power supply monitoring control circuit; The internal power supply monitoring control circuit is configured to turn on the first switch circuit when the semiconductor device is in an internal power supply monitoring mode, or turn off the first switch circuit when the semiconductor device is in a non-internal power supply monitoring mode.

7. The semiconductor device of claim 6, wherein, The semiconductor device is a semiconductor memory.

8. The semiconductor device of claim 7, wherein, The signal wiring is an address signal line, and the pad is a data input / output pad.

9. An internal power monitoring method, characterized by, The internal power supply structure comprises: a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad; the output end of the power supply generation circuit is coupled with the internal power supply wiring; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit; and the internal power supply monitoring wiring is coupled with the pad; an internal voltage is generated by the power supply generation circuit; the first switch circuit is turned on, and the internal voltage is transmitted to the pad through the internal power supply monitoring wiring; the internal power supply structure further comprises a second switch circuit; and the second switch circuit is coupled with the internal power supply monitoring wiring and the pad respectively; after the first switch circuit is turned on, the internal power supply monitoring method further comprises: the second switch circuit is turned on, and the internal voltage is transmitted to the pad. ​

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