Method for preparing image sensor

Abstract

The present application relates to a method for preparing an image sensor, including: providing a substrate having a pixel area and a logic area on the substrate; forming a patterned mask layer on the substrate; etching the substrate to a first preset depth based on the patterned mask layer to form a first shallow groove located in the logic area and a second initial shallow groove located in the pixel area; forming an epitaxial layer on the surface of the second initial shallow groove, and the epitaxial layer reduces the depth of the second initial shallow groove from the first preset depth to the second preset depth to form a second shallow groove. The method for preparing the image sensor of the present application does not involve multiple etchings, and can keep the patterned mask layers of the logic area and the pixel area highly consistent, and can be completely removed later. At the same time, the process window of chemical mechanical polishing is increased, and a P-type selective epitaxial growth layer can also be performed in the pixel area, which can save the ion implantation process steps and the corresponding mask.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an image sensor. Background Art

[0002] With the development of semiconductor technology, a double shallow trench structure has appeared in traditional image sensors. The formation process of the double shallow trench structure includes: based on the patterned mask layer, etching the substrate to form two shallow trenches with a relatively shallow depth, then using a patterned photoresist to cover the shallow trench in the pixel area, and etching the shallow trench in the logic area for the second time to form a shallow trench with a relatively deep depth.

[0003] During the formation of the above-mentioned double shallow trenches, since the patterned photoresist covers the shallow trenches located in the pixel area and exposes the shallow trenches located in the logic area, and the photoresist may contact the substrate, when the shallow trenches located in the logic area are etched for the second time based on the patterned photoresist, the patterned mask layer located in the logic area will be etched and thinned, resulting in a height difference between the patterned mask layer located in the logic area and the patterned mask layer located in the pixel area. This height difference will affect the subsequent process steps and reduce product reliability.

[0004] Therefore, providing an image sensor with higher reliability has become an urgent problem to be solved. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing an image sensor to address the reliability issues in traditional image sensor technology.

[0006] In order to achieve the above object, the present application provides a method for preparing an image sensor, comprising:

[0007] Providing a substrate, wherein the substrate has a pixel area and a logic area;

[0008] forming a patterned mask layer on the substrate;

[0009] Etching the substrate to a first preset depth based on the patterned mask layer to form a first shallow trench located in the logic area and a second initial shallow trench located in the pixel area;

[0010] An epitaxial layer is formed on the surface of the second initial shallow trench, and the epitaxial layer reduces the depth of the second initial shallow trench from the first preset depth to a second preset depth to form a second shallow trench.

[0011] The preparation method of the above-mentioned image sensor does not involve multiple etchings, so there will be no height difference between the graphic mask layer of the logic area and the pixel area, thereby avoiding the residue of the graphic mask layer, ensuring that the graphic mask layer is completely removed, and further improving product reliability.

[0012] In one embodiment, the width of the first shallow trench is smaller than the width of the second initial shallow trench;

[0013] The step of forming an epitaxial layer on the surface of the second initial shallow trench comprises:

[0014] forming an epitaxial barrier layer on the surface of the first shallow trench;

[0015] Based on the epitaxial barrier layer, epitaxial growth is performed on the surface of the second initial shallow trench to form the epitaxial layer.

[0016] In one embodiment, the step of performing epitaxial growth on the surface of the second initial shallow trench based on the epitaxial barrier layer to form the epitaxial layer includes:

[0017] The substrate based on the surface of the second initial shallow trench is selectively epitaxially grown and P-type doped to form the epitaxial layer doped with P-type ions.

[0018] In one embodiment, forming an epitaxial barrier layer on the surface of the first shallow trench includes:

[0019] forming an epitaxial barrier material layer on the surface of the first shallow trench and the surface of the second shallow trench;

[0020] The epitaxial barrier material layer on the surface of the second initial shallow trench is removed, and the epitaxial barrier material layer remaining on the surface of the first shallow trench forms an epitaxial barrier layer.

[0021] In one embodiment, forming an epitaxial barrier material layer on the surface of the first shallow trench and the second shallow trench includes:

[0022] The surfaces of the first shallow trench and the second initial shallow trench are oxidized to form a first oxide material layer, and the first oxide material layer serves as the epitaxial barrier material layer.

[0023] In one embodiment, removing the epitaxial barrier material layer on the surface of the second initial shallow trench includes:

[0024] Filling the first shallow trench with a patterned photoresist layer;

[0025] Based on the patterned photoresist layer, the epitaxial barrier material layer on the surface of the second initial shallow trench is removed by etching.

[0026] In one embodiment, the step of filling the first shallow trench with a patterned photoresist layer includes:

[0027] The patterned photoresist layer is formed in the logic area.

[0028] In one embodiment, after forming the epitaxial layer on the surface of the second initial shallow trench, the method further comprises:

[0029] A second oxide layer is formed on the surface of the epitaxial layer.

[0030] In one embodiment, forming a patterned mask layer on the substrate includes:

[0031] forming a pad oxide layer on the substrate;

[0032] forming a hard mask layer on the pad oxide layer;

[0033] Based on the photolithography process, the pad oxide layer and the hard mask layer are patterned to form the patterned mask layer.

[0034] In one embodiment, the pad oxide layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer or a silicon oxynitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a flow chart of a method for preparing an image sensor provided in an embodiment;

[0037] Figure 2 is a schematic cross-sectional structural diagram of a structure obtained in step S100 in a method for preparing an image sensor provided in an embodiment;

[0038] Figure 3 is a schematic cross-sectional structural diagram of a structure obtained in step S300 in a method for preparing an image sensor provided in an embodiment;

[0039] Figure 4 is a schematic cross-sectional structural diagram of a structure obtained in step S411 in a method for preparing an image sensor provided in an embodiment;

[0040] Figure 5 is a schematic cross-sectional structural diagram of a structure obtained in step S412 in a method for preparing an image sensor provided in an embodiment;

[0041] Figure 6is a schematic diagram of a cross-sectional structure of a structure obtained in step S400 in a method for preparing an image sensor provided in an embodiment;

[0042] Figure 7 FIG. 1 is a schematic diagram of a cross-sectional structure of a structure obtained in step S500 in a method for preparing an image sensor provided in an embodiment.

[0043] Explanation of the figure numbers: 100-substrate, 110-logic area, 120-pixel area, 200-patterned mask layer, 210-pad oxide layer, 220-hard mask layer, 300-epitaxial barrier layer, 310-epitaxial barrier material layer, 400-second oxide layer, 500-epitaxial layer, 600-patterned photoresist layer, 710-first mask, 720-second mask. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0047] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0048] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0049] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques.

[0050] In one embodiment, see Figure 1 , provides a method for preparing an image sensor, comprising:

[0051] Step S100, providing a substrate 100, the substrate 100 having a pixel area 120 and a logic area 110;

[0052] Step S200, forming a patterned mask layer 200 on the substrate 100;

[0053] Step S300, etching the substrate 100 to a first preset depth based on the patterned mask layer 200 to form a first shallow trench located in the logic area 110 and a second initial shallow trench located in the pixel area 120;

[0054] In step S400 , an epitaxial layer 500 is formed on the surface of the second initial shallow trench, and the epitaxial layer 500 reduces the depth of the second initial shallow trench from the first preset depth to the second preset depth to form a second shallow trench.

[0055] In step S100, the base 100 may include a semiconductor substrate, which may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Therefore, the type of semiconductor substrate should not limit the protection scope of the present application.

[0056] See also Figure 2 , the substrate 100 has a pixel area 120 and a logic area 110. It can be understood that the semiconductor substrate also has a pixel area 120 and a logic area 110. The pixel area 120 can be used to form array-arranged pixels and various components. The pixel area 120 is used to absorb light, thereby generating photocharges or photoelectrons and accumulating them in the photosensitive area of ​​the photodiode. The logic area 110 can be used to form a logic circuit connecting pixels. The logic area 110 provides an operating environment and external communication for the pixel area 120; based on increasing the photosensitive area of ​​the pixel area 120 and reducing the dark current between pixels, the shallow trench depth required for the pixel area 120 is shallower than that of the logic area 110.

[0057] In step S200, refer to Figure 3 , a patterned mask layer 200 is formed on the substrate 100. Specifically, a mask layer may be first formed on the substrate 100; then the mask layer is patterned using a first photomask 710 to form a patterned mask layer 200 having a plurality of openings, wherein the openings expose the surface of the substrate 100 and are respectively located in the pixel region 120 and the logic region 110. As an example, the patterned mask layer 200 may have two, ten or fifty openings.

[0058] The patterned mask layer 200 may include multiple film layers, which is not limited here. At the same time, the materials of each film layer are not limited here. As an example, the material of the patterned mask layer 200 may be silicon oxide, silicon nitride, or silicon oxynitride, etc., which are formed using a variety of processes.

[0059] In step S300, refer to Figure 3 , the substrate 100 can be etched based on the multiple openings on the patterned mask layer 200 to form a first shallow trench and a second initial shallow trench. The first shallow trench is located in the logic area 110, and the second initial shallow trench is located in the pixel area 120. It can be understood that the first shallow trench and the second initial shallow trench in this embodiment are used to distinguish different trenches, and do not limit the actual number of trenches on the substrate 100. It can be understood that when the number of openings in the patterned mask layer 200 corresponds to the number of trenches on the substrate 100.

[0060] The depth of the first shallow trench is the same as that of the second initial shallow trench, and the depth can be defined as a first preset depth D 1 The present embodiment does not impose any specific limitation on the widths of the first shallow trench and the second shallow trench. For example, the width of the first shallow trench may be smaller than the width of the second initial shallow trench.

[0061] In step S400, refer to Figure 6 , an epitaxial layer 500 is formed on the surface of the second initial shallow trench. As an example, at this time, the epitaxial layer 500 can be formed by selective epitaxial growth. Figure 5 and Figure 6 , the epitaxial layer 500 has a certain thickness, so the epitaxial layer 500 reduces the depth and width of the second initial shallow trench. Figure 5 In the case where the epitaxial layer 500 is not formed, the depth of the second initial shallow trench is D 1 , width W 1 .exist Figure 6 After the epitaxial layer 500 is formed, the second initial shallow trench becomes a second shallow trench, and the depth of the second shallow trench at this time is defined as the second preset depth D 2 , the width of the second shallow trench is a second preset width W 2 Specifically, when the selective epitaxy is performed, when the growth rates of the epitaxial layer 500 at the trench sidewall and the trench bottom are substantially the same, it can be considered that the thickness of the epitaxial layer 500 is uniform. It can be understood that the depth D of the second initial shallow trench is 1 Equal to the second preset depth D 2 With epitaxial layer thickness of 500 (W 3 ) and the second initial shallow trench (W 1 ) is equal to the width of the second shallow trench (W 2 ) and twice the thickness of the epitaxial layer 500 (W 3 ). At this time, the second preset depth D 2 Less than the first preset depth D 1 , the second preset width W 2 Less than W 1 Therefore, the depth and width of the second shallow trench can be adjusted by the thickness of the epitaxial layer 500 .

[0062] As an example, the thickness and width of the epitaxial layer 500 are preset values. This embodiment does not limit the specific values ​​of the thickness and width of the epitaxial layer 500.

[0063] So far, in this embodiment, shallow trenches of different depths are formed in the pixel area 120 and the logic area 110. It can be understood that this embodiment does not limit the number of shallow trenches of different depths. As an example, the pixel area 120 and the logic area 110 can each have a shallow trench with different depths.

[0064] After step S400, the first shallow trench and the second shallow trench may be filled to form an isolation material layer that fills the first shallow trench and the second shallow trench and covers the patterned mask layer 200. As an example, the material of the isolation material layer may include silicon oxide formed by deposition through a high density plasma (HDP) process or a high aspect ratio process (HARP) process. Then, the isolation material layer is removed by chemical mechanical polishing, specifically, the isolation material layer outside the first shallow trench and the second shallow trench is removed to form an isolation layer.

[0065] In the preparation process of a traditional image sensor, the substrate is first etched based on the patterned mask layer 200 to form two shallow grooves with a shallow depth, and then the shallow groove located in the pixel area 120 is covered with a patterned photoresist, and the shallow groove located in the logic area 110 is etched a second time, thereby forming two shallow grooves of different depths.

[0066] In the above preparation process, since the patterned photoresist covers the shallow grooves located in the pixel area 120 and exposes the shallow grooves located in the logic area 110, when the shallow grooves located in the logic area 110 are etched for the second time based on the patterned photoresist, the patterned mask layer located in the logic area 110 will be etched and thinned, so that the patterned mask layer 200 on the substrate 100 has a height difference at the junction of the pixel area 120 and the logic area 110, forming an uneven step surface. In addition, when the isolation material layer in the shallow groove is removed by chemical mechanical polishing, the patterned mask layer 200 will be used as a stop layer and stop on the surface of the higher image mask layer located in the pixel area 120. At this time, the isolation material layer is still retained on the lower patterned mask layer 200 located in the logic area 110, and the isolation material layer will cause the subsequent removal of the patterned mask layer 200 to be incomplete.

[0067] In this embodiment, by first forming a first preset depth D 1 The first shallow trench and the second initial shallow trench are formed, and then an epitaxial layer 500 is formed on the surface of the second initial shallow trench, so as to form a second preset depth D 2 The second shallow trench is formed to complete the preparation of the double shallow trench. 1 Greater than the second preset depth D 2 Since this embodiment does not involve multiple etchings, there will be no height difference in the patterned mask layer 200, thereby reducing the residue of the patterned mask layer 200, ensuring that the patterned mask layer 200 is completely removed, and the photoresist will not directly contact the substrate 100, further improving product reliability.

[0068] In one embodiment, step S400 includes:

[0069] Step S410, forming an epitaxial barrier layer 300 on the surface of the first shallow trench;

[0070] In step S420 , based on the epitaxial barrier layer 300 , selective epitaxial growth is performed on the surface of the second initial shallow trench to form an epitaxial layer 500 .

[0071] In step S410 , there is no specific limitation on the method of forming the epitaxial barrier layer 300 .

[0072] As an example, the substrate on the surface of the first shallow trench may be oxidized to form a first oxide layer, and the first oxide layer is used as the epitaxial barrier layer 300. For example, the oxidation method may be to perform thermal oxidation treatment on the substrate on the surface of the first shallow trench, or to perform treatment by an in-situ water vapor method or the like, to form the first oxide layer.

[0073] In this example, the first oxide layer can repair the damage caused by etching to the substrate 100, making the surface of the first shallow trench smoother. At the same time, the first oxide layer makes the bottom angle and top angle of the first shallow trench smoother, preventing the tip discharge of the product.

[0074] In step S420, the epitaxial barrier layer 300 covers the surface of the first shallow trench and exposes the surface of the second shallow trench. Therefore, based on the epitaxial barrier layer 300, selective epitaxial growth can be performed on the surface of the second initial shallow trench that is not covered by the epitaxial barrier layer 300, thereby forming the epitaxial layer 500. For example, dichlorosilane (SiH 2 C 12 , DCS) as the silicon source. For example, the process temperature during the epitaxial growth process can be between 950°C and 1150°C.

[0075] In addition, as an example, in step S300, see Figure 3 , the width of the first shallow trench may be different from the width of the second initial shallow trench. For example, the width of the first shallow trench may be smaller than the width of the second initial shallow trench. After forming the epitaxial layer 500, the width of the first shallow trench may be the same as the width of the second shallow trench. Of course, the height and width in this embodiment both include process errors.

[0076] In one embodiment, step S420 includes:

[0077] In step S421 , epitaxial growth and P-type doping are performed on the substrate 100 based on the surface of the second initial shallow trench to form an epitaxial layer 500 doped with P-type ions.

[0078] Specifically, B can be doped while epitaxial growth is being performed. 2 H6 , thereby improving the isolation effect of the second shallow trench.

[0079] In this embodiment, P-type doping is performed while the substrate 100 is epitaxially grown, thereby saving the ion implantation step and the corresponding photomask in the conventional process. At the same time, since the ion implantation process is not used in this embodiment, it is not necessary to prepare shallow trench isolation in the pixel area as in the conventional technology, thereby avoiding the shadowing effect that may occur in the ion implantation process with an angle, and the resulting electrical deviation and reduced imaging effect.

[0080] In addition, this embodiment also saves the patterned photoresist used to cover the shallow trench of the logic area 110 in the ion implantation process and the photomask used when forming it. It can be understood that this process requires complete self-alignment, so this embodiment can also avoid the problem of uneven overlay that may occur in the photolithography process before ion implantation.

[0081] In the traditional process, it is necessary to perform P-type ion implantation separately in the isolation shallow groove of the pixel area 120 to prevent the electrons in the pixel area 120 from contacting with the surface defects, thereby improving the isolation effect. However, the process is complicated, and a separate mask needs to be introduced to complete the definition of the ion implantation area. Moreover, the angle of ion implantation is difficult to control, which may cause electrical deviation and increase of dark current and white spot defects of the image sensor, thereby reducing the imaging quality of the image sensor. In this embodiment, P-type doping can prevent the electrons in the pixel area 120 from combining with the surface interface defects, thereby further improving the isolation effect of the groove.

[0082] In one embodiment, see Figure 4 as well as Figure 5 , step S410 includes:

[0083] Step S411, forming an epitaxial barrier material layer 310 on the surface of the first shallow trench and the surface of the second shallow trench;

[0084] Step S412 , removing the epitaxial barrier material layer 310 on the surface of the second initial shallow trench, and retaining the epitaxial barrier material layer 310 on the surface of the first shallow trench to form an epitaxial barrier layer 300 .

[0085] When the epitaxial barrier layer 300 is formed on the surface of the first shallow trench, refer to Figure 4, an epitaxial barrier material layer 310 may be first formed on both the surface of the first shallow trench and the surface of the second initial shallow trench, and then the epitaxial barrier material layer 310 on the surface of the second initial shallow trench may be removed, and the epitaxial barrier material layer 310 on the surface of the first shallow trench may be retained, thereby forming an epitaxial barrier layer 300. As an example, the epitaxial barrier material layer 310 may be formed by a thermal oxidation process, in which case the surfaces of the first shallow trench and the second shallow trench may be thermally oxidized to form a first oxide material layer, which may serve as the epitaxial barrier material layer 310. Thereafter, the first oxide material layer may be subsequently processed to form a first oxide layer, which may serve as the epitaxial barrier layer 300.

[0086] In step S412, refer to Figure 5 As an example, in order to retain the epitaxial barrier material layer 310 located on the surface of the first shallow trench, a patterned photoresist layer 600 may be filled in the first shallow trench, and the patterned photoresist layer 600 covers the epitaxial barrier material layer 310 on the surface of the first shallow trench. Based on the patterned photoresist layer 600, the epitaxial barrier material layer 310 is etched, and since the epitaxial barrier material layer 310 on the surface of the first shallow trench is covered by the patterned photoresist layer 600, it is retained to form the epitaxial barrier layer 300, and the epitaxial barrier material layer 310 on the surface of the second initial shallow trench is removed. As an example, when etching the epitaxial barrier material layer 310, a dry etching method or a wet etching method may be used. For example, wet etching may be used when etching the epitaxial barrier material layer 310, and the etching liquid may include diluted hydrofluoric acid (DHF / BOE) and the like to reduce the etching cost.

[0087] For example, when the patterned photoresist layer 600 is filled in the first shallow trench, the patterned photoresist layer 600 may be formed in the logic region 110 ; for another example, the patterned photoresist layer 600 may be formed only in the first shallow trench.

[0088] Specifically, during the formation of the patterned photoresist layer 600 , a photoresist layer may be coated first, and then the second photomask 720 may be used to expose and develop the photoresist layer, thereby forming the patterned photoresist layer 600 .

[0089] In this example, the patterned photoresist layer 600 covers the epitaxial barrier layer 300 on the surface of the first shallow trench and does not directly contact the surface of the substrate 100 , thereby preventing the patterned photoresist layer 600 from contaminating the substrate 100 .

[0090] In one embodiment, see Figure 7 , after step S400, further comprising:

[0091] In step S500 , a second oxide layer 400 is formed on the surface of the epitaxial layer 500 .

[0092] The second oxide layer 400 is not specifically limited here, and it can be made by the same process as the epitaxial barrier layer 300. For example, the second oxide layer 400 can be formed by thermal oxidation, or by low pressure chemical vapor deposition, or in-situ water vapor deposition, etc.

[0093] In addition, before step S500, the photoresist may be removed by dry etching or wet etching. For example, when wet etching is used, a mixture of sulfuric acid and hydrogen peroxide (Sulfuric Peroxide Mixture, SPM) may be used as an etching liquid to save costs.

[0094] In this embodiment, the second oxide layer 400 is formed on the epitaxial layer 500, which can provide a smoother surface for the epitaxial layer 500. At the same time, the formation of the second oxide layer 400 in this embodiment can also smooth the top angle and bottom angle of the bottom of the second shallow trench to avoid tip discharge and protect the substrate 100 from possible plasma damage in the subsequent formation of the isolation oxide layer, thereby further improving the reliability of the image sensor.

[0095] Also, see Figure 3 , the width of the first shallow trench and the width of the second initial shallow trench may be different. For example, the width of the first shallow trench may be smaller than the width of the second initial shallow trench. In this case, please refer to Figure 7 , the width (W 4 ), which may be the same as the width (W 5 ) are consistent, thus forming a regular image sensor structure.

[0096] In one embodiment, see Figure 2 as well as Figure 3 , step S200 includes:

[0097] Step S210, forming a pad oxide layer 210 on the substrate 100;

[0098] Step S220 , forming a hard mask layer 220 on the pad oxide layer 210 ;

[0099] In step S230 , the pad oxide layer 210 and the hard mask layer 220 are patterned based on a photolithography process to form a patterned mask layer 200 .

[0100] The patterned mask layer 200 may include a pad oxide layer 210 and a hard mask layer 220, which are sequentially formed on the substrate 100. The pad oxide layer 210 is used to buffer the stress between the substrate 100 and the hard mask layer. The pad oxide layer 210 may be formed of an oxide material. It is understood that the pad oxide layer 210 includes a silicon oxide layer. The hard mask layer 220 may be formed of a silicon nitride (SiN) material. It is understood that the hard mask layer 220 includes a silicon nitride layer.

[0101] When patterning the pad oxide layer 210 and the hard mask layer 220 based on the photolithography process, first, photoresist can be applied; then the photoresist is exposed and developed using a first photomask 710 to form a patterned photoresist; finally, the pad oxide layer 210 and the hard mask layer 220 are etched layer by layer based on the patterned photoresist.

[0102] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0103] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing an image sensor, characterized in that: include: Providing a substrate, wherein the substrate has a pixel area and a logic area; forming a patterned mask layer on the substrate; Etching the substrate to a first preset depth based on the patterned mask layer to form a first shallow trench located in the logic area and a second initial shallow trench located in the pixel area, wherein the width of the first shallow trench is smaller than the width of the second initial shallow trench; forming an epitaxial layer on the surface of the second initial shallow trench, adjusting the depth and width of the second initial shallow trench by the thickness of the epitaxial layer, and the epitaxial layer reduces the depth of the second initial shallow trench from the first preset depth to a second preset depth to form a second shallow trench, wherein the depth of the second shallow trench is less than the depth of the first shallow trench; The step of forming an epitaxial layer on the surface of the second initial shallow trench comprises: forming an epitaxial barrier layer on the surface of the first shallow trench; Based on the epitaxial barrier layer, epitaxial growth is performed on the surface of the second initial shallow trench to form the epitaxial layer; After forming an epitaxial layer on the surface of the second initial shallow trench, the method further includes: A second oxide layer is formed on the surface of the epitaxial layer, and the width of the second shallow trench after the second oxide layer is formed is consistent with the width of the first shallow trench after the epitaxial barrier layer is formed.

2. The method for preparing an image sensor according to claim 1, characterized in that: The forming of an epitaxial barrier layer on the surface of the first shallow trench comprises: The substrate on the surface of the first shallow trench is oxidized to form a first oxide layer, and the first oxide layer is used as the epitaxial barrier layer.

3. The method for preparing an image sensor according to claim 2, characterized in that: The step of performing epitaxial growth on the surface of the second initial shallow trench based on the epitaxial barrier layer to form the epitaxial layer comprises: The substrate based on the surface of the second initial shallow trench is selectively epitaxially grown and P-type doped to form the epitaxial layer doped with P-type ions.

4. The method for preparing an image sensor according to claim 2, characterized in that: The step of forming an epitaxial barrier layer on the surface of the first shallow trench comprises: forming an epitaxial barrier material layer on the surface of the first shallow trench and the surface of the second shallow trench; The epitaxial barrier material layer on the surface of the second initial shallow trench is removed, and the epitaxial barrier material layer remaining on the surface of the first shallow trench forms an epitaxial barrier layer.

5. The method for preparing an image sensor according to claim 4, characterized in that: The step of forming an epitaxial barrier material layer on the surfaces of the first shallow trench and the second shallow trench comprises: The surfaces of the first shallow trench and the second initial shallow trench are oxidized to form a first oxide material layer, and the first oxide material layer serves as the epitaxial barrier material layer.

6. The method for preparing an image sensor according to claim 4, characterized in that: The removing of the epitaxial barrier material layer on the surface of the second initial shallow trench comprises: Filling the first shallow trench with a patterned photoresist layer; Based on the patterned photoresist layer, the epitaxial barrier material layer on the surface of the second initial shallow trench is removed by etching.

7. The method for preparing an image sensor according to claim 6, characterized in that: The step of filling the first shallow trench with an imaged photoresist layer comprises: The patterned photoresist layer is formed in the logic area.

8. The method for preparing an image sensor according to claim 1, characterized in that: Dichlorosilane was selected as the silicon source during the epitaxial growth process.

9. The method for preparing an image sensor according to claim 1, characterized in that: The step of forming a patterned mask layer on the substrate comprises: forming a pad oxide layer on the substrate; forming a hard mask layer on the pad oxide layer; Based on the photolithography process, the pad oxide layer and the hard mask layer are patterned to form the patterned mask layer.

10. The method for preparing an image sensor according to claim 9, characterized in that: The pad oxide layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer or a silicon oxynitride layer.

Images