Formation method of semiconductor device

Abstract

The invention provides a method for forming a semiconductor device. The method comprises the following steps: providing a substrate; p trap ion implantation of the first active region is executed; forming a first gate layer on the substrate of the first active region; forming a second gate layer on the substrate of the second active region; performing maskless N-type drain electrode lightly doped ion implantation; and executing N trap ion implantation and P-type drain electrode lightly doped ion implantation of the second active region under the same photomask. Processing is carried out on a low-cost and high-cost-performance platform, and N-trap ion implantation and P-type drain electrode lightly doped ion implantation share the same photomask; after the gate layer is etched, maskless N-type drain electrode lightly doped ion implantation is carried out under the condition that the photoresist layer after the gate layer is etched is reserved, so that the gate layer is prevented from being punched by the N-type lightly doped ion implantation. And photomasks for forming the N well and the N-type drain electrode light doping are saved. And two LDD ion implantation processes are reserved, so that the hot carrier effect performance of the NMOS tube is ensured, the leakage current of the substrate is reduced, and the reliability test is passed.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for forming a semiconductor device. Background Art

[0002] For the production of CMOS devices (for example, with an operating voltage of 7V), the market requires a low-cost, cost-effective process platform. While ensuring that the gate size of 7V CMOS devices and 5V CMOS devices remain unchanged, at least two masks are required to be saved on the basis of the normal logic process, which poses a great challenge to the logic process of the wafer processing plant. Summary of the invention

[0003] The purpose of the present invention is to provide a method for forming a semiconductor device, which is processed on a low-cost, high-cost-performance process platform, and the N-well ion implantation and the P-type drain lightly doped ion implantation share the same mask, and the N-type drain lightly doped uses maskless ion implantation, which saves the masks of the two processes of forming the N-well and the N-type drain lightly doped. While retaining the process of two LDD ion implantations, the hot carrier effect performance of the NMOS tube is prioritized, the substrate leakage current is greatly reduced, and the reliability test is passed.

[0004] The present invention provides a method for forming a semiconductor device, comprising:

[0005] Step S1, providing a substrate, on which a first active area and a second active area are defined by shallow trench isolation;

[0006] Step S2, performing P-well ion implantation in the first active area;

[0007] Step S3, forming a gate layer, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region;

[0008] Step S4, retaining the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region;

[0009] Step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region under the same photomask; in the second active region, the implanted P-type drain lightly doped ions neutralize the N-type second lightly doped region and invert to finally form a P-type lightly doped region;

[0010] Step S6, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube;

[0011] Step S7, performing P-type ion heavy doping implantation on the second active region II to form a source region and a drain region of the PMOS tube.

[0012] Furthermore, step S3 specifically includes:

[0013] forming a gate oxide material layer and a gate material layer sequentially covering the substrate;

[0014] Forming an imaged second photoresist layer on the surface of the gate material layer, wherein the imaged second photoresist layer includes a second photoresist layer first region and a second photoresist layer second region;

[0015] Using the second photoresist layer as a mask, the gate material layer and the gate oxide layer material layer are etched in sequence to form the first gate layer and the first gate oxide layer located below the first region of the second photoresist layer, and the second gate layer and the second gate oxide layer located below the second region of the second photoresist layer.

[0016] Furthermore, when the maskless N-type drain lightly doped ion implantation is performed in step S4, the first region of the second photoresist layer and the second region of the second photoresist layer are still retained;

[0017] After the maskless N-type drain lightly doped ion implantation is completed, the first region of the second photoresist layer and the second region of the second photoresist layer are removed.

[0018] Furthermore, step S5 specifically includes:

[0019] A third photoresist layer is formed, wherein the third photoresist layer has an opening in the second active area and covers the first active area; using the third photoresist layer as a mask, the N-well ion implantation is first performed on the second active area to form an N-well; and then the P-type drain lightly doped ion implantation is performed on the second active area to form a P-type lightly doped area.

[0020] Furthermore, in step S5, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.

[0021] Furthermore, in step S5, the N-well ion implantation also passes through the second gate layer and the second gate oxide layer and enters the substrate below.

[0022] Furthermore, the operating voltage of the semiconductor device includes: 7V or 5V.

[0023] Furthermore, after step S5 and before step S6, the forming method further includes:

[0024] A first sidewall is formed on the substrate of the first active region, and the first sidewall covers the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, and the second sidewall covers the sidewalls of the second gate oxide layer and the second gate layer.

[0025] Furthermore, after step S7, the forming method further includes:

[0026] Forming metal silicide, forming the metal silicide on the surfaces of the first gate layer and the second gate layer, and the surfaces of the substrate of the first active region and the second active region;

[0027] forming a dielectric layer, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer; and forming a contact hole in the dielectric layer;

[0028] Metal interconnection is formed, metal is filled in the contact hole, and the gate, source region and drain region of the NMOS tube and the PMOS tube are led out.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides a method for forming a semiconductor device, comprising: step S1, providing a substrate, on which a first active area and a second active area are defined by shallow trench isolation; step S2, performing P-well ion implantation in the first active area; step S3, forming a gate layer, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active area; sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active area; step S4, retaining the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer, forming an N-type first lightly doped area in the first active area, and forming an N-type second lightly doped area in the second active area; step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active area under the same photomask; step S6, performing N-type ion heavy doping implantation in the first active area to form a source area and a drain area of ​​an NMOS tube; step S7, performing P-type ion heavy doping implantation in the second active area II to form a source area and a drain area of ​​a PMOS tube.

[0031] The method for forming a semiconductor device provided by the present invention is manufactured on a low-cost, high-cost-performance process platform, and the N-well ion injection and the P-type drain lightly doped (LDD) ion injection share the same mask. After the gate layer is etched, the maskless N-type drain lightly doped ion injection is performed while retaining the photoresist layer after the gate layer is etched, so as to avoid the gate layer being penetrated by the N-type lightly doped ion injection. The masks (mask plates) for the two processes of forming the N-well and the N-type drain lightly doped (LDD) are saved. Under the process conditions of retaining the two LDD ion injections of the N-type drain lightly doped (LDD) and the P-type drain lightly doped (LDD), the hot carrier effect performance of the NMOS tube is preferentially guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the electrical performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Normal logic process flow chart for 5V CMOS devices.

[0033] Figure 2 Mask-saving logic process flow diagram for 5V CMOS devices.

[0034] Figure 3 The present invention is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0035] Figure 4 It is a schematic diagram of the method for forming a semiconductor device according to an embodiment of the present invention after ion implantation into the first active region P-well.

[0036] Figure 5 It is a schematic diagram of a semiconductor device after performing maskless N-type drain lightly doped (LDD) ion implantation in a method for forming the semiconductor device according to an embodiment of the present invention.

[0037] Figure 6 The diagram is a schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention after N-well ion implantation and P-type drain lightly doped (LDD) ion implantation are performed in a second active region.

[0038] Figure 7 The present invention is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0039] The reference numerals are as follows:

[0040] 10-substrate; 10a-P well; 10b-N well; 11-STI; I-first active region; II-second active region; 121-first gate oxide layer; 122-second gate oxide layer; 131-first gate layer; 132-second gate layer; 141-N-type first lightly doped region; 142-N-type second lightly doped region; 152-P-type lightly doped region; 21-first photoresist layer; 221-second photoresist layer first region; 222-second photoresist layer second region; 23-third photoresist layer. DETAILED DESCRIPTION

[0041] As described in the background art, the market requires a low-cost, cost-effective process platform for the manufacture of CMOS devices.

[0042] Figure 1 The following is a normal logic process flow chart of a 5V CMOS device. The inventor has found that in order to save masks, Figure 1 Based on the process, directly omitting the two process steps of N-type drain light doping (LDD) and P-type drain light doping (LDD) and the corresponding two masks will result in a very poor hot carrier effect of the CMOS device and a very high substrate leakage current Isub, which cannot pass the reliability evaluation.

[0043] Figure 2 The following is a process flow chart of mask-saving logic for 5V CMOS devices. Figure 2 The same process, Figure 1 Based on the normal logic process of 5V CMOS devices, the N-type drain light doping (LDD) and the N-type ion heavy doping share the same mask, and the P-type drain light doping (LDD) and the P-type ion heavy doping share the same mask; in this way, two masks of N-type drain light doping (LDD) and P-type drain light doping (LDD) can be saved; but in actual tests, it is found that under the application voltage of 7VCMOS devices, the substrate leakage current Isub is still very high and cannot pass the reliability test. Therefore, for the low-cost and cost-effective process platform of 7V CMOS devices, a new process method is urgently needed to save mask costs and ensure device performance, especially the electrical performance of NMOS tubes.

[0044] Based on the above research, the present invention provides a method for forming a semiconductor device. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0045] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0046] An embodiment of the present invention provides a method for forming a semiconductor device, such as Figure 3 As shown, including:

[0047] Step S1, providing a substrate, on which a first active area and a second active area are defined by shallow trench isolation;

[0048] Step S2, performing P-well ion implantation in the first active area;

[0049] Step S3, forming a gate layer, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; and sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region;

[0050] Step S4, retaining the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region;

[0051] Step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region under the same photomask; in the second active region, the implanted P-type drain lightly doped ions neutralize the N-type second lightly doped region and invert to finally form a P-type lightly doped region;

[0052] Step S6, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube;

[0053] Step S7, performing P-type ion heavy doping implantation on the second active region II to form a source region and a drain region of the PMOS tube.

[0054] Combine the following Figures 4 to 7 Each step of the method for forming a semiconductor device according to an embodiment of the present invention is described in detail.

[0055] Step S1: Figure 4 As shown, a substrate 10 is provided, and a first active region I and a second active region II are defined on the substrate 10 by shallow trench isolation (STI) 11. The substrate 10 may include a semiconductor material, and may be a single-layer structure or a multi-layer structure. The substrate 10 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors; it may also include a layered substrate such as silicon on insulator (SOI) or silicon germanium on insulator. This embodiment is described by taking the first active region I being used to form NMOS and the second active region II being used to form PMOS as an example. In other embodiments, the first active region I may be used to form PMOS, and the second active region II may be used to form NMOS.

[0056] Step S2: Figure 4 As shown, P-well ion implantation is performed in the first active region I. Specifically, a first photoresist layer 21 is formed, the first photoresist layer 21 has an opening in the first active region I, the first photoresist layer 21 exposes the first active region I, and the first photoresist layer 21 covers the second active region II. Using the first photoresist layer 21 as a mask, P-well (Well) ion implantation is performed in the first active region I to form a P-well 10a.

[0057] Step S3: Figure 5 As shown, a gate layer is formed, and a first gate oxide layer 121 and a first gate layer 131 are sequentially formed on the substrate of the first active region I; a second gate oxide layer 122 and a second gate layer 132 are sequentially formed on the substrate of the second active region II. Specifically, a thermal oxidation growth process can be used to grow the material layers of the first gate oxide layer 121 and the second gate oxide layer 122, and the temperature of the thermal oxidation growth process is, for example, 900° C. to 1150° C. The material layers of the first gate layer 131 and the second gate layer 132 can be formed by any one of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or metal organic chemical vapor deposition (MOCVD) and other suitable processes.

[0058] The first region 221 of the second photoresist layer and the second region 222 of the second photoresist layer are used as masks, and the first gate layer 131 and the second gate layer 132, as well as the first gate oxide layer 121 and the second gate oxide layer 122 are formed by the same etching process. The tail end of the first gate layer 131 and the tail end of the second gate layer 132 can be connected together. The tail end of the first gate oxide layer 121 and the tail end of the second gate oxide layer 122 can be connected together.

[0059] Step S4: Figure 5As shown, the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer is retained; maskless N-type drain lightly doped (LDD) ion implantation is performed under the protection of the photoresist layer, and an N-type first lightly doped region 141 is formed on the shallow surface of the substrate located on both sides of the first gate layer 131 in the first active region I, and an N-type second lightly doped region 142 is formed on the shallow surface of the substrate located on both sides of the second gate layer 132 in the second active region II. In this step, after etching to form the first gate layer 131 and the second gate layer 132, the first region 221 of the second photoresist layer and the second region 222 of the second photoresist layer are retained to prevent the maskless LDD ion implantation from entering the substrate 10 directly below the first gate layer 131 and the second gate layer 132. After the maskless LDD ion implantation step is completed, the first region 221 of the second photoresist layer and the second region 222 of the second photoresist layer are removed.

[0060] Step S5: Figure 6 As shown, N-well ion implantation and P-type drain lightly doped (LDD) ion implantation are performed in the second active region II. Specifically, a third photoresist layer 23 is formed, and the third photoresist layer 23 has an opening in the second active region II. The third photoresist layer 23 exposes the second active region II, and the third photoresist layer 23 covers the first active region I. Using the third photoresist layer 23 as a mask, N-well ion implantation is first performed in the second active region II to form an N-well 10b; the N-well ion implantation also passes through the second gate layer 132 and enters the substrate directly below it. Using the third photoresist layer 23 as a mask, P-type drain lightly doped (LDD) ion implantation is performed in the second active region II to form a P-type lightly doped region 152. The N-well ion implantation depth is greater than the P-type drain lightly doped (LDD) ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped (LDD) ion implantation energy. It should be understood that in step S4, the N-type second lightly doped region 142 is formed in the shallow surface source region and drain region of the substrate on both sides of the second active region II of the second gate layer 132. In step S5, more P-type drain lightly doped (LDD) ions need to be injected into the shallow surface source region and drain region of the substrate of the second active region II to neutralize the previous N-type second lightly doped region 142, and invert to finally form a P-type lightly doped region 152. By performing drain light doping (LDD), the short channel effect and the hot carrier effect are suppressed, the concentration gradient of the channel and the drain and source junction is reduced, and the electric field strength of the source and drain is reduced to a certain extent. By performing drain light doping (LDD), the lightly doped drain region has a lighter doping in the overlapping area with the gate layer, which can increase the penetration voltage of the LDD junction, improve the channel penetration characteristics of the device, and reduce the hot carrier effect and improve the reliability of the device.

[0061] Next, the third photoresist layer 23 is removed. A first sidewall spacer (not shown) is formed on the substrate of the first active region I, and the first sidewall spacer covers the sidewalls of the first gate oxide layer 121 and the first gate layer 131; a second sidewall spacer is formed on the substrate of the second active region II, and the second sidewall spacer covers the sidewalls of the second gate oxide layer 122 and the second gate layer 132.

[0062] Next, N-type ion heavy doping implantation is performed in the first active region I. Specifically, a fourth photoresist layer (not shown) is formed, the fourth photoresist layer has an opening in the first active region I, the fourth photoresist layer exposes the first active region I, and the fourth photoresist layer covers the second active region II. Using the fourth photoresist layer as a mask, N-type ion heavy doping implantation is performed in the first active region I. A source region and a drain region are respectively formed in the substrate on both sides of the first sidewall, and an NMOS is formed in the first active region I.

[0063] Next, perform P-type ion heavy doping injection into the second active region II. Specifically, a fifth photoresist layer (not shown) is formed, the fifth photoresist layer has an opening in the second active region II, the fifth photoresist layer exposes the second active region II, and the fifth photoresist layer covers the first active region I. Using the fifth photoresist layer as a mask, perform P-type ion heavy doping injection into the second active region II, form a source region and a drain region in the substrate on both sides of the second sidewall, and form a PMOS in the second active region II. The order of performing N-type ion heavy doping injection into the first active region I and performing P-type ion heavy doping injection into the second active region II can be swapped.

[0064] Next, metal silicide is formed. A layer of metal (such as Ti, Co, and NiPt, etc.) can be deposited on the first gate layer 131, the second gate layer 132, and the first active area I and the second active area II by physical vapor deposition. Then, rapid thermal annealing and selective wet etching are performed to finally form metal silicide on the surface of the first gate layer 131 and the second gate layer 132, and the substrate surface of the first active area I and the second active area II. Metal silicide includes thin films such as TiSi2, CoSi2, and NiPtSi. Metal Ti, Co, or NiPt will not react with dielectric materials to form metal silicide, but will only react with directly contacted polysilicon and substrate silicon of the active area to form metal silicide, so as to reduce the block resistance and contact resistance, thereby obtaining a smaller series resistance, reducing RC delay, and increasing the speed of the circuit.

[0065] Next, metal interconnection is formed; specifically, a dielectric layer is deposited, the dielectric layer covers the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer, etc., a chemical mechanical polishing (CMP) process is used to complete the dielectric layer flattening process, and then a dry etching process is used to complete the device contact hole processing. The device contact hole filling process is completed by a tungsten sputtering process and a tungsten chemical mechanical flattening process. The gate, source region and drain region can be led out through the contact hole. A metal film layer is sputtered and a metal wiring etching process is completed.

[0066] Combination Figure 7 As shown, the method for forming a semiconductor device provided by the present invention is manufactured on a low-cost, cost-effective process platform, and the N-well ion implantation and the P-type drain light doping (LDD) ion implantation share the same mask. The N-type drain light doping (LDD) adopts maskless ion implantation, which saves the masks (mask plates) of the two processes of forming the N-well and the N-type drain light doping (LDD). Under the process conditions of retaining the two LDD ion implantations of the N-type drain light doping (LDD) and the P-type drain light doping (LDD), the hot carrier effect performance of the NMOS tube is preferentially guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the hot carrier effect performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved.

[0067] The hot carrier injection of high-voltage NMOS tubes is worse than that of PMOS tubes. The majority carriers of NMOS tubes are electrons, and the electron mobility is higher than that of the majority carrier holes of PMOS tubes. Therefore, under the same electric field, the hot carrier effect injection of NMOS tubes will be worse. The present invention gives priority to ensuring the performance of NMOS tubes, and guarantees the performance of NMOS tubes as much as possible by giving priority to P-well ion implantation and maskless N-type drain lightly doped (LDD) ion implantation of NMOS tubes.

[0068] For example, the semiconductor device of this embodiment may be a CMOS device, and the operating voltage is, for example, 7V, that is, when the gate voltage and the drain voltage are 7V, the transistor is fully turned on. According to actual tests, the substrate leakage current Isub performance of the NMOS tube of the 7V CMOS device formed by the method for forming a semiconductor device of the present invention is better than that of the NMOS tube formed by the method for forming a semiconductor device of the present invention. Figure 2 The mask-saving logic process of the 5V CMOS device has been significantly improved, and the substrate leakage current Isub has been reduced to 1 / 4 of the original level before the improvement, which is only 0.6% of the saturation current Idsat.

[0069] In summary, the present invention provides a method for forming a semiconductor device, comprising: step S1, providing a substrate, on which a first active region and a second active region are defined by shallow trench isolation; step S2, performing P-well ion implantation in the first active region; step S3, forming a gate layer, sequentially forming a first gate oxide layer and a first gate layer on the substrate in the first active region; sequentially forming a second gate oxide layer and a second gate layer on the substrate in the second active region; step S4, retaining the first gate layer and the second gate layer covered in the step of forming the gate layer photoresist layer; performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region; step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region under the same photomask; step S6, performing N-type ion heavy doping implantation in the first active region to form a source region and a drain region of the NMOS tube; step S7, performing P-type ion heavy doping implantation in the second active region II to form a source region and a drain region of the PMOS tube.

[0070] The method for forming a semiconductor device provided by the present invention is manufactured on a low-cost, high-cost-performance process platform, and the N-well ion injection and the P-type drain lightly doped (LDD) ion injection share the same mask; after the gate layer is etched, the maskless N-type drain lightly doped ion injection is performed while retaining the photoresist layer after the gate layer is etched, so as to prevent the gate layer from being penetrated by the N-type lightly doped ion injection. The masks (mask plates) for the two processes of forming the N-well and the N-type drain lightly doped (LDD) are saved. Under the process conditions of retaining the two LDD ion injections of the N-type drain lightly doped (LDD) and the P-type drain lightly doped (LDD), the hot carrier effect performance of the NMOS tube is preferentially guaranteed, the substrate leakage current is greatly reduced, and the reliability test is passed. Not only the electrical performance of the semiconductor device is guaranteed, but also the purpose of saving the mask cost is achieved.

[0071] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0072] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Step S1, providing a substrate, on which a first active area and a second active area are defined by shallow trench isolation; Step S2, performing P-well ion implantation in the first active area; Step S3, forming a gate layer, sequentially forming a first gate oxide layer and a first gate layer on the substrate of the first active region; sequentially forming a second gate oxide layer and a second gate layer on the substrate of the second active region; Step S4, retaining the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; Performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region; Step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region under the same photomask; in the second active region, the implanted P-type drain lightly doped ions neutralize the N-type second lightly doped region and invert to finally form a P-type lightly doped region; Step S6, performing N-type ion heavy doping implantation on the first active region to form a source region and a drain region of the NMOS tube; Step S7, performing P-type ion heavy doping implantation on the second active region II to form a source region and a drain region of the PMOS tube.

2. The method for forming a semiconductor device according to claim 1, wherein: Step S3 specifically includes: forming a gate oxide material layer and a gate material layer sequentially covering the substrate; Forming an imaged second photoresist layer on the surface of the gate material layer, wherein the imaged second photoresist layer includes a second photoresist layer first region and a second photoresist layer second region; Using the second photoresist layer as a mask, the gate material layer and the gate oxide layer material layer are etched in sequence to form the first gate layer and the first gate oxide layer located below the first region of the second photoresist layer, and the second gate layer and the second gate oxide layer located below the second region of the second photoresist layer.

3. The method for forming a semiconductor device according to claim 2, wherein: When the maskless N-type drain lightly doped ion implantation is performed in step S4, the first region of the second photoresist layer and the second region of the second photoresist layer are still retained; After the maskless N-type drain lightly doped ion implantation is completed, the first region of the second photoresist layer and the second region of the second photoresist layer are removed.

4. The method for forming a semiconductor device according to claim 1, wherein: Step S5 specifically includes: A third photoresist layer is formed, wherein the third photoresist layer has an opening in the second active area and covers the first active area; using the third photoresist layer as a mask, the N-well ion implantation is first performed on the second active area to form an N-well; and then the P-type drain lightly doped ion implantation is performed on the second active area to form a P-type lightly doped area.

5. The method for forming a semiconductor device according to claim 4, wherein: In step S5, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.

6. The method for forming a semiconductor device according to claim 4, wherein: In step S5, the N-well ion implantation also passes through the second gate layer and the second gate oxide layer and enters the substrate below.

7. The method for forming a semiconductor device according to any one of claims 1 to 6, wherein: The operating voltage of the semiconductor device includes: 7V or 5V.

8. The method for forming a semiconductor device according to claim 1, wherein: After step S5 and before step S6, the forming method further includes: A first sidewall is formed on the substrate of the first active region, and the first sidewall covers the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, and the second sidewall covers the sidewalls of the second gate oxide layer and the second gate layer.

9. The method for forming a semiconductor device according to claim 8, wherein: After step S7, the forming method further includes: Forming metal silicide, forming the metal silicide on the surfaces of the first gate layer and the second gate layer, and the surfaces of the substrate of the first active region and the second active region; forming a dielectric layer, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall and the second gate layer; and forming a contact hole in the dielectric layer; Metal interconnection is formed, metal is filled in the contact hole, and the gate, source region and drain region of the NMOS tube and the PMOS tube are led out.

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