Low-cost three-part photovoltaic junction box

Abstract

The present invention belongs to the field of photovoltaic power generation technology, in particular to a low-cost three-part photovoltaic junction box, comprising left and right box bodies, small-sized wafers being installed inside the left and right box bodies, a middle box body, a large-sized wafer being installed inside the middle box body, a diode module, differentiated diode modules installed in the left and right box bodies and the middle box body, and a photovoltaic cable, wherein the photovoltaic cable is connected to the left and right box bodies, and the photovoltaic cable and the diode modules in the left and right box bodies are reliably electrically connected by resistance welding or riveting and then led out from the inside. Through the differentiated wafer size design, the production cost is greatly reduced, and the market competitiveness of the product is enhanced. The thermal conductivity of the cable is utilized to ensure that the junction temperature of each box body is consistent, and the international standard for photovoltaic junction boxes is met. This provides a new cost optimization solution for the photovoltaic industry and promotes technological progress in the industry.

Description

Technical Field

[0001] The invention belongs to the technical field of photovoltaic power generation, and specifically relates to a low-cost three-part photovoltaic junction box. Background Art

[0002] With the rapid development of the photovoltaic industry, cost control has become the key to improving product competitiveness. In the traditional three-body photovoltaic junction box design, diode modules of uniform specifications are installed in the left, middle and right boxes, making it difficult to further optimize costs. This patent aims to achieve balanced heat dissipation by rationally utilizing the thermal conductivity of photovoltaic cables, while significantly reducing production costs and meeting the cost reduction needs of the photovoltaic industry. Summary of the invention

[0003] The technical problem to be solved by the present invention is: how to obtain a photovoltaic junction box with the same performance and better cost by using differentiated wafers.

[0004] The technical solution of the present invention is as follows:

[0005] Low-cost three-part photovoltaic junction box, including:

[0006] Left and right boxes, with small-sized wafers installed inside the left and right boxes;

[0007] An intermediate box body, wherein a large-size wafer is installed inside the intermediate box body;

[0008] Diode modules, differentiated diode modules installed in left and right boxes and middle boxes;

[0009] Photovoltaic cable, the photovoltaic cable is connected to the left and right box bodies. The photovoltaic cable and the diode modules in the left and right box bodies are reliably electrically connected through resistance welding or riveting and then led out from the inside. The photovoltaic cable is used to directly export the electric energy generated inside the left and right box bodies. The photovoltaic cable is also used to serve as an additional heat dissipation path, using the high thermal conductivity of the copper core to disperse the heat of small-size wafers and large-size wafers.

[0010] In some embodiments, optionally, the diode module also includes an excellent diode module and a secondary diode module, the excellent diode module is installed in the middle box body, and the secondary diode module is installed in the left and right boxes. The excellent diode module is used for the middle box body without photovoltaic cable heat conduction, and the secondary diode module is used for the left and right boxes with photovoltaic cable heat conduction.

[0011] In some embodiments, optionally, a wafer processing process includes a trench process and a planar process;

[0012] The groove process is:

[0013] Step 1: By etching a series of deep and narrow trenches in the silicon wafer;

[0014] Step 2: Then fill with insulating material and metal;

[0015] Step 3: Let it stand for a while, and then a vertical current path will be formed;

[0016] Plane technology:

[0017] Step 1: Make the diode and transistor have a planar PN junction;

[0018] Step 2: The current then flows mainly along the surface of the silicon wafer.

[0019] In some embodiments, optionally, the combination of large-size wafers and small-size wafers includes but is not limited to the following combinations:

[0020] 1) Both large-size wafers and small-size wafers are trench / planar process wafers, and large-size wafers are larger than small-size wafers;

[0021] 2) Large-size wafers use trench technology, and small-size wafers use planar technology. Large-size wafers and small-size wafers are based on meeting technical requirements;

[0022] 3) The large-size wafer and the small-size wafer are of the same size and are made using the same process, but the grade of the photovoltaic module in which the small-size wafer is located is lower than the grade of the photovoltaic module in which the large-size wafer is located;

[0023] 4) Large-size wafers and small-size wafers are of the same size and are made with the same process, but they come from different wafer foundries or from different batches of the same manufacturer, so they have obvious performance differences and are purchased at different prices. The grade of photovoltaic modules containing small-size wafers is lower than that of photovoltaic modules containing large-size wafers.

[0024] The working principle and beneficial effects of the present invention are:

[0025] The present invention significantly reduces production costs and enhances product market competitiveness through differentiated wafer size design. It utilizes the thermal conductivity of cables to ensure that the junction temperature of each box is consistent, meeting international standards for photovoltaic junction boxes, providing a new cost optimization solution for the photovoltaic industry and promoting technological progress in the industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] Figure 1 It is a schematic diagram of the overall structural framework of the present invention;

[0028] Figure 2 This is a comparison diagram of junction temperature and forward voltage drop experiments of different process models from the same manufacturer in Example 3 of the present invention;

[0029] Figure 3This is a comparison diagram of junction temperature and forward voltage drop experiments of different manufacturers' models with the same process in Example 3 of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Example 1

[0032] like Figure 1-Figure 3 As shown, the low-cost three-part photovoltaic junction box includes:

[0033] Left and right boxes, with small-sized wafers installed inside the left and right boxes;

[0034] An intermediate box body, wherein a large-size wafer is installed inside the intermediate box body;

[0035] Diode modules, differentiated diode modules installed in left and right boxes and middle boxes;

[0036] Photovoltaic cable, the photovoltaic cable is connected to the left and right box bodies. The photovoltaic cable and the diode modules in the left and right box bodies are reliably electrically connected through resistance welding or riveting and then led out from the inside. The photovoltaic cable is used to directly export the electric energy generated inside the left and right box bodies. The photovoltaic cable is also used to serve as an additional heat dissipation path, using the high thermal conductivity of the copper core to disperse the heat of small-size wafers and large-size wafers.

[0037] The diode module also includes a superior diode module and a secondary diode module. The superior diode module is installed in the middle box body, and the secondary diode module is installed in the left and right boxes. The superior diode module is used for the middle box body without photovoltaic cable heat conduction, and the secondary diode module is used for the left and right boxes with photovoltaic cable heat conduction.

[0038] Specifically, the photovoltaic cable is connected to the diode modules in the left and right boxes by resistance welding or riveting, and then led out from the inside of the photovoltaic junction box. Therefore, the cable can directly conduct the heat generated by the photovoltaic module and serve as an additional heat dissipation path. The high thermal conductivity of the cable copper core can effectively disperse the heat generated by the wafer.

[0039] By comparing the thermal conductivity of the PPO shell of the photovoltaic junction box, the potting compound, the cable copper core, and the photovoltaic cable sheath, the rationality of the cable as a heat dissipation path can be confirmed. The thermal conductivity of the tinned copper core of the cable is about 380 W / (m·K), and the thermal conductivity of the XLPE (cross-linked polyethylene) of the photovoltaic cable sheath is relatively low, about 0.25 W / (m·K). The potting compound is about 0.1-0.3 W / (m·K). PPO is an engineering plastic with a thermal conductivity of about 0.2 W / (m·K).

[0040] Example 2

[0041] A wafer processing technology, including a groove process and a plane process;

[0042] The groove process is:

[0043] Step 1: By etching a series of deep and narrow trenches in the silicon wafer;

[0044] Step 2: Then fill with insulating material and metal;

[0045] Step 3: Let it stand for a while, and then a vertical current path will be formed;

[0046] Plane technology:

[0047] Step 1: Make the diode and transistor have a planar PN junction;

[0048] Step 2: The current then flows mainly along the surface of the silicon wafer.

[0049] Specifically, the trench process forms a vertical current path by etching a series of deep and narrow grooves on the silicon wafer and then filling it with insulating materials and metals. This can improve the current carrying capacity per unit area. The trench process allows current to flow in the vertical direction, thereby reducing the on-resistance of the device, improving efficiency and reducing conduction loss. Since the trench structure can more effectively conduct heat from the inside of the device to the surface, the trench process device usually has better thermal performance. The trench process is particularly suitable for applications that require high current density and fast switching speed, such as power converters, motor drives, etc.

[0050] Planar diodes and transistors have planar PN junctions, and current flows mainly along the surface of the silicon wafer. This structure is simple and easy to manufacture. Planar devices usually have higher on-resistance because the current path is longer, the lateral diffusion resistance is larger, and the planar structure has a longer thermal path, which may lead to poor thermal performance, especially in high-power applications. Planar technology is suitable for lower power applications and applications that do not require extreme performance because it is low cost and the manufacturing process is relatively simple.

[0051] Example 3

[0052] The combination of large-size wafers and small-size wafers includes but is not limited to the following combinations:

[0053] 1) Both large-size wafers and small-size wafers are trench / planar process wafers, and large-size wafers are larger than small-size wafers;

[0054] 2) Large-size wafers use trench technology, and small-size wafers use planar technology. Large-size wafers and small-size wafers are based on meeting technical requirements;

[0055] 3) The large-size wafer and the small-size wafer are of the same size and are made using the same process, but the grade of the photovoltaic module in which the small-size wafer is located is lower than the grade of the photovoltaic module in which the large-size wafer is located;

[0056] 4) Large-size wafers and small-size wafers are of the same size and are made with the same process, but they come from different wafer foundries or from different batches of the same manufacturer, so they have obvious performance differences and are purchased at different prices. The grade of photovoltaic modules containing small-size wafers is lower than that of photovoltaic modules containing large-size wafers.

[0057] More specifically, the cost comparison between the trench process and the planar process is that the cost is relatively high due to the high process complexity and the need for high-precision equipment and technology. The trench process can provide higher cell density and lower on-resistance, which is particularly important in high-performance power devices, but it also means higher manufacturing costs. The planar process is relatively simple and low-cost, and is suitable for some applications that do not require particularly high performance. The planar process has a long history in semiconductor manufacturing and mature technology, so it has advantages in cost and reliability. Although the trench process is more expensive than the planar process, due to its significant advantages in improving device performance and power density, its demand in specific application areas such as high-performance power devices continues to grow. With the advancement of technology and further reduction of costs, the application scope of the trench process is expected to be further expanded;

[0058] In addition, the performance and cost of the wafer also need to consider the impact of chip size. A larger chip size means a larger cross-sectional area, which can allow higher current to pass through, resulting in better current carrying capacity and lower on-resistance. This is because the current density is more evenly distributed on a larger chip, reducing the risk of hot spots and local overheating.

[0059] For example, excluding the influence of other interference factors, for chips made with the same process, large-size chips have better electrical and heat dissipation performance than small-size chips. For example, it can be considered that 165mil groove chips have better performance than 150mil groove chips, and the purchase price is also higher;

[0060] However, despite the above-mentioned principle facts, in daily practice, there are often huge differences. The difference in wafer performance usually comes from the process level, technical routes and product batches of different wafer manufacturers. In the process of packaging and testing photovoltaic modules, the process of packaging wafers into photovoltaic modules will introduce more influencing factors, which will cause the performance differences of the final diode module products.

[0061] Based on the above facts, we use the photovoltaic module packaging MES system to control the batch performance of wafer packaging and the photovoltaic module testing stage. We test and grade the finished photovoltaic modules based on the wafer batch performance. Generally, the lower the grade, the lower the price of the module.

[0062] Specifically, at least the following three feasible material matching solutions are determined through experiments to ensure that the product meets the international standards for photovoltaic junction boxes.

[0063] Specific implementation plan:

[0064] Solution 1: The left and right boxes use dual-core 120 trench process diode wafers, and the middle box uses dual-core 130 trench process diode wafers, which are suitable for 30A photovoltaic junction boxes.

[0065] Solution 2: The left and right boxes use single-core 150 trench process diode wafers, and the middle box uses single-core 165 trench process diode wafers, which are suitable for 28A photovoltaic junction boxes.

[0066] Solution 3: The left and right boxes use single-core 120 trench process diode wafers, and the middle box uses single-core 130 trench process diode wafers, which are suitable for 25A photovoltaic junction boxes.

[0067] The present invention realizes the innovative design of a low-cost three-part photovoltaic junction box through differentiated wafer size design and optimized cable heat conduction path. It can not only meet the cost reduction needs of the photovoltaic industry, but also ensure the electrical performance and heat dissipation performance of the product. It complies with the international standards for photovoltaic junction boxes and has important market value and application prospects.

Claims

1. Low-cost three-part photovoltaic junction box, characterized by: include: Left and right box bodies, wherein small-sized wafers are installed inside the left and right box bodies; An intermediate box body, wherein a large-size wafer is installed inside the intermediate box body; Diode module, the differentiated diode modules installed in the left and right boxes and the middle box, the diode module also includes a superior diode module and a secondary diode module, the superior diode module is installed in the middle box, the secondary diode module is installed in the left and right boxes, the superior diode module is used for the middle box without photovoltaic cable heat conduction, and the secondary diode module is used for the left and right boxes with photovoltaic cable heat conduction; Photovoltaic cables, which are connected to the left and right boxes. The photovoltaic cables are reliably electrically connected to the diode modules in the left and right boxes by resistance welding or riveting and then led out from the inside. The photovoltaic cables are used to directly lead out the electric energy generated inside the left and right boxes. The photovoltaic cables are also used to serve as an additional heat dissipation path, using the high thermal conductivity of the copper core to disperse the heat of the small-sized wafers and the large-sized wafers. Among them, the size in small-size wafer and large-size wafer refers to the chip size. Large-size chips allow higher current to pass through, have better current carrying capacity and lower on-resistance.

2. The low-cost three-part photovoltaic junction box according to claim 1 is characterized in that: The combination of the large-size wafer and the small-size wafer includes the following combinations: The large-size wafer and the small-size wafer are both trench or planar process wafers, and the large-size wafer is larger than the small-size wafer; Or if the two groups of wafers are of the same size and are made by the same process, a larger-sized wafer with a higher grade of the photovoltaic module is used as a substitute, and a smaller-sized wafer with a lower grade of the photovoltaic module is used as a substitute; Or two groups of wafers have the same size and are made by the same process, but have obvious performance differences and different costs. The larger wafers are replaced by the ones with better performance, and the smaller wafers are replaced by the ones with worse performance. The performance differences come from the process levels of different wafer manufacturers or different batches of the same manufacturer. Or the two groups of wafers have the same size but different wafer processing techniques. The large-size wafers made using the trench process will be replaced, while the small-size wafers made using the planar process will be replaced.

3. The low-cost three-part photovoltaic junction box according to claim 2 is characterized in that: The trench process is: Step 1: By etching deep and narrow trenches in the silicon wafer; Step 2: Then fill with insulating material and metal; Step 3: Let it stand, and then a vertical current path will be formed; The planar process: Step 1: Make the diode and transistor have a planar PN junction; Step 2: Current then flows along the surface of the silicon wafer.

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