A display panel driving method, a display device, and a display panel

Abstract

The embodiments of the present application provide a display panel driving method, a display device, and a display panel. The display panel driving method includes: when switching from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-uniform width pulse PWM signal, where the non-uniform width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses, both the first type pulses and the second type pulses are first level signals, the pulse width of the first type pulses is greater than the pulse width of the second type pulses, and the pulse width of the first type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; using the non-uniform width pulse PWM signal to scan the pixel circuits of each row in the display panel. Through the plurality of first type pulses and the plurality of second type pulses included in the non-uniform width pulse PWM signal, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM, and the flicker problem during the switching between high-frequency PWM dimming and DC dimming can be reduced.

Description

[0001] This application is a divisional of the Chinese patent application with application number 202310839356.3 filed on July 7, 2023, and invention name “A display panel driving method, display device and display panel”, all contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel driving method, a display device and a display panel. Background Art

[0003] In the traditional PWM (Pulse Width Modulation) dimming scheme, when the OLED (Organic Light Emitting Diode) screen uses the PMOS (positive channel Metal Oxide Semiconductor) process, all EM (light-emitting control signals) high levels are set to be consistent with the first approximation. This setting is relatively simple to implement and easy to control logically. However, with the improvement of high-frequency PWM specifications, the implementation of the new LTPO (Low Temperature Polycrystalline Oxide) scheme (with reset in the middle holding area and limited EM width) or the reduction of the vertical resolution of some special products, the proportion of high-level EM signals increases, and the duty cycle of PWM dimming becomes smaller. In high-brightness DC dimming (changing the brightness of the screen by increasing or decreasing the power of the screen panel circuit), the proportion of high-level EM signals is very small, and the proportion of low-level signals is relatively large. Therefore, the duty cycle of DC dimming is usually very high, see Figure 3 If the duty of high-frequency PWM dimming is too small, the flicker problem will increase when switching with DC dimming during the dimming process. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a display panel driving method, a display device and a display panel to reduce the flicker problem when switching between high-frequency PWM dimming and DC dimming. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel driving method, the method comprising:

[0006] When converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated. The non-uniform width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses. The first type pulses and the second type pulses are both first level signals. The pulse width of the first type pulses is greater than the pulse width of the second type pulses, and the pulse width of the first type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel.

[0007] Use the non-uniform width pulse PWM signal to scan each row of pixel circuits in the display panel.

[0008] In a possible implementation, for each frame of the non-uniform width pulse PWM signal, the frame of the non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one of the first type pulses and a plurality of the second type pulses.

[0009] In a possible implementation, the pulse width of the first type pulses is the minimum level width for scanning or resetting the pixel circuits in the display panel, and the pulse width of the second type pulses is the minimum width required for the display panel timing.

[0010] In a possible implementation, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type pulses.

[0011] In a possible implementation, the method further includes:

[0012] Obtain the number of pulses within each refreshed image frame, the pulse width of the first type pulses, the pulse width of the second type pulses, and obtain the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit;

[0013] Determine the number and timing of the first type pulses according to the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type pulses, where the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type pulses, and the timing of the first type pulses is evenly arranged within the time of one image frame;

[0014] Divide one image frame into n sub-timing signals according to the number and timing of the first type pulses, where n is the number of the first type pulses. For each sub-timing signal, the sub-timing signal includes one first type pulse and is located at the timing head of the sub-timing signal;

[0015] Determine the timing and quantity of the second type of pulses in each segment of the sub-timing signal according to the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, so as to obtain the generation parameters of the PWM signal; wherein, the generation parameters include the timing of the first type of pulses, the timing and quantity of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal.

[0016] When converting from the DC dimming mode to the pulse width modulation (PWM) dimming mode, generating a non-uniform width pulse PWM signal includes:

[0017] When converting from the DC dimming mode to the pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

[0018] In a possible implementation manner, after scanning each row of pixel circuits in the display panel by using the non-uniform width pulse PWM signal, the method further includes:

[0019] Increase the pulse width of the second type of pulses in the non-uniform width pulse PWM signal by a preset width according to a preset scanning period to obtain the current PWM signal;

[0020] Scan each row of pixel circuits in the display panel by using the current PWM signal;

[0021] Return to execute the step: increase the pulse width of the second type of pulses in the non-uniform width pulse PWM signal, or increase the pulse widths of the first type of pulses and the second type of pulses in the non-uniform width pulse PWM signal according to a preset scanning period to obtain the current PWM signal until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0022] In a possible implementation manner, the method further includes:

[0023] In the PWM dimming mode, generate a second non-uniform width pulse PWM signal in a first brightness scenario, wherein the second non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses;

[0024] Scan each row of pixel circuits in the display panel by using the second non-uniform width pulse PWM signal;

[0025] When switching from the first brightness scenario to the second brightness scenario, generate a third non-uniform width pulse PWM signal, wherein the third non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses;

[0026] Scan each row of pixel circuits in the display panel by using the third non-uniform width pulse PWM signal;

[0027] Among them, the brightness of the scanned image in the first brightness scenario is greater than that of the scanned image in the second brightness scenario; the number of the second type of pulses in the second non-uniform-width pulse PWM signal is less than the number of the second type of pulses in the third non-uniform-width pulse PWM signal, and the total width of the second type of pulses in the second non-uniform-width pulse PWM signal is greater than the total width of the second type of pulses in the third non-uniform-width pulse PWM signal.

[0028] In a second aspect, an embodiment of the present application provides a display device, and the display device includes a display panel and a display driving chip:

[0029] The display panel includes a display module, and the display module includes multiple rows of pixel rows, and each row of pixel rows includes multiple pixel circuits;

[0030] The display driving chip is configured to: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generate a non-uniform-width pulse PWM signal, where the non-uniform-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; use the non-uniform-width pulse PWM signal to scan the pixel circuits in each pixel row of the display panel;

[0031] The display module is configured to: in response to the scanning of the non-uniform-width pulse PWM signal, drive the pixel circuits in each pixel row.

[0032] In a possible implementation manner, for each frame of non-uniform-width pulse PWM signal, the frame of non-uniform-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

[0033] In a possible implementation manner, the pulse width of the first-type pulses is the minimum level width for scanning or resetting the pixel circuits in the display panel, and the pulse width of the second-type pulses is the minimum width required for the timing of the display panel.

[0034] In a possible implementation manner, the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit are within the timing of the first-type pulses.

[0035] In a possible implementation manner,

[0036] The display driving chip is further configured to obtain the number of pulses within each frame of image refreshed, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and obtain the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timings of the first type of pulses according to the timings of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, wherein the timings of the reset signal, initialization signal, charging signal, and reset compensation signal are within the timings of the first type of pulses, and the timings of the first type of pulses are evenly arranged within the time of one frame of image; divide one frame of image into n sub-timing signals according to the number and timings of the first type of pulses, where n is the number of the first type of pulses, and for each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the head of the timing of the sub-timing signal; determine the timings and number of the second type of pulses in each sub-timing signal according to the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timings and number of the first type of pulses and the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signals.

[0037] Specifically, the display driving chip is configured to: when converting from the DC dimming mode to the pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

[0038] In a possible implementation manner, the display driving chip is further configured to:

[0039] According to a preset scanning period, increase the pulse width of the second type of pulses in the non-uniform width pulse PWM signal by a preset width to obtain the current PWM signal; scan each row of pixel circuits in the display panel with the current PWM signal; return to execute the step: according to the preset scanning period, increase the pulse width of the second type of pulses in the non-uniform width pulse PWM signal, or increase the pulse widths of the first type of pulses and the second type of pulses in the non-uniform width pulse PWM signal, to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0040] In a possible implementation manner, the display driving chip is further configured to:

[0041] In the PWM dimming mode, in the first brightness scenario, a second non-uniform-width pulse PWM signal is generated, where the second non-uniform-width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses; the second non-uniform-width pulse PWM signal is used to scan the pixel circuits in each row of the display panel; after switching from the first brightness scenario to the second brightness scenario, a third non-uniform-width pulse PWM signal is generated, where the third non-uniform-width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses; the third non-uniform-width pulse PWM signal is used to scan the pixel circuits in each row of the display panel; wherein, the brightness of the scanned image in the first brightness scenario is greater than the brightness of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform-width pulse PWM signal is less than the number of second-type pulses in the third non-uniform-width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform-width pulse PWM signal.

[0042] In a third aspect, an embodiment of the present application further provides a display panel, where the display panel includes:

[0043] a driving module and a display module, the display module includes multiple pixel rows, and each pixel row includes a plurality of pixel circuits;

[0044] The driving module is configured to: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generate a non-uniform-width pulse PWM signal, where the non-uniform-width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; use the non-uniform-width pulse PWM signal to scan the pixel circuits in each pixel row of the display panel;

[0045] The display module is configured to: in response to the scanning of the non-uniform-width pulse PWM signal, drive the pixel circuits in each pixel row.

[0046] Advantageous effects of the embodiments of the present application:

[0047] A display panel driving method, a display device, and a display panel provided by an embodiment of the present application. The display panel driving method includes: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-uniform width pulse PWM signal, where the non-uniform width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses, both the first type pulses and the second type pulses are first level signals, the pulse width of the first type pulses is greater than the pulse width of the second type pulses, and the pulse width of the first type pulses is not less than the minimum level width for scanning or resetting pixel circuits in the display panel; using the non-uniform width pulse PWM signal to scan each row of pixel circuits in the display panel. Through the plurality of first type pulses and the plurality of second type pulses included in the non-uniform width pulse PWM signal, in the case of high-frequency PWM, the duty cycle of PWM dimming can be increased, and the flicker problem during the switching between high-frequency PWM dimming and DC dimming can be reduced.

[0048] Of course, implementing any product or method of the present application does not necessarily require achieving all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0050] Figure 1 It is a schematic structural diagram of a 7T1C pixel circuit in the related art;

[0051] Figure 2a It is a schematic diagram of the scanning of a display panel Panel in the related art;

[0052] Figure 2b It is a schematic diagram of PWM dimming in the related art;

[0053] Figure 2c It is a schematic diagram of DC dimming in the related art;

[0054] Figure 3 It is a schematic diagram of the timing sequence of PWM dimming and DC dimming in the related art;

[0055] Figure 4a It is a first flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0056] Figure 4b It is a schematic diagram of a timing sequence of an EM signal of high-frequency non-uniform width pulse PWM dimming provided by the embodiment of the present application;

[0057] Figure 5 It is the second flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0058] Figure 6a It is the third flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0059] Figure 6b It is the schematic diagram of the switching between high-frequency PWM dimming and DC dimming;

[0060] Figure 6c It is another timing schematic diagram of the EM signal of high-frequency non-uniform pulse PWM dimming provided by the embodiment of the present application;

[0061] Figure 7 It is the timing schematic diagram of the scanning signal and the reset compensation signal of high-frequency non-uniform pulse PWM dimming provided by the embodiment of the present application;

[0062] Figure 8a It is the fourth flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0063] Figure 8b It is the timing schematic diagram of PWM dimming in two different scenarios;

[0064] Figure 9 It is a schematic structural diagram of the display device provided by the embodiment of the present application;

[0065] Figure 10 It is the first schematic structural diagram of the display panel provided by the embodiment of the present application;

[0066] Figure 11 It is the second schematic structural diagram of the display panel provided by the embodiment of the present application. Detailed implementation manners

[0067] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0068] First, a brief introduction to the display device in the related art is given. The display device in the related art includes a display panel and a display driving chip. The display panel includes a display module, and the display module includes multiple pixel rows. Each pixel row includes multiple pixel circuits. The display driving chip is used to: in the Pulse Width Modulation (PWM) dimming mode, generate an equal-width pulse PWM signal (EM signal), and use the equal-width pulse PWM signal to scan the pixel circuits in each pixel row of the display panel; the display driving chip is also used to: in the DC dimming mode, generate an EM signal with a higher low-level occupancy ratio, and use this EM signal to scan the pixel circuits in each pixel row of the display panel.

[0069] Next, a brief introduction to PWM dimming in the related art is given. Due to the light-emitting principle and characteristics of current-driven OLED (Organic Light Emitting Diode), the current corresponding to low brightness and low gray levels is very small, resulting in poor color and brightness uniformity of the image, and serious problems such as color deviation and mura (referring to the phenomenon of uneven brightness of the display, causing various traces). To solve the above problems, current OLED screens in the industry use PWM dimming at low brightness and can use DC dimming (changing the brightness of the screen by increasing or decreasing the power of the screen panel circuit) at high brightness. However, the traditional low-frequency PWM dimming in the past may have an adverse effect on the human eye when watching the screen for a long time. To solve this problem, a high-frequency PWM scheme has emerged in the industry. Generally, the higher the PWM frequency, the smaller the impact on the human eye, and the more eye-protective it is. With the improvement of demand and the development of technology, PWM evolves towards a higher frequency direction. However, for higher-frequency PWM dimming, the risk of flicker increases correspondingly when switching with low-frequency PWM dimming / high-brightness DC dimming, which needs to be optimized and solved.

[0070] To facilitate the description of the problems existing in the related art, some basic concepts are briefly introduced as follows:

[0071] GOA signal: GOA stands for Gate Drive On Array, which is a signal used to control the gate scan. Through timing configuration, the scanning time h of each pixel row and the durations of VBP (Vertical Back Porch, the back shoulder of the vertical synchronization signal, representing the number of invalid rows after the vertical synchronization signal at the start of a frame of image) and VFP (Vertical Front Porch, the front shoulder of the vertical synchronization signal, representing the number of invalid rows before the vertical synchronization signal at the end of a frame of image) of each frame of image can be set.

[0072] EM (PWM) signal: That is, the signal used to control the lighting of the OLED, see Figure 1The shown 7T1C (7 Thin Film Transistors (TFTs), 1 capacitor) pixel circuit, where ELVDD is the positive power supply voltage, ELVSS is the negative power supply voltage, Cst is the storage capacitor, Vdata is the data signal, Scan1, Scan2, and Scan3 are the scan signals, and Vref is the reset signal. For each pixel, after charging is completed, the driving TFT, i.e., transistor T3, remains in the on state all the time. At this time, the lighting / turning off of the OLED is controlled by the EM signal. Usually, the so-called DC dimming means that the EM signal is always in the on state, and PWM dimming means that the EM signal is modulated to control the pixel brightness according to a set frequency, i.e., on - off - on - off.

[0073] Principle of PWM (EM) dimming: Due to the current-driven light-emitting principle of OLEDs, the process consistency of different pixel TFTs cannot be guaranteed at low brightness, resulting in problems such as mura and color deviation caused by different pixel brightnesses. Therefore, PWM dimming is basically used at low brightness of OLEDs, that is, by maintaining a certain TFT driving voltage (current), and adjusting the OLED light-emitting brightness through the duty cycle of the EM signal, namely the so-called bright - dark - bright - dark ratio.

[0074] Scanning time h for each row of the display panel Panel: When the panel is working, it is usually controlled by a DDIC (Display Driver IC) to drive the relevant GOA, EM, and TFT timings of the panel according to a certain timing sequence to complete actions such as reset, initialization, charging, and light emission. The scanning of each row of pixel rows has precise hardware timing control, and the required duration for each row can be set through the internal clock of the IC. This duration is called the row scanning h. For example, for a screen with a resolution of 1200×2800×120hz, assuming that the total VFP and VBP in the frame interval porch area is 80 h (which can be flexibly set according to different product requirements in practice), then the approximate duration of h is h = 1 / 120 / (2800 + 80) = 2.894 us.

[0075] In current OLED displays, the duration ratio of the low level of EM is generally defined as the EM duty cycle (EM duty), hereinafter collectively referred to as duty. It should be noted here that if the PMOS process is used for the OLED screen, the high level of the EM signal corresponds to the turning off of the OLED, and the low level of the EM signal corresponds to the lighting of the OLED; if the NMOS (Negative channel-Metal-Oxide-Semiconductor) process is used for the OLED screen, the high level of the EM signal corresponds to the lighting of the OLED, and the low level of the EM signal corresponds to the turning off of the OLED, and the PMOS process is usually used for the current OLED screen. Calculation of the duty cycle of PWM(EM): The high and low level durations of PWM are usually calculated by the number of h. The duration width of the black insertion (high level, turning off the OLED) of each EM signal is x*h, and the duration width of the lighting area (effective level) of each EM signal is y*h. Then x + y = the total number of pixel rows + VBP + VFP, and the EM light emission duty cycle duty = the total duration of the EM lighting area / the total duration of each frame * 100% = 1 - x*h / (the total number of pixel rows + VBP + VFP)*h * 100% = 1 - x / (the total number of pixel rows + VBP + VFP) * 100%. As Figure 2a , Figure 2b and Figure 2c shown, for example, for a screen with a resolution of 1200×2800×120hz, assuming that VFP and VBP total 80 h in total, then the duty of the EM lighting is approximately 1 - (x / (2800 + 80)) × 100%. Thus, it can be seen that the wider the black insertion of the EM signal within one frame, the smaller the duty, and the darker the screen brightness, and vice versa. The duty in the DC dimming range can usually reach more than 90%, or even more than 98%. Due to the increasingly high PWM specifications and the use of LTPO, the duty in the PWM dimming range is getting lower and lower.

[0076] OLED screens usually perform progressive scanning (including reset, initialization, charging, light emission, etc.). For each row of pixels, the reset, initialization, charging, etc. operations are usually completed at the high level (no light emission) of the first EM signal. See Figure 1 . For the signals for reset, initialization, and charging operations, several scan operation signals need to be used respectively, such as Scan1, Scan2, Scan3 (it should be noted that the number of scan signals may be 2, 3, 4, or 5 signals, and the number of scan signals is different for different circuit architectures). This requires a relatively wide width of the corresponding EM signal to wrap these scan signals within the time range. For other EM signals in the non-scanning charging interval, usually meeting the minimum requirements of the Panel circuit is sufficient. As Figure 3As shown, EM-1 is the DC EM signal waveform of the highlighted interval, and EM-2 is the EM signal waveform of PWM in the low-light interval. The first EM pulse duration is required to be longer. In the PWM dimming in the related art, the high level of all EM signals is usually set to be approximately the same as the first one. Because in the actual duty adjustment process, for the width of some EM high levels, there will be a certain regular fine-tuning. Taking 120hz with 12Pulse (12 pulses) as an example for illustration. For example, if one step is adjusted by 4h, then this 4h is usually added to the first EM high level, so the first EM high level will be 4h longer than the others; if it is adjusted by 8h, it is usually added to the first EM high level and the seventh EM high level, so the widths of the first EM high level and the seventh EM high level are slightly wider. The increased EM high level duration is usually evenly distributed to the 12 Pulses as much as possible in terms of time and scanning space. Therefore, the high level of the EM signal is approximately the same as the first EM high level, and the difference is not too large, and there is no obvious special setting for a wider EM. This setting is relatively simple to implement and the logic control is also easy. However, with the improvement of the high-frequency PWM specifications, such as 2160, 3840hz, etc., and the implementation of the new LTPO scheme (there is a reset in the intermediate holding area and the EM width is limited) or the reduction of the vertical resolution of some special products, etc., the duty of the PWM dimming becomes smaller. The duty of the DC dimming is usually very high when it is highlighted. If the duty of the high-frequency PWM dimming is too small, the flickering risk increases when switching between DC dimming and PWM dimming during the dimming process, or in some specific low-frequency PWM dimming scenarios, the proportion of the high level of the EM signal is smaller than that of the high-frequency PWM dimming. Therefore, the lighting duty of the low-frequency PWM dimming is larger than that of the high-frequency PWM dimming. When switching with the high-frequency PWM dimming, there will also be a relatively serious flickering problem due to the too large duty difference.

[0077] For example, referring to Figure 3 , if the DC dimming is 1pulse (pulse) of PWM, and the PWM dimming is 4pulse, and the blanking width of each PWM is calculated as 40h, and the duration width within one frame is 2800 + 80 = 2880h, then the duty of the 4pulse PWM dimming = 1 - (40 * 4 / 2880) * 100% = 94.4%, and the duty of the DC dimming = 1 - (40 * 1 / 2880) * 100% = 98.6%. The difference between the two is very small, and the flickering is weak when switching. If the PWM dimming becomes 32pulse (it may be higher), at this time, the duty of the PWM dimming = 1 - (40 * 32 / 2800) * 100% = 55.6%, and the DC is still 98.6%. At this time, the flickering problem during switching is aggravated.

[0078] In order to increase the duty cycle of high-frequency PWM dimming and reduce the flicker problem during the switching between high-frequency PWM dimming and DC dimming / low-frequency PWM dimming, the embodiments of the present application provide a display panel driving method. Refer to Figure 4a , which includes the following steps:

[0079] Step S401: When converting from the direct current (DC) dimming mode to the pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal. The non-uniform width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel.

[0080] Referring to the description in the above related technology, if the OLED screen uses the PMOS process, the first-level signal in step S401 is a high-level signal. If the OLED screen uses the NMOS process, the first-level signal in step S401 is a low-level signal. The examples and explanations in the subsequent embodiments are based on the PMOS process for the OLED screen, and no further explanation will be given in the subsequent embodiments.

[0081] In one example, refer to Figure 4b , EM-3 is a schematic diagram of the EM signal waveform of low-frequency PWM dimming in the related technology, and EM-4 is a schematic diagram of the EM signal waveform of high-frequency non-uniform width pulse PWM dimming provided by the embodiments of the present application (taking the PMOS process for the OLED screen as an example). Figure 4b In, EM-4 can be a 32-pulse high-frequency PWM timing. The first EM pulse and the 17th EM pulse can be first-type pulses. The first-type pulses can be high-level signals. The pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel. In one example, the minimum level width can be 80h, and it can be flexibly set according to the actual display panel product. The other 30 EM pulses can be second-type pulses, and the second-type pulses can be high-level signals.

[0082] Step S402: Use the non-uniform width pulse PWM signal to scan each row of pixel circuits in the display panel.

[0083] In the embodiments of the present application, through the plurality of first-type pulses and the plurality of second-type pulses included in the non-uniform width pulse PWM signal, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM.

[0084] In a possible implementation, for each frame of non-uniform-width pulse PWM signal, the frame of non-uniform-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one of the first type of pulses and multiple second type of pulses.

[0085] In one example, referring to Figure 4b , each frame of non-uniform-width pulse PWM signal may include two sub-timing signals, and each sub-timing signal may include 1 first type of pulse and 16 second type of pulses.

[0086] In a possible implementation, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

[0087] In one example, referring to Figure 4b , the level width of the first EM pulse and the level width of the 17th EM pulse can be 80h, or 85h, or 75h, and can be flexibly set according to the actual product. The level widths of the other 30 EM pulses can be 16h, or 4h, or 8h, etc., and can be flexibly set according to the actual product. It should be noted that the above examples are for the case when the pulse widths of the first type and the second type are in the minimum state (i.e., the brightest state of PWM dimming).

[0088] In a possible implementation, referring to Figure 5 , based on Figure 4a , the display panel driving method further includes the following steps:

[0089] Step S501, according to a preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal by a preset width to obtain the current PWM signal.

[0090] Step S502, use the current PWM signal to scan each row of pixel circuits in the display panel.

[0091] Step S503, return to execute Step S501: according to a preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal, or increase the pulse widths of the first type of pulses and the second type of pulses in the non-uniform-width pulse PWM signal to obtain the current PWM signal until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0092] The PWM interval is usually duty dimming. As the brightness decreases, the high level of the second type of pulse will gradually increase. Generally, at the lowest brightness, such as 2 nit, the duty will drop to about 10%. At this time, all the second type of pulses may have the same width as the first type of pulses, such as 1 - 80 * 32 / 2880 = 16.67%. That is, in the low-brightness interval of high-frequency PWM dimming, the first type of pulse and the second type of pulse may be the same or similar. After the first type and the second type of pulses reach the same or approximate width, when the brightness is further adjusted downward, these two types of pulses can be regarded as one type. As the brightness is adjusted, the EM width is adjusted in the smallest step (such as adding 4h each time).

[0093] During the PWM dimming process, as the brightness decreases, the EM duty will decrease accordingly, and the widths of the first type and the second type of pulses will increase according to certain rules. For example, according to the panel (display panel) design, the duration is increased by 4h each time. The increased EM will be evenly distributed to each EM as much as possible in the duration position. In this way, at a lower brightness, the widths of the first type and the second type of pulses may be the same or approximately the same, which is not fixed. In an example, as the brightness decreases, in a certain state, the widths of the first type and the second type both reach 80h after adjustment. At this time, the EM duty = 1 - (80 * 32) / 2880 * 100% = 11.11%. Of course, if the minimum width of the first type of pulse is 70h, or lower, or the number of EM Pulses is relatively small, when the widths of the first type of pulse and the second type of pulse are the same, the duty is still relatively high, such as 30%. Then, as the brightness decreases, the duty will continue to decrease, that is, the EM width will continue to increase in a step (spacing) of 4h. At this time, the widths of the first type and the second type of pulses will break through the originally set 70h.

[0094] In a possible implementation manner, the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit are within the timing of the first type of pulse.

[0095] In a possible implementation manner, refer to Figure 6a , based on Figure 4a , the display panel driving method further includes the following steps:

[0096] Step S601, obtaining the number of pulses within each frame of the refreshed image, the pulse width of the first type of pulse, the pulse width of the second type of pulse, and obtaining the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit.

[0097] Step S602: Determine the number and timing of the first type of pulses according to the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, where the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame.

[0098] Step S603: Divide one image frame into n sub-timing signals according to the number and timing of the first type of pulses, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse, and the first type of pulse is located at the head of the timing of the sub-timing signal.

[0099] Step S604: Determine the timing and number of the second type of pulses in each sub-timing signal according to the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, to obtain the generation parameters of the PWM signal; where the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signals.

[0100] Step S605: When converting from the DC dimming mode to the pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

[0101] In an example, based on the description of the calculation method of the PWM dimming duty ratio in the above related technology, still taking Figure 4bFor example, each frame of PWM signal can be divided into two sub-timing signals. Each sub-timing signal can include 1 first-type pulse and 16 second-type pulses, and the first-type pulse is located at the head of the timing. Therefore, EM-4 can be a high-frequency PWM timing of 32 pulses. Set the high-level width of the 1st EM pulse and the high-level width of the 17th EM pulse to the minimum level width required for pixel circuit scanning, which can be 80h. Set the high-level widths of the other 30 EM pulses to the minimum width required for the display panel timing, which can be 16h. Taking a total frame duration of 2900h as an example, when in high-brightness DC dimming, the duty cycle duty is 1 - (80 * 2 / 2900) * 100% = 94.5%. When in low-brightness high-frequency PWM dimming, the duty cycle duty is 1 - {(80 * 2 + 16 * 30) / 2900} * 100% = 77.9%. According to the low-brightness high-frequency PWM dimming method in the above related technology, the calculated duty cycle duty is 1 - {(40 * 32) / 2900} * 100% = 55.9%. It can be seen that the non-uniform-width pulse PWM signal provided by the embodiments of the present application can increase the lighting duty cycle, reduce the difference in duty cycle when switching with high-brightness DC dimming, and can weaken the flicker problem when switching between high-frequency PWM dimming and DC dimming. The schematic diagram of the switching between high-frequency PWM dimming and DC dimming is as Figure 6b shown, where nit, that is, nits is the unit of display brightness. Similarly, the flicker problem when switching between high-frequency PWM dimming and low-frequency PWM dimming can also be weakened.

[0102] In one example, for Figure 4b the non-uniform-width pulse PWM signal shown, it can also be an equally spaced 2-equal division setting, that is, each frame of PWM signal is divided into 2 sub-timing signals. For example, it can be 2 pulses in high-brightness DC dimming, and can be 24 pulses, 30 pulses or 36 pulses in low-brightness high-frequency PWM dimming. The high-level widths of the 1st EM pulse and the (24 / 3)*n + 1th, (30 / 3)*n + 1th, (36 / 3)*n + 1th (n = 1, 2, 3...) EM pulses can be set to the minimum level width required for pixel scanning, and the high-level widths of the other EM pulses are set to the minimum width required for the display panel timing. Similarly, it can also be set to different divisions such as 4-equal division, 5-equal division, 6-equal division according to actual needs. The present application does not make specific limitations on this.

[0103] It should be noted that Figure 4b is only a schematic diagram. At different actual refresh rates, the first-type pulses can also be equally periodically extended within the same base frequency of 120hz. For example, there are 2 equally periodic first-type pulses within 120hz, and 4 equally periodic first-type pulses within 60hz, asFigure 6c As shown, other refresh rates are similar.

[0104] The setting of the PWM signal with non-uniform pulse widths can also be well combined with LTPO scanning and reset compensation. It can not only reduce the duty of the high-frequency PWM but also meet the timing requirements of reset and compensation in the non-scanning area. For example, some LTPS (Low Temperature Poly-Silicon) or LTPO use 8T1C (8 TFTs, 1 capacitor) pixel circuits. After charging is completed, there will be a reset compensation operation for the T3 transistor (the same as the Figure 1 7T1C pixel circuit shown here) during the holding period. These reset compensations also require a certain period of high-level EM. Using the setting of the PWM signal with non-uniform pulse widths can just make the reset compensation operation occur during these relatively wide high-level EMs. As Figure 7 shown, the scanning operation is completed during the first wide high-level EM of each sub-timing, and the reset compensation can be carried out during the equally divided wide high-level EMs in the holding period.

[0105] In the setting of the PWM signal with non-uniform pulse widths in the above embodiments, the relatively wide EM Pulses are distributed at equally divided positions in the time domain according to a certain period. This can be well combined with some operations of the OLED that require reset and compensation during the holding period. In addition, the relatively wide non-uniform EM pulses can also be adjusted to non-equally divided positions according to actual needs. In this way, the wide-level EMs can be distributed in different frequency domains, dispersing the frequency domain energy of the inserted black, which is beneficial to eye protection.

[0106] The embodiment of the present application also provides a display panel driving method. Refer to Figure 8a , including the following steps:

[0107] Step S801, in the PWM dimming mode, in the first brightness scene, generate a second non-uniform pulse PWM signal, where the second non-uniform pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses;

[0108] Step S802, use the second non-uniform pulse PWM signal to scan each row of pixel circuits in the display panel;

[0109] Step S803, when switching from the first brightness scene to the second brightness scene, generate a third non-uniform pulse PWM signal, where the third non-uniform pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses;

[0110] Step S804, use the third non-uniform pulse PWM signal to scan each row of pixel circuits in the display panel;

[0111] Among them, the brightness of the scanned image in the first brightness scenario is greater than that of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform-width pulse PWM signal is less than the number of second-type pulses in the third non-uniform-width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform-width pulse PWM signal.

[0112] The non-uniform-width EM setting can be applied not only to the switching between high and low brightness DC and high-frequency PWM, but also to different PWM Pulse configurations in different scenarios. In one example, Special Scenario 1 (which can be AOD, i.e., Always On Display, always-on display) uses 8 Pulses, and Normal Display Scenario 2 uses 32 Pulses. Then both Scenario 1 and Scenario 2 use the non-uniform-width EM setting. As Figure 8b shown, it can also well reduce the duty difference during the PWM dimming switching between the two scenarios and weaken the switching flicker.

[0113] The embodiment of the present application also provides a display device. Refer to Figure 9 , the display device includes a display panel 1 and a display driving chip 2:

[0114] The display panel 1 includes a display module 12, and the display module 12 includes multiple pixel rows 121. Each pixel row 121 includes multiple pixel circuits 1211;

[0115] The display driving chip 2 is configured to: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generate a non-uniform-width pulse PWM signal, where the non-uniform-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; use the non-uniform-width pulse PWM signal to scan the pixel circuits 1211 in each pixel row 121 of the display panel;

[0116] The specific analysis is the same as above, and will not be elaborated here.

[0117] The display module 12 is configured to: in response to the scanning of the non-uniform-width pulse PWM signal, drive the pixel circuits 1211 in each pixel row 121.

[0118] The specific analysis is the same as above, and will not be elaborated here.

[0119] The display panel is used to receive the non-uniform width pulse PWM signal timing generated by the display driving chip, and through its own driving circuit, complete the timing scanning and transmission of each row of pixel rows, so as to realize the timing control and driving of non-uniform width pulses.

[0120] In the embodiment of the present application, by including a plurality of first type pulses and a plurality of second type pulses in the non-uniform width pulse PWM signal, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM.

[0121] In a possible implementation manner, for each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one of the first type pulses and a plurality of the second type pulses.

[0122] The specific analysis is the same as above, and will not be elaborated here.

[0123] In a possible implementation manner, the pulse width of the first type pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type pulse is the minimum width required for the timing of the display panel.

[0124] The specific analysis is the same as above, and will not be elaborated here.

[0125] In a possible implementation manner, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type pulse.

[0126] The specific analysis is the same as above, and will not be elaborated here.

[0127] In a possible implementation manner,

[0128] The display driving chip 2 is further configured to obtain the number of pulses within each frame of image refreshed, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and obtain the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timings of the first type of pulses according to the timings of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, wherein the timings of the reset signal, initialization signal, charging signal, and reset compensation signal are within the timings of the first type of pulses, and the timings of the first type of pulses are evenly arranged within the time of one frame of image; divide one frame of image into n sub-timing signals according to the number and timings of the first type of pulses, where n is the number of the first type of pulses, and for each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the head of the timings of the sub-timing signal; determine the timings and number of the second type of pulses in each sub-timing signal according to the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timings of the first type of pulses, the timings and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signals.

[0129] The specific analysis is the same as above and will not be elaborated here.

[0130] Examples of settings in the display driving chip are as follows: 1. According to the specification requirements, set the number of Pulses of EM, such as 12 Pulses, 16 Pulses, 24 Pulses, 32 Pulses, etc.

[0131] 2. According to the entire PWM timing duration determined by the resolution and porch time, artificially estimate the highest EM duty, such as 66.67% in the above embodiment, and set the corresponding parameters; and set the adjustment change rule of the duty (the minimum step number of increase, such as 4h, 8h, etc., evenly distributed to different Pulses), and output it to the driving circuit of the display panel itself.

[0132] 3. Output the scan-related signals according to the expected set timings, and ensure that the scan-related signals are within the expected EM high level, such as within the first EM high level.

[0133] The display driving chip 2 is specifically configured to: when converting from the direct current (DC) dimming mode to the pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

[0134] The specific analysis is the same as above and will not be elaborated here.

[0135] In a possible implementation manner, the display driving chip 2 is further configured to:

[0136] According to a preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal by a preset width to obtain a current PWM signal; use the current PWM signal to scan each row of pixel circuits in the display panel; return to execute the step: according to the preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal, or increase the pulse widths of the first type of pulses and the second type of pulses in the non-uniform-width pulse PWM signal to obtain a current PWM signal until the brightness of the scanned image under the current PWM signal is a specified brightness.

[0137] The specific analysis is the same as above and will not be elaborated here.

[0138] The display driving chip is used to generate a non-uniform-width pulse PWM signal and control the rule of the pulse width change in the PWM signal caused by the corresponding duty change.

[0139] In a possible implementation manner, the display driving chip 2 is further used for:

[0140] In the PWM dimming mode, in a first brightness scenario, generate a second non-uniform-width pulse PWM signal, where the second non-uniform-width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; use the second non-uniform-width pulse PWM signal to scan each row of pixel circuits in the display panel; when switching from the first brightness scenario to a second brightness scenario, generate a third non-uniform-width pulse PWM signal, where the third non-uniform-width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; use the third non-uniform-width pulse PWM signal to scan each row of pixel circuits in the display panel; where the brightness of the scanned image in the first brightness scenario is greater than the brightness of the scanned image in the second brightness scenario; the number of the second type of pulses in the second non-uniform-width pulse PWM signal is less than the number of the second type of pulses in the third non-uniform-width pulse PWM signal, and the total width of the second type of pulses in the second non-uniform-width pulse PWM signal is greater than the total width of the second type of pulses in the third non-uniform-width pulse PWM signal.

[0141] The specific analysis is the same as above and will not be elaborated here.

[0142] The embodiment of the present application further provides a display panel 3, see Figure 10 , the display panel 3 includes:

[0143] A driving module 31 and a display module 32, the display module 32 includes multiple rows of pixel rows 321, and each pixel row 321 includes a plurality of pixel circuits 3211;

[0144] The driving module 31 is configured to: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal, where the non-uniform width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses, both the first type pulses and the second type pulses are first level signals, the pulse width of the first type pulses is greater than the pulse width of the second type pulses, and the pulse width of the first type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; use the non-uniform width pulse PWM signal to scan the pixel circuits 3211 in each pixel row 321 of the display panel;

[0145] The display module 32 is configured to: in response to the scanning of the non-uniform width pulse PWM signal, drive the pixel circuits 3211 in each pixel row 321.

[0146] In a possible implementation manner, referring to Figure 11 , the display panel 3 further includes:

[0147] A driving configuration module 33, configured to obtain the number of pulses within each frame of image refreshed, the pulse width of the first type pulses, the pulse width of the second type pulses, and obtain the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timings of the first type pulses according to the timings of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type pulses, where the timings of the reset signal, initialization signal, charging signal, and reset compensation signal are within the timings of the first type pulses, and the timings of the first type pulses are evenly arranged within the time of one frame of image; divide one frame of image into n sub-timing signals according to the number and timings of the first type pulses, where n is the number of the first type pulses, for each sub-timing signal, the sub-timing signal includes one first type pulse and is located at the timing head of the sub-timing signal; determine the timings and number of the second type pulses in each sub-timing signal according to the number of pulses, the number of the first type pulses, and the pulse width of the second type pulses, to obtain the generation parameters of the PWM signal; where the generation parameters include the timings of the first type pulses, the timings and number of the second type pulses in each sub-timing signal, and the number of segments n of the sub-timing signals;

[0148] The driving module 31 is specifically configured to: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

[0149] In a possible implementation manner, the driving module 31 is further configured to:

[0150] According to a preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal by a preset width to obtain a current PWM signal; use the current PWM signal to scan each row of pixel circuits in the display panel; return to execute the step: according to the preset scanning period, increase the pulse width of the second type of pulses in the non-uniform-width pulse PWM signal, or increase the pulse widths of the first type of pulses and the second type of pulses in the non-uniform-width pulse PWM signal to obtain a current PWM signal until the brightness of the scanned image under the current PWM signal is a specified brightness.

[0151] In an embodiment of the present application, the display panel can generate a uniform-width pulse PWM signal through its own driving module, and can set the number of EM Pulses, the width of the EM pulse, etc. within different frames through its own driving configuration module.

[0152] In a possible implementation manner, the driving module 31 is further configured to:

[0153] In the PWM dimming mode, in a first brightness scenario, generate a second non-uniform-width pulse PWM signal, where the second non-uniform-width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses; use the second non-uniform-width pulse PWM signal to scan each row of pixel circuits in the display panel; when switching from the first brightness scenario to a second brightness scenario, generate a third non-uniform-width pulse PWM signal, where the third non-uniform-width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses; use the third non-uniform-width pulse PWM signal to scan each row of pixel circuits in the display panel; where the brightness of the scanned image in the first brightness scenario is greater than the brightness of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform-width pulse PWM signal is less than the number of second-type pulses in the third non-uniform-width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform-width pulse PWM signal.

[0154] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0155] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and reference can be made to the corresponding parts of the method embodiments for the relevant content.

[0156] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A method for driving a display panel, characterized in that, the method includes: When adjusting the brightness of the display panel using the direct current (DC) dimming mode, generating a pulse width modulation (PWM) signal with equal pulse widths, and the PWM signal with equal pulse widths does not include the second type of pulses; In response to the dimming mode being switched from the DC dimming mode to the pulse width modulation (PWM) dimming mode, generating a PWM signal with unequal pulse widths, wherein the PWM signal with unequal pulse widths includes a plurality of first type of pulses and a plurality of second type of pulses, both the first type of pulses and the second type of pulses are first-level signals, the pulse width of the first type of pulses is greater than the pulse width of the second type of pulses, and the pulse width of the first type of pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel. During the dimming process of the PWM dimming mode, as the brightness decreases, the duty cycle of the PWM signal will decrease accordingly; there are a plurality of the second type of pulses between every two adjacent first type of pulses, and the pulse widths of the same type of pulses are the same; the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulses; Scanning each row of pixel circuits in the display panel using the PWM signal with unequal pulse widths; According to a preset scanning period, increasing the pulse width of the second type of pulses in the PWM signal with unequal pulse widths by a preset width to obtain the current PWM signal; scanning each row of pixel circuits in the display panel using the current PWM signal; The method further includes: obtaining the number of pulses within each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and obtaining the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; Determining the number and timing of the first type of pulses according to the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame; Determining the timing and number of the second type of pulses in each sub-timing signal in the image frame according to the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timing, number of the second type of pulses, and the number of segments n of the sub-timing signal, and the PWM signal with unequal pulse widths is generated according to the generation parameters.

2. The method according to claim 1, characterized in that, For each frame of the PWM signal with unequal pulse widths, the frame of the PWM signal with unequal pulse widths includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type of pulse and a plurality of second type of pulses.

3. The method according to claim 1, characterized in that, The pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuits in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing sequence of the display panel.

4. The method according to claim 1, wherein, the method further comprises: dividing one frame of image frame into n sub-timing signals according to the number and timing sequence of the first type of pulses, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing head of the sub-timing signal; The generating of the non-uniform width pulse PWM signal in response to the dimming mode being switched from the DC dimming mode to the pulse width modulation PWM dimming mode includes: in response to the dimming mode being switched from the DC dimming mode to the pulse width modulation PWM dimming mode, generating a non-uniform width pulse PWM signal according to the generating parameters.

5. The method according to claim 1, wherein, the method further comprises: in the PWM dimming mode, in a first brightness scene, generating a second non-uniform width pulse PWM signal, wherein the second non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; scanning each row of pixel circuits in the display panel by using the second non-uniform width pulse PWM signal; after switching from the first brightness scene to a second brightness scene, generating a third non-uniform width pulse PWM signal, wherein the third non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; scanning each row of pixel circuits in the display panel by using the third non-uniform width pulse PWM signal; wherein the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of the second type of pulses in the second non-uniform width pulse PWM signal is less than the number of the second type of pulses in the third non-uniform width pulse PWM signal, and the total width of the second type of pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second type of pulses in the third non-uniform width pulse PWM signal.

6. A display device, wherein, the display device comprises a display panel and a display driving chip: the display panel comprises a display module, and the display module comprises a plurality of pixel rows, and each pixel row comprises a plurality of pixel circuits; The display driving chip is configured to: when adjusting the brightness of the display panel by using a direct current (DC) dimming mode, generate a pulse-width modulation (PWM) signal with equal pulse widths, where the PWM signal with equal pulse widths does not include second-type pulses; in response to the dimming mode being switched from the DC dimming mode to the PWM dimming mode, generate a PWM signal with unequal pulse widths, where the PWM signal with unequal pulse widths includes a plurality of first-type pulses and a plurality of second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel. During the dimming process in the PWM dimming mode, as the brightness decreases, the duty cycle of the PWM signal decreases accordingly; there are a plurality of second-type pulses between every two adjacent first-type pulses, and the pulse widths of the pulses of the same type are the same; the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit are within the timing of the first-type pulses; and scan the pixel circuits in each pixel row in the display panel by using the PWM signal with unequal pulse widths. The display module is configured to: in response to the scanning of the PWM signal with unequal pulse widths, drive the pixel circuits in each pixel row. The display driving chip is configured to: according to a preset scanning period, increase the pulse width of the second-type pulses in the PWM signal with unequal pulse widths by a preset width to obtain a current PWM signal; and scan the pixel circuits in each row in the display panel by using the current PWM signal. The display driving chip is further configured to: obtain the number of pulses within each frame of image refreshed, the pulse width of the first-type pulses, the pulse width of the second-type pulses, and obtain the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timing of the first-type pulses according to the timings of the reset signal, initialization signal, charging signal, and reset compensation signal and the pulse width of the first-type pulses, where the timings of the reset signal, initialization signal, charging signal, and reset compensation signal are within the timing of the first-type pulses, and the timing of the first-type pulses is evenly arranged within the time of one frame of image; determine the timing and number of the second-type pulses in each sub-timing signal in the image frame according to the number of pulses, the number of the first-type pulses, and the pulse width of the second-type pulses to obtain the generation parameters of the PWM signal; where the generation parameters include the timing and number of the first-type pulses and the second-type pulses in each sub-timing signal, and the number of segments n of the sub-timing signal, and the PWM signal with unequal pulse widths is generated according to the generation parameters.

7. The display device according to claim 6, wherein, For each frame of the PWM signal with unequal pulse widths, the frame of the PWM signal with unequal pulse widths includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and a plurality of second-type pulses.

8. The display device according to claim 6, wherein, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuits in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing sequence of the display panel.

9. The display device according to claim 6, wherein, the display driving chip is further configured to divide a frame of image frame into n sub-timing signals according to the number and timing sequence of the first type of pulses, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the head of the timing sequence of the sub-timing signal; the display driving chip is specifically configured to: in response to the dimming mode being switched from the DC dimming mode to the pulse width modulation PWM dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters.

10. The display device according to claim 6, wherein, the display driving chip is further configured to: in the PWM dimming mode, in a first brightness scenario, generate a second non-uniform width pulse PWM signal, where the second non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; use the second non-uniform width pulse PWM signal to scan each row of pixel circuits in the display panel; when switching from the first brightness scenario to a second brightness scenario, generate a third non-uniform width pulse PWM signal, where the third non-uniform width pulse PWM signal includes a plurality of first type of pulses and a plurality of second type of pulses; use the third non-uniform width pulse PWM signal to scan each row of pixel circuits in the display panel; wherein, the brightness of the scanned image in the first brightness scenario is greater than the brightness of the scanned image in the second brightness scenario; the number of the second type of pulses in the second non-uniform width pulse PWM signal is less than the number of the second type of pulses in the third non-uniform width pulse PWM signal, and the total width of the second type of pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second type of pulses in the third non-uniform width pulse PWM signal.

11. A display panel, wherein, the display panel includes: a driving module and a display module, the display module includes multiple rows of pixel rows, and each row of pixel rows includes a plurality of pixel circuits; The driving module is configured to: generate a pulse-width modulation (PWM) signal with equal pulse widths when adjusting the brightness of the display panel using a direct current (DC) dimming mode, where the PWM signal with equal pulse widths does not include second-type pulses; in response to a conversion of the dimming mode from the DC dimming mode to the PWM dimming mode, generate a PWM signal with unequal pulse widths, where the PWM signal with unequal pulse widths includes a plurality of first-type pulses and a plurality of second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel. During the dimming process in the PWM dimming mode, as the brightness decreases, the duty cycle of the PWM signal will decrease accordingly; there are a plurality of second-type pulses between every two adjacent first-type pulses, and the pulse widths of the same type of pulses are the same; the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit are within the timing of the first-type pulses; scan the pixel circuits in each pixel row in the display panel using the PWM signal with unequal pulse widths; The display module is configured to: drive the pixel circuits in each pixel row in response to the scanning of the PWM signal with unequal pulse widths; The driving module is configured to: increase the pulse width of the second-type pulses in the PWM signal with unequal pulse widths by a preset width according to a preset scanning period to obtain a current PWM signal; scan the pixel circuits in each row in the display panel using the current PWM signal; The driving module is further configured to: obtain the number of pulses within each frame of image refreshed, the pulse width of the first-type pulses, the pulse width of the second-type pulses, and obtain the timings of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timing of the first-type pulses according to the timings of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first-type pulses, where the timings of the reset signal, initialization signal, charging signal, and reset compensation signal are within the timing of the first-type pulses, and the timings of the first-type pulses are evenly arranged within the time of one frame of image; determine the timing and number of the second-type pulses in each sub-timing signal in the image frame according to the number of pulses, the number of the first-type pulses, and the pulse width of the second-type pulses to obtain the generation parameters of the PWM signal; where the generation parameters include the timings and number of the first-type pulses, the timings and number of the second-type pulses, and the number of segments n of the sub-timing signals in each segment, and the PWM signal with unequal pulse widths is generated according to the generation parameters.

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